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Searched refs:FIELD_PREP (Results 1 – 25 of 36) sorted by relevance

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/Zephyr-Core-3.5.0/drivers/can/
Dcan_stm32_fdcan.c279 *val |= FIELD_PREP(CAN_MCAN_IR_ARA, FIELD_GET(CAN_STM32FD_IR_ARA, bits)); in can_stm32fd_read_reg()
280 *val |= FIELD_PREP(CAN_MCAN_IR_PED, FIELD_GET(CAN_STM32FD_IR_PED, bits)); in can_stm32fd_read_reg()
281 *val |= FIELD_PREP(CAN_MCAN_IR_PEA, FIELD_GET(CAN_STM32FD_IR_PEA, bits)); in can_stm32fd_read_reg()
282 *val |= FIELD_PREP(CAN_MCAN_IR_WDI, FIELD_GET(CAN_STM32FD_IR_WDI, bits)); in can_stm32fd_read_reg()
283 *val |= FIELD_PREP(CAN_MCAN_IR_BO, FIELD_GET(CAN_STM32FD_IR_BO, bits)); in can_stm32fd_read_reg()
284 *val |= FIELD_PREP(CAN_MCAN_IR_EW, FIELD_GET(CAN_STM32FD_IR_EW, bits)); in can_stm32fd_read_reg()
285 *val |= FIELD_PREP(CAN_MCAN_IR_EP, FIELD_GET(CAN_STM32FD_IR_EP, bits)); in can_stm32fd_read_reg()
286 *val |= FIELD_PREP(CAN_MCAN_IR_ELO, FIELD_GET(CAN_STM32FD_IR_ELO, bits)); in can_stm32fd_read_reg()
287 *val |= FIELD_PREP(CAN_MCAN_IR_TOO, FIELD_GET(CAN_STM32FD_IR_TOO, bits)); in can_stm32fd_read_reg()
288 *val |= FIELD_PREP(CAN_MCAN_IR_MRAF, FIELD_GET(CAN_STM32FD_IR_MRAF, bits)); in can_stm32fd_read_reg()
[all …]
Dcan_sja1000_priv.h98 #define CAN_SJA1000_BTR0_BRP_PREP(brp) FIELD_PREP(CAN_SJA1000_BTR0_BRP_MASK, brp)
99 #define CAN_SJA1000_BTR0_SJW_PREP(sjw) FIELD_PREP(CAN_SJA1000_BTR0_SJW_MASK, sjw)
106 #define CAN_SJA1000_BTR1_TSEG1_PREP(tseg1) FIELD_PREP(CAN_SJA1000_BTR1_TSEG1_MASK, tseg1)
107 #define CAN_SJA1000_BTR1_TSEG2_PREP(tseg2) FIELD_PREP(CAN_SJA1000_BTR1_TSEG2_MASK, tseg2)
114 #define CAN_SJA1000_ECC_ERRC_BIT_ERROR FIELD_PREP(CAN_SJA1000_ECC_ERRC_MASK, 0U)
115 #define CAN_SJA1000_ECC_ERRC_FORM_ERROR FIELD_PREP(CAN_SJA1000_ECC_ERRC_MASK, 1U)
116 #define CAN_SJA1000_ECC_ERRC_STUFF_ERROR FIELD_PREP(CAN_SJA1000_ECC_ERRC_MASK, 2U)
117 #define CAN_SJA1000_ECC_ERRC_OTHER_ERROR FIELD_PREP(CAN_SJA1000_ECC_ERRC_MASK, 3U)
124 #define CAN_SJA1000_FRAME_INFO_DLC_PREP(dlc) FIELD_PREP(CAN_SJA1000_FRAME_INFO_DLC_MASK, dlc)
Dcan_mcp251xfd.c36 dst->id = FIELD_PREP(MCP251XFD_OBJ_ID_SID_MASK, src->id >> 18); in mcp251xfd_canframe_to_txobj()
37 dst->id |= FIELD_PREP(MCP251XFD_OBJ_ID_EID_MASK, src->id); in mcp251xfd_canframe_to_txobj()
41 dst->id = FIELD_PREP(MCP251XFD_OBJ_ID_SID_MASK, src->id); in mcp251xfd_canframe_to_txobj()
48 dst->flags |= FIELD_PREP(MCP251XFD_OBJ_FLAGS_DLC_MASK, src->dlc); in mcp251xfd_canframe_to_txobj()
54 dst->flags |= FIELD_PREP(MCP251XFD_OBJ_FLAGS_SEQ_MASK, mailbox_idx); in mcp251xfd_canframe_to_txobj()
307 *reg = FIELD_PREP(MCP251XFD_REG_TDC_TDCMOD_MASK, MCP251XFD_REG_TDC_TDCMOD_AUTO); in mcp251xfd_set_tdc()
308 *reg |= FIELD_PREP(MCP251XFD_REG_TDC_TDCO_MASK, tdc_offset); in mcp251xfd_set_tdc()
310 *reg = FIELD_PREP(MCP251XFD_REG_TDC_TDCMOD_MASK, MCP251XFD_REG_TDC_TDCMOD_DISABLED); in mcp251xfd_set_tdc()
357 reg_con |= FIELD_PREP(MCP251XFD_REG_CON_REQOP_MASK, requested_mode); in mcp251xfd_set_mode_internal()
368 dev, MCP251XFD_REG_CON, FIELD_PREP(MCP251XFD_REG_CON_OPMOD_MASK, requested_mode), in mcp251xfd_set_mode_internal()
[all …]
Dcan_esp32_twai.c35 #define TWAI_BAUD_PRESC_PREP(brp) FIELD_PREP(TWAI_BAUD_PRESC_MASK, brp)
36 #define TWAI_SYNC_JUMP_WIDTH_PREP(sjw) FIELD_PREP(TWAI_SYNC_JUMP_WIDTH_MASK, sjw)
46 #define TWAI_TIME_SEG1_PREP(seg1) FIELD_PREP(TWAI_TIME_SEG1_MASK, seg1)
47 #define TWAI_TIME_SEG2_PREP(seg2) FIELD_PREP(TWAI_TIME_SEG2_MASK, seg2)
Dcan_mcan.c209 nbtp |= FIELD_PREP(CAN_MCAN_NBTP_NSJW, timing->sjw - 1UL) | in can_mcan_set_timing()
210 FIELD_PREP(CAN_MCAN_NBTP_NTSEG1, timing->phase_seg1 - 1UL) | in can_mcan_set_timing()
211 FIELD_PREP(CAN_MCAN_NBTP_NTSEG2, timing->phase_seg2 - 1UL) | in can_mcan_set_timing()
212 FIELD_PREP(CAN_MCAN_NBTP_NBRP, timing->prescaler - 1UL); in can_mcan_set_timing()
238 dbtp |= FIELD_PREP(CAN_MCAN_DBTP_DSJW, timing_data->sjw - 1UL) | in can_mcan_set_timing_data()
239 FIELD_PREP(CAN_MCAN_DBTP_DTSEG1, timing_data->phase_seg1 - 1UL) | in can_mcan_set_timing_data()
240 FIELD_PREP(CAN_MCAN_DBTP_DTSEG2, timing_data->phase_seg2 - 1UL) | in can_mcan_set_timing_data()
241 FIELD_PREP(CAN_MCAN_DBTP_DBRP, timing_data->prescaler - 1UL); in can_mcan_set_timing_data()
1254 reg = (addr & CAN_MCAN_SIDFC_FLSSA) | FIELD_PREP(CAN_MCAN_SIDFC_LSS,
1262 reg = (addr & CAN_MCAN_XIDFC_FLESA) | FIELD_PREP(CAN_MCAN_XIDFC_LSS,
[all …]
Dcan_sja1000.c286 frame->id = FIELD_PREP(GENMASK(28, 21), in can_sja1000_read_frame()
288 frame->id |= FIELD_PREP(GENMASK(20, 13), in can_sja1000_read_frame()
290 frame->id |= FIELD_PREP(GENMASK(12, 5), in can_sja1000_read_frame()
292 frame->id |= FIELD_PREP(GENMASK(4, 0), in can_sja1000_read_frame()
302 frame->id = FIELD_PREP(GENMASK(10, 3), in can_sja1000_read_frame()
304 frame->id |= FIELD_PREP(GENMASK(2, 0), in can_sja1000_read_frame()
/Zephyr-Core-3.5.0/drivers/sensor/icm42688/
Dicm42688_common.c76 FIELD_PREP(MASK_FIFO_MODE, BIT_FIFO_MODE_BYPASS)); in icm42688_configure()
84 FIELD_PREP(BIT_FIFO_FLUSH, 1)); in icm42688_configure()
95 uint8_t pwr_mgmt0 = FIELD_PREP(MASK_GYRO_MODE, cfg->gyro_mode) | in icm42688_configure()
96 FIELD_PREP(MASK_ACCEL_MODE, cfg->accel_mode) | in icm42688_configure()
97 FIELD_PREP(BIT_TEMP_DIS, cfg->temp_dis); in icm42688_configure()
112 uint8_t accel_config0 = FIELD_PREP(MASK_ACCEL_ODR, cfg->accel_odr) | in icm42688_configure()
113 FIELD_PREP(MASK_ACCEL_UI_FS_SEL, cfg->accel_fs); in icm42688_configure()
122 uint8_t gyro_config0 = FIELD_PREP(MASK_GYRO_ODR, cfg->gyro_odr) | in icm42688_configure()
123 FIELD_PREP(MASK_GYRO_UI_FS_SEL, cfg->gyro_fs); in icm42688_configure()
139 uint8_t fifo_config_bypass = FIELD_PREP(MASK_FIFO_MODE, BIT_FIFO_MODE_BYPASS); in icm42688_configure()
[all …]
Dicm42688_spi.c87 temp |= FIELD_PREP(mask, data); in icm42688_spi_update_register()
/Zephyr-Core-3.5.0/include/zephyr/drivers/can/
Dcan_sja1000.h30 #define CAN_SJA1000_OCR_OCMODE_BIPHASE FIELD_PREP(CAN_SJA1000_OCR_OCMODE_MASK, 0U)
31 #define CAN_SJA1000_OCR_OCMODE_TEST FIELD_PREP(CAN_SJA1000_OCR_OCMODE_MASK, 1U)
32 #define CAN_SJA1000_OCR_OCMODE_NORMAL FIELD_PREP(CAN_SJA1000_OCR_OCMODE_MASK, 2U)
33 #define CAN_SJA1000_OCR_OCMODE_CLOCK FIELD_PREP(CAN_SJA1000_OCR_OCMODE_MASK, 3U)
48 #define CAN_SJA1000_CDR_CD_DIV1 FIELD_PREP(CAN_SJA1000_CDR_CD_MASK, 7U)
49 #define CAN_SJA1000_CDR_CD_DIV2 FIELD_PREP(CAN_SJA1000_CDR_CD_MASK, 0U)
50 #define CAN_SJA1000_CDR_CD_DIV4 FIELD_PREP(CAN_SJA1000_CDR_CD_MASK, 1U)
51 #define CAN_SJA1000_CDR_CD_DIV6 FIELD_PREP(CAN_SJA1000_CDR_CD_MASK, 2U)
52 #define CAN_SJA1000_CDR_CD_DIV8 FIELD_PREP(CAN_SJA1000_CDR_CD_MASK, 3U)
53 #define CAN_SJA1000_CDR_CD_DIV10 FIELD_PREP(CAN_SJA1000_CDR_CD_MASK, 4U)
[all …]
/Zephyr-Core-3.5.0/drivers/dai/intel/dmic/
Ddmic_nhlt.c285 val |= FIELD_PREP(DMICLVSCTL_MLCS, source); in dai_dmic_clock_select_set()
290 val |= FIELD_PREP(DMICLCTL_MLCS, source); in dai_dmic_clock_select_set()
458 ref = FIELD_PREP(OUTCONTROL_TIE, bf1) | FIELD_PREP(OUTCONTROL_SIP, bf2) | in print_outcontrol()
459 FIELD_PREP(OUTCONTROL_FINIT, bf3) | FIELD_PREP(OUTCONTROL_FCI, bf4) | in print_outcontrol()
460 FIELD_PREP(OUTCONTROL_BFTH, bf5) | FIELD_PREP(OUTCONTROL_OF, bf6) | in print_outcontrol()
461 FIELD_PREP(OUTCONTROL_IPM, bf7) | FIELD_PREP(OUTCONTROL_IPM_SOURCE_1, bf9) | in print_outcontrol()
462 FIELD_PREP(OUTCONTROL_IPM_SOURCE_2, bf10) | in print_outcontrol()
463 FIELD_PREP(OUTCONTROL_IPM_SOURCE_3, bf11) | in print_outcontrol()
464 FIELD_PREP(OUTCONTROL_IPM_SOURCE_4, bf12) | FIELD_PREP(OUTCONTROL_TH, bf8) | in print_outcontrol()
465 FIELD_PREP(OUTCONTROL_IPM_SOURCE_MODE, bf13); in print_outcontrol()
[all …]
Ddmic.c143 FIELD_PREP(DMICLCTL_OSEL, 0x3), dmic->shim_base + DMICLCTL_OFFSET); in dai_dmic_claim_ownership()
176 sys_write32(sys_read32(base + DMICSYNC_OFFSET) | FIELD_PREP(DMICSYNC_SYNCPRD, val), in dai_dmic_set_sync_period()
189 sys_write32(sys_read32(base + DMICSYNC_OFFSET) | FIELD_PREP(DMICSYNC_SYNCPRD, val), in dai_dmic_set_sync_period()
422 cdmas = FIELD_PREP(TS_LOCAL_TSCTRL_CDMAS, cfg->dma_chan_index + in dai_timestamp_dmic_start()
531 val = FIELD_PREP(OUT_GAIN, gval); in dai_dmic_gain_ramp()
595 FIELD_PREP(CIC_CONTROL_CIC_START_A, 1) | in dai_dmic_start()
596 FIELD_PREP(CIC_CONTROL_CIC_START_B, 1)); in dai_dmic_start()
600 FIELD_PREP(MIC_CONTROL_PDM_EN_A, 1) | in dai_dmic_start()
601 FIELD_PREP(MIC_CONTROL_PDM_EN_B, 1)); in dai_dmic_start()
605 FIELD_PREP(CIC_CONTROL_CIC_START_A, 1)); in dai_dmic_start()
[all …]
/Zephyr-Core-3.5.0/include/zephyr/sensing/
Dsensing.h52 (FIELD_PREP(GENMASK(31, 24), _major) | \
53 FIELD_PREP(GENMASK(23, 16), _minor) | \
54 FIELD_PREP(GENMASK(15, 8), _hotfix) | \
55 FIELD_PREP(GENMASK(7, 0), _build))
/Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/ace/
Dcomm_widget.h776 uint32_t attr = FIELD_PREP(USATTR_DSTPID, dest) | FIELD_PREP(USATTR_FID, func) | in cw_upstream_set_attr()
777 FIELD_PREP(USATTR_OPC, opcode) | FIELD_PREP(USATTR_BE, be) | in cw_upstream_set_attr()
778 FIELD_PREP(USATTR_BAR, bar); in cw_upstream_set_attr()
828 cmd |= FIELD_PREP(USCMD_MSGTYP, CW_TRANSACTION_POSTED) | in cw_upstream_do_pw()
829 FIELD_PREP(USCMD_TRANTYP, CW_TRANSACTION_WRITE) | in cw_upstream_do_pw()
Dcomm_widget_messages.c22 uint32_t iface = FIELD_PREP(CW_PMC_IPC_OP_CODE, CW_PMC_OPC_SRAM_CONFIG) | in adsp_comm_widget_pmc_send_ipc()
23 FIELD_PREP(CW_PMC_IPC_SRAM_USED_BANKS, banks) | in adsp_comm_widget_pmc_send_ipc()
/Zephyr-Core-3.5.0/drivers/counter/
Dcounter_ace_v1x_art.c23 val |= FIELD_PREP(ACE_TSCTRL_IONTE_MASK, new_timestamp_enable); in counter_ace_v1x_art_ionte_set()
33 val |= FIELD_PREP(ACE_TSCTRL_CDMAS_MASK, cdmas); in counter_ace_v1x_art_cdmas_set()
43 val |= FIELD_PREP(ACE_TSCTRL_NTK_MASK, new_timestamp_taken); in counter_ace_v1x_art_ntk_set()
58 val |= FIELD_PREP(ACE_TSCTRL_HHTSE_MASK, enable); in counter_ace_v1x_art_hhtse_set()
/Zephyr-Core-3.5.0/drivers/led_strip/
Dtlc5971.c101 return FIELD_PREP(TLC5971_BYTE27_WRITE_CMD_MASK, TLC5971_WRITE_COMMAND) | in tlc5971_data_byte27()
102 FIELD_PREP(TLC5971_BYTE27_CTRL_MASK, control_data); in tlc5971_data_byte27()
114 return FIELD_PREP(TLC5971_BYTE26_CTRL_MASK, control_data) | in tlc5971_data_byte26()
115 FIELD_PREP(TLC5971_BYTE26_GBC1_MASK, gbc_color_1 >> 2); in tlc5971_data_byte26()
127 return FIELD_PREP(TLC5971_BYTE25_GBC1_MASK, gbc_color_1 << 6) | in tlc5971_data_byte25()
128 FIELD_PREP(TLC5971_BYTE25_GBC2_MASK, gbc_color_2 >> 1); in tlc5971_data_byte25()
140 return FIELD_PREP(TLC5971_BYTE24_GBC2_MASK, gbc_color_2 << 7) | in tlc5971_data_byte24()
141 FIELD_PREP(TLC5971_BYTE24_GBC3_MASK, gbc_color_3); in tlc5971_data_byte24()
/Zephyr-Core-3.5.0/soc/arm/xilinx_zynq7000/common/
Dpinctrl_soc.h20 #define MIO_PIN_DISABLE_RCVR(val) FIELD_PREP(MIO_PIN_DISABLE_RCVR_MASK, val)
23 #define MIO_PIN_PULLUP(val) FIELD_PREP(MIO_PIN_PULLUP_MASK, val)
26 #define MIO_PIN_IO_TYPE(val) FIELD_PREP(MIO_PIN_IO_TYPE_MASK, val)
29 #define MIO_PIN_SPEED(val) FIELD_PREP(MIO_PIN_SPEED_MASK, val)
32 #define MIO_PIN_L3_SEL(val) FIELD_PREP(MIO_PIN_L3_SEL_MASK, val)
35 #define MIO_PIN_L2_SEL(val) FIELD_PREP(MIO_PIN_L2_SEL_MASK, val)
38 #define MIO_PIN_L1_SEL(val) FIELD_PREP(MIO_PIN_L1_SEL_MASK, val)
41 #define MIO_PIN_L0_SEL(val) FIELD_PREP(MIO_PIN_L0_SEL_MASK, val)
44 #define MIO_PIN_TRI_ENABLE(val) FIELD_PREP(MIO_PIN_TRI_ENABLE_MASK, val)
/Zephyr-Core-3.5.0/drivers/w1/
Dw1_ds2477_85_common.h144 #define RPUP_BUF_SW_TH_PREP(x) FIELD_PREP(RPUP_BUF_SW_TH_Msk, x)
150 #define RPUP_BUF_APULL_TH_PREP(x) FIELD_PREP(RPUP_BUF_APULL_TH_Msk, x)
156 #define RPUP_BUF_WPULL_PREP(x) FIELD_PREP(RPUP_BUF_WPULL_Msk, x)
165 #define PDSLEW_STD_PREP(x) FIELD_PREP(PDSLEW_STD_Msk, BIT(x))
170 #define PDSLEW_OVD_PREP(x) FIELD_PREP(PDSLEW_OVD_Msk, BIT(x))
/Zephyr-Core-3.5.0/drivers/dac/
Ddac_ltc166x.c32 regval = FIELD_PREP(LTC166X_REG_MASK, addr); in ltc166x_reg_write()
35 regval |= FIELD_PREP(LTC166X_DATA10_MASK, data); in ltc166x_reg_write()
37 regval |= FIELD_PREP(LTC166X_DATA8_MASK, data); in ltc166x_reg_write()
/Zephyr-Core-3.5.0/drivers/watchdog/
Dwdt_dw.h348 control |= FIELD_PREP(WDT_CR_RPL, pclk_cycles); in dw_wdt_reset_pulse_length_set()
364 timeout |= FIELD_PREP(WDT_TORR_TOP, timeout_period); in dw_wdt_timeout_period_set()
391 timeout |= FIELD_PREP(WDT_TORR_TOP_INIT, timeout_period); in dw_wdt_timeout_period_init_set()
Dwdt_intel_adsp.h96 control |= FIELD_PREP(DSPCxWDTCS_PCODE, DSPCxWDTCS_PCODE_VALUE); in intel_adsp_wdt_pause()
/Zephyr-Core-3.5.0/drivers/serial/
Duart_pl011_ambiq.h43 get_uart(dev)->cr |= FIELD_PREP(PL011_CR_AMBIQ_CLKSEL, clksel); in pl011_ambiq_clk_set()
/Zephyr-Core-3.5.0/drivers/pwm/
Dpwm_max31790.c75 *destination |= FIELD_PREP(GENMASK(pos + length - 1, pos), value); in max31790_set_fandynamics_speedrange()
84 *destination |= FIELD_PREP(GENMASK(pos + length - 1, pos), value); in max31790_set_fandynamics_pwmrateofchange()
93 *destination |= FIELD_PREP(GENMASK(pos + length - 1, pos), value); in max31790_set_pwmfrequency()
110 *destination |= FIELD_PREP(GENMASK(pos + length - 1, pos), value); in max31790_set_fanconfiguration_spinup()
/Zephyr-Core-3.5.0/drivers/ethernet/
Deth_smsc91x.c315 smsc_write_2(sc, MMUCR, FIELD_PREP(MMUCR_CMD_MASK, MMUCR_CMD_MMU_RESET)); in smsc_reset()
327 FIELD_PREP(RPCR_LSA_MASK, RPCR_LED_LINK_ANY) | in smsc_enable()
328 FIELD_PREP(RPCR_LSB_MASK, RPCR_LED_ACT_ANY)); in smsc_enable()
465 smsc_write_2(sc, MMUCR, FIELD_PREP(MMUCR_CMD_MASK, MMUCR_CMD_RELEASE)); in smsc_recv_pkt()
486 smsc_write_2(sc, MMUCR, FIELD_PREP(MMUCR_CMD_MASK, MMUCR_CMD_TX_ALLOC)); in smsc_send_pkt()
536 smsc_write_2(sc, MMUCR, FIELD_PREP(MMUCR_CMD_MASK, MMUCR_CMD_ENQUEUE)); in smsc_send_pkt()
598 FIELD_PREP(MMUCR_CMD_MASK, MMUCR_CMD_RELEASE_PKT)); in smsc_isr_task()
/Zephyr-Core-3.5.0/drivers/flash/
Dflash_cadence_qspi_nor_ll.h31 #define CAD_QSPI_CFG_BAUDDIV(x) FIELD_PREP(0x780000, x)
65 #define CAD_QSPI_FLASHCMD_NUM_DUMMYBYTES(x) (FIELD_PREP(0x000f80, (x)))

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