1 #ifndef ETH_CYCLONEV_HEADER 2 #define ETH_CYCLONEV_HEADER 3 /* 4 * SPDX-License-Identifier: Apache-2.0 5 * Copyright (C) 2022, Intel Corporation 6 * Description: 7 * Driver for the Synopsys DesignWare 8 * 3504-0 Universal 10/100/1000 Ethernet MAC (DWC_gmac) 9 * specifically designed for Cyclone V SoC DevKit use only. 10 */ 11 12 #include <zephyr/kernel.h> 13 #include <zephyr/types.h> 14 15 #define alt_replbits_word(dest, msk, src) \ 16 (sys_write32((sys_read32(dest) & ~(msk)) | ((src) & (msk)), dest)) 17 18 #define NB_TX_DESCS CONFIG_ETH_CVSX_NB_TX_DESCS 19 #define NB_RX_DESCS CONFIG_ETH_CVSX_NB_RX_DESCS 20 21 #define ETH_BUFFER_SIZE 1536 22 23 /* Descriptor Structure */ 24 struct eth_cyclonev_dma_desc { 25 uint32_t status; /*!< Status */ 26 uint32_t control_buffer_size; /*!< Control and Buffer1, Buffer2 sizes */ 27 uint32_t buffer1_addr; /*!< Buffer1 address pointer */ 28 uint32_t buffer2_next_desc_addr; /*!< Buffer2 or next desc address pointer */ 29 }; 30 31 struct eth_cyclonev_priv { 32 mem_addr_t base_addr; /* Base address */ 33 uint8_t mac_addr[6]; 34 uint32_t interrupt_mask; 35 struct net_if *iface; /* Zephyr net_if Interface Struct (for interface initialisation) */ 36 uint32_t tx_current_desc_number; 37 uint32_t rx_current_desc_number; 38 uint32_t tx_tail; 39 40 uint32_t feature; /* HW feature register */ 41 /* Tx/Rx Descriptor Rings */ 42 struct eth_cyclonev_dma_desc tx_desc_ring[NB_TX_DESCS], rx_desc_ring[NB_RX_DESCS]; 43 uint32_t rxints; /* Tx stats */ 44 uint32_t txints; /* Rx stats */ 45 uint8_t rx_buf[ETH_BUFFER_SIZE * NB_RX_DESCS]; /* Receive Buffer */ 46 uint8_t tx_buf[ETH_BUFFER_SIZE * NB_TX_DESCS]; /* Transmit Buffer */ 47 48 struct k_sem free_tx_descs; 49 uint8_t running; /* Running state flag */ 50 uint8_t initialised; /* Initialised state flag */ 51 }; 52 53 /* 54 * Reset Manager Regs 55 */ 56 /* The base address of the Rstmgr register group. */ 57 #define RSTMGR_BASE 0xffd05000 58 59 /* The byte offset of the ALT_RSTMGR_PERMODRST register from the beginning of 60 * the component. 61 */ 62 #define RSTMGR_PERMODRST_OFST 0x14 63 /* The address of the ALT_RSTMGR_PERMODRST register. */ 64 #define RSTMGR_PERMODRST_ADDR 0xFFD05014 65 /* The mask used to set the ALT_RSTMGR_PERMODRST_EMAC0 register field value. */ 66 #define RSTMGR_PERMODRST_EMAC0_SET_MSK 0x00000001 67 /* The mask used to set the ALT_RSTMGR_PERMODRST_EMAC1 register field value. */ 68 #define RSTMGR_PERMODRST_EMAC1_SET_MSK 0x00000002 69 70 /* 71 * System Manager Regs 72 */ 73 #define SYSMGR_BASE 0xffd08000 74 #define SYSMGR_EMAC_ADDR 0xffd08060 75 #define SYSMGR_FPGAINTF_INDIV_ADDR 0xffd08004 76 77 /* The byte offset of the SYSMGR_EMAC register from the beginning of the 78 * component. 79 */ 80 #define SYSMGR_EMAC_OFST 0x60 81 /* The byte offset of the SYSMGR_FPGAINTF_INDIV register from the beginning of 82 * the component. 83 */ 84 #define SYSMGR_FPGAINTF_INDIV_OFST 0x4 85 /* 86 * Enumerated value for register field ALT_SYSMGR_EMACn_PHY_INTF_SEL 87 * 88 */ 89 #define SYSMGR_EMAC_PHY_INTF_SEL_E_GMII_MII 0x0 90 /* 91 * Enumerated value for register field ALT_SYSMGR_EMACn_PHY_INTF_SEL 92 * 93 */ 94 #define SYSMGR_EMAC0_PHY_INTF_SEL_E_RGMII 0x1 95 #define SYSMGR_EMAC1_PHY_INTF_SEL_E_RGMII 0x4 96 /* 97 * Enumerated value for register field ALT_SYSMGR_EMACn_PHY_INTF_SEL 98 * 99 */ 100 #define SYSMGR_EMAC_PHY_INTF_SEL_E_RMII 0x2 101 102 /* The mask used to set the ALT_SYSMGR_EMACn_PHY_INTF_SEL register field value. 103 */ 104 #define SYSMGR_EMAC0_PHY_INTF_SEL_SET_MSK 0x00000003 105 #define SYSMGR_EMAC1_PHY_INTF_SEL_SET_MSK 0x0000000c 106 107 /* The mask used to set the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0 register field 108 * value. 109 */ 110 #define SYSMGR_FPGAINTF_MODULE_EMAC_0_SET_MSK 0x00000004 111 112 /* The mask used to set the ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1 register field 113 * value. 114 */ 115 #define SYSMGR_FPGAINTF_MODULE_EMAC_1_SET_MSK 0x00000008 116 117 /* 118 * Emac Registers 119 */ 120 /* Macros */ 121 #define EMAC_BASE_ADDRESS DT_INST_REG_ADDR(0) 122 123 #define EMAC_DMAGRP_BUS_MODE_ADDR(base) (uint32_t)((base) + EMAC_DMA_MODE_OFST) /* Bus Mode */ 124 #define EMAC_DMA_RX_DESC_LIST_ADDR(base) (uint32_t)((base) + EMAC_DMA_RX_DESC_LIST_OFST) 125 /* Receive Descriptor Address List */ 126 #define EMAC_DMA_TX_DESC_LIST_ADDR(base) (uint32_t)((base) + EMAC_DMA_TX_DESC_LIST_OFST) 127 /* Transceive Descriptor Address List */ 128 #define EMAC_DMAGRP_OPERATION_MODE_ADDR(base) (uint32_t)((base) + EMAC_DMAGRP_OPERATION_MODE_OFST) 129 /* Operation Mode */ 130 #define EMAC_DMAGRP_STATUS_ADDR(base) (uint32_t)((base) + EMAC_DMAGRP_STATUS_OFST) /* Status */ 131 #define EMAC_DMAGRP_DEBUG_ADDR(base) (uint32_t)((base) + EMAC_DMAGRP_DEBUG_OFST) /* Debug */ 132 #define EMAC_DMA_INT_EN_ADDR(base) (uint32_t)((base) + EMAC_DMA_INT_EN_OFST) 133 /* Interrupt Enable */ 134 #define EMAC_DMAGRP_AXI_BUS_MODE_ADDR(base) (uint32_t)((base) + EMAC_DMAGRP_AXI_BUS_MODE_OFST) 135 /* AXI Bus Mode */ 136 #define EMAC_DMAGRP_AHB_OR_AXI_STATUS_ADDR(base) \ 137 (uint32_t)((base) + EMAC_DMAGRP_AHB_OR_AXI_STATUS_OFST) 138 /* AHB or AXI Status */ 139 #define GMACGRP_CONTROL_STATUS_ADDR(base) \ 140 (uint32_t)((base) + \ 141 EMAC_GMACGRP_SGMII_RGMII_SMII_CONTROL_STATUS_OFST) \ 142 /* SGMII RGMII SMII Control Status */ 143 #define EMAC_GMAC_INT_MSK_ADDR(base) (uint32_t)((base) + EMAC_GMAC_INT_MSK_OFST) 144 /* Interrupt Mask */ 145 #define EMAC_GMAC_INT_STAT_ADDR(base) (uint32_t)((base) + EMAC_GMAC_INT_STAT_OFST) 146 /* Interrupt Status */ 147 #define GMACGRP_MAC_CONFIG_ADDR(base) (uint32_t)((base) + EMAC_GMACGRP_MAC_CONFIGURATION_OFST) 148 /* MAC Configuration */ 149 #define EMAC_GMACGRP_MAC_FRAME_FILTER_ADDR(base) \ 150 (uint32_t)((base) + EMAC_GMACGRP_MAC_FRAME_FILTER_OFST) 151 /* MAC Frame Filter */ 152 #define EMAC_GMAC_MAC_ADDR0_HIGH_ADDR(base) (uint32_t)((base) + EMAC_GMAC_MAC_ADDR0_HIGH_OFST) 153 /* MAC Address 0 High */ 154 #define EMAC_GMAC_MAC_ADDR0_LOW_ADDR(base) (uint32_t)((base) + EMAC_GMAC_MAC_ADDR0_LOW_OFST) 155 /* MAC Address 0 Low */ 156 #define EMAC_GMAC_MAC_ADDR_HIGH_ADDR(base, n) (uint32_t)((base) + EMAC_GMAC_MAC_ADDR_HIGH_OFST(n)) 157 /* MAC Address 0 High */ 158 #define EMAC_GMAC_MAC_ADDR_LOW_ADDR(base, n) (uint32_t)((base) + EMAC_GMAC_MAC_ADDR_LOW_OFST(n)) 159 /* MAC Address 0 High */ 160 #define EMAC_GMAC_GMII_ADDR_ADDR(base) (uint32_t)((base) + EMAC_GMAC_GMII_ADDR_OFST) 161 /* GMII Address */ 162 #define EMAC_GMAC_GMII_DATA_ADDR(base) (uint32_t)((base) + EMAC_GMAC_GMII_DATA_OFST) 163 /* GMII Data */ 164 #define EMAC_DMA_TX_POLL_DEMAND_ADDR(base) (uint32_t)((base) + EMAC_DMA_TX_POLL_DEMAND_OFST) 165 /* Transmit Poll Demand */ 166 #define EMAC_DMA_RX_POLL_DEMAND_ADDR(base) (uint32_t)((base) + EMAC_DMA_RX_POLL_DEMAND_OFST) 167 /* Receive Poll Demand */ 168 #define EMAC_DMA_CURR_HOST_TX_DESC_ADDR(base) (uint32_t)((base) + EMAC_DMA_CURR_HOST_TX_DESC_OFST) 169 /* Current Host Transmit Descriptor */ 170 #define EMAC_DMA_CURR_HOST_RX_DESC_ADDR(base) (uint32_t)((base) + EMAC_DMA_CURR_HOST_RX_DESC_OFST) 171 /* Current Host Receive Descriptor */ 172 #define EMAC_DMA_CURR_HOST_TX_BUFF_ADDR(base) (uint32_t)((base) + EMAC_DMA_CURR_HOST_TX_BUFF_OFST) 173 /* Current Host Transmit Buffer Address */ 174 #define EMAC_DMA_CURR_HOST_RX_BUFF_ADDR(base) (uint32_t)((base) + EMAC_DMA_CURR_HOST_RX_BUFF_OFST) 175 /* Current Host Receive Buffer Address */ 176 #define EMAC_DMA_HW_FEATURE_ADDR(base) (uint32_t)((base) + EMAC_DMA_HW_FEATURE_OFST) 177 /* HW Feature */ 178 179 /* Bus Mode */ 180 #define EMAC_DMA_MODE_OFST 0x1000 181 #define EMAC_DMA_MODE_SWR_SET_MSK 0x00000001 182 #define EMAC_DMA_MODE_SWR_GET(value) (((value)&0x00000001) >> 0) 183 #define EMAC_DMA_MODE_FB_SET_MSK 0x00010000 184 #define EMAC_DMA_MODE_RPBL_SET(value) (((value) << 17) & 0x007e0000) 185 #define EMAC_DMA_MODE_PBL_SET(value) (((value) << 8) & 0x00003f00) 186 #define EMAC_DMA_MODE_EIGHTXPBL_SET(value) (((value) << 24) & 0x01000000) 187 #define EMAC_DMA_MODE_AAL_SET_MSK 0x02000000 188 #define EMAC_DMA_MODE_USP_SET_MSK 0x00800000 189 190 /* Receive Descriptor Address List */ 191 #define EMAC_DMA_RX_DESC_LIST_OFST 0x100c 192 193 /* Transceive Descriptor Address List */ 194 #define EMAC_DMA_TX_DESC_LIST_OFST 0x1010 195 196 /* Operation Mode */ 197 #define EMAC_DMAGRP_OPERATION_MODE_OFST 0x1018 198 #define EMAC_DMAGRP_OPERATION_MODE_OSF_SET_MSK 0x00000004 /* Operate on Second Frame */ 199 #define EMAC_DMAGRP_OPERATION_MODE_TSF_SET_MSK 0x00200000 /* Transmit Store and Forward */ 200 #define EMAC_DMAGRP_OPERATION_MODE_RSF_SET_MSK 0x02000000 /* Receive Store and Forward */ 201 #define EMAC_DMAGRP_OPERATION_MODE_FTF_SET_MSK 0x00100000 /* Receive Store and Forward */ 202 #define EMAC_DMAGRP_OPERATION_MODE_ST_SET_MSK 0x00002000 203 #define EMAC_DMAGRP_OPERATION_MODE_SR_SET_MSK 0x00000002 204 #define EMAC_DMAGRP_OPERATION_MODE_DT_SET_MSK 0x04000000 /* Ignore frame errors */ 205 206 /* Interrupt Enable */ 207 #define EMAC_DMA_INT_EN_OFST 0x101C 208 #define EMAC_DMA_INT_EN_NIE_SET_MSK 0x00010000 209 #define EMAC_DMA_INT_EN_AIE_SET_MSK 0x00008000 210 #define EMAC_DMA_INT_EN_ERE_SET_MSK 0x00004000 211 #define EMAC_DMA_INT_EN_FBE_SET_MSK 0x00002000 212 #define EMAC_DMA_INT_EN_ETE_SET_MSK 0x00000400 213 #define EMAC_DMA_INT_EN_RWE_SET_MSK 0x00000200 214 #define EMAC_DMA_INT_EN_RSE_SET_MSK 0x00000100 215 #define EMAC_DMA_INT_EN_RUE_SET_MSK 0x00000080 216 #define EMAC_DMA_INT_EN_RIE_SET_MSK 0x00000040 217 #define EMAC_DMA_INT_EN_UNE_SET_MSK 0x00000020 218 #define EMAC_DMA_INT_EN_OVE_SET_MSK 0x00000010 219 #define EMAC_DMA_INT_EN_TJE_SET_MSK 0x00000008 220 #define EMAC_DMA_INT_EN_TUE_SET_MSK 0x00000004 221 #define EMAC_DMA_INT_EN_TSE_SET_MSK 0x00000002 222 #define EMAC_DMA_INT_EN_TIE_SET_MSK 0x00000001 223 224 /* Status */ 225 #define EMAC_DMAGRP_STATUS_OFST 0x1014 226 #define EMAC_DMAGRP_STATUS_TS_SET_MSK 0x00700000 227 #define EMAC_DMAGRP_STATUS_TS_E_SUSPTX 0x00600000 228 #define EMAC_DMAGRP_STATUS_RS_SET_MSK 0x000e0000 229 #define EMAC_DMAGRP_STATUS_RS_E_SUSPRX 0x00080000 230 231 #define EMAC_DMAGRP_DEBUG_OFST 0x24 232 #define EMAC_DMAGRP_DEBUG_TWCSTS 0x00400000 233 #define EMAC_DMAGRP_DEBUG_RWCSTS 0x00000010 234 #define EMAC_DMAGRP_DEBUG_RXFSTS_GET(value) (((value)&0x00000300) >> 8) 235 236 /* AXI Bus Mode */ 237 #define EMAC_DMAGRP_AXI_BUS_MODE_OFST 0x1028 238 #define EMAC_DMAGRP_AXI_BUS_MODE_BLEN16_SET_MSK 0x00000008 239 240 /* AHB or AXI Status */ 241 #define EMAC_DMAGRP_AHB_OR_AXI_STATUS_OFST 0x102c 242 243 /* MAC Configuration */ 244 245 #define EMAC_GMACGRP_MAC_CONFIGURATION_OFST 0x0000 246 #define EMAC_GMACGRP_MAC_CONFIGURATION_IPC_SET_MSK 0x00000400 247 #define EMAC_GMACGRP_MAC_CONFIGURATION_JD_SET_MSK 0x00400000 /* Jabber Disable */ 248 #define EMAC_GMACGRP_MAC_CONFIGURATION_PS_SET_MSK 0x00008000 /* Port Select = MII */ 249 #define EMAC_GMACGRP_MAC_CONFIGURATION_BE_SET_MSK 0x00200000 /* Frame Burst Enable */ 250 #define EMAC_GMACGRP_MAC_CONFIGURATION_WD_SET_MSK 0x00800000 /* Watchdog Disable */ 251 #define EMAC_GMACGRP_MAC_CONFIGURATION_DO_SET_MSK 0x00002000 252 #define EMAC_GMACGRP_MAC_CONFIGURATION_TE_SET_MSK 0x00000008 253 #define EMAC_GMACGRP_MAC_CONFIGURATION_RE_SET_MSK 0x00000004 254 #define EMAC_GMACGRP_MAC_CONFIGURATION_TC_SET_MSK 0x01000000 255 256 #define EMAC_GMACGRP_MAC_CONFIGURATION_DM_SET_MSK 0x00000800 257 #define EMAC_GMACGRP_MAC_CONFIGURATION_FES_SET_MSK 0x00004000 258 259 /* SGMII RGMII SMII Control Status */ 260 #define EMAC_GMACGRP_SGMII_RGMII_SMII_CONTROL_STATUS_OFST 0x00d8 261 #define EMAC_GMAC_MII_CTL_STAT_LNKSTS_GET(value) (((value)&0x00000008) >> 3) 262 #define EMAC_GMAC_MII_CTL_STAT_LNKSPEED_GET(value) (((value)&0x00000007) >> 1) 263 #define EMAC_GMAC_MII_CTL_STAT_LNKMOD_GET(value) ((value)&0x00000001) 264 265 /* Interrupt Mask */ 266 #define EMAC_GMAC_INT_MSK_OFST 0x003c 267 #define EMAC_GMAC_INT_STAT_LPIIS_SET_MSK 0x00000400 268 #define EMAC_GMAC_INT_STAT_TSIS_SET_MSK 0x00000200 269 #define EMAC_GMAC_INT_STAT_RGSMIIIS_SET_MSK 0x00000001 270 271 /* Interrupt Status (Gmac)*/ 272 #define EMAC_GMAC_INT_STAT_OFST 0x0038 273 274 /* MAC Frame Filter */ 275 #define EMAC_GMACGRP_MAC_FRAME_FILTER_OFST 0x0004 276 #define EMAC_GMACGRP_MAC_FRAME_FILTER_PR_SET_MSK 0x00000001 277 278 /* MAC Address 0 High */ 279 #define EMAC_GMAC_MAC_ADDR0_HIGH_OFST 0x40 280 #define EMAC_GMAC_MAC_ADDR_HIGH_OFST(n) (0x40 + 8 * (n)) 281 /* MAC Address 0 Low */ 282 #define EMAC_GMAC_MAC_ADDR0_LOW_OFST 0x44 283 #define EMAC_GMAC_MAC_ADDR_LOW_OFST(n) (0x44 + 8 * (n)) 284 285 /* GMII Address */ 286 #define EMAC_GMAC_GMII_ADDR_OFST 0x10 287 #define EMAC_GMAC_GMII_ADDR_PA_SET(value) (((value) << 11) & 0x0000f800) 288 #define EMAC_GMAC_GMII_ADDR_GR_SET(value) (((value) << 6) & 0x000007c0) 289 #define EMAC_GMAC_GMII_ADDR_GW_SET_MSK 0x00000002 290 #define EMAC_GMAC_GMII_ADDR_GW_CLR_MSK 0xfffffffd 291 #define EMAC_GMAC_GMII_ADDR_CR_SET(value) (((value) << 2) & 0x0000003c) 292 #define EMAC_GMAC_GMII_ADDR_GB_SET(value) (((value) << 0) & 0x00000001) 293 #define EMAC_GMAC_GMII_ADDR_CR_E_DIV102 0x4 294 #define EMAC_GMAC_GMII_ADDR_GB_SET_MSK 0x00000001 295 296 /* GMII Data */ 297 #define EMAC_GMAC_GMII_DATA_OFST 0x14 298 299 /* Transmit Poll Demand */ 300 #define EMAC_DMA_TX_POLL_DEMAND_OFST 0x1004 301 302 /* Receive Poll Demand */ 303 #define EMAC_DMA_RX_POLL_DEMAND_OFST 0x1008 304 305 /* Current Host Transmit Descriptor */ 306 #define EMAC_DMA_CURR_HOST_TX_DESC_OFST 0x1048 307 308 /* Current Host Receive Descriptor */ 309 #define EMAC_DMA_CURR_HOST_RX_DESC_OFST 0x104C 310 311 /* Current Host Transmit Buffer Address */ 312 #define EMAC_DMA_CURR_HOST_TX_BUFF_OFST 0x1050 313 314 /* Current Host Receive Buffer Address */ 315 #define EMAC_DMA_CURR_HOST_RX_BUFF_OFST 0x1054 316 317 /* HW Feature */ 318 #define EMAC_DMA_HW_FEATURE_OFST 0x1058 319 #define EMAC_DMA_HW_FEATURE_MIISEL 0x00000001 /* 10/100 Mbps support */ 320 #define EMAC_DMA_HW_FEATURE_GMIISEL 0x00000002 /* 1000 Mbps support */ 321 #define EMAC_DMA_HW_FEATURE_HDSEL 0x00000004 /* Half-Duplex support */ 322 #define EMAC_DMA_HW_FEATURE_RXTYP2COE 0x00040000 /* IP Checksum Offload (Type 2) in Rx */ 323 #define EMAC_DMA_HW_FEATURE_RXTYP1COE 0x00020000 /* IP Checksum Offload (Type 1) in Rx */ 324 #define EMAC_DMA_HW_FEATURE_TXOESEL 0x00010000 /* Checksum Offload in Tx */ 325 326 /* 327 * DMA Descriptor Flag Definitions 328 */ 329 330 /* 331 * DMA Rx Descriptor 332 * ------------------------------------------------------------------------------------------- 333 * RDES0 | OWN(31) | Status [30:0] | 334 * ------------------------------------------------------------------------------------------- 335 * RDES1 |CTRL(31)|Reserv[30:29]|Buff2ByteCt[28:16]|CTRL[15:14] 336 * Reservr(13)|Buff1ByteCt[12:0]| 337 * ------------------------------------------------------------------------------------------- 338 * RDES2 | Buffer1 Address [31:0] | 339 * -------------------------------------------------------------------------------------------- 340 * RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] 341 * | 342 * -------------------------------------------------------------------------------------------- 343 */ 344 345 /* Bit definition of RDES0 register: DMA Rx descriptor status register */ 346 #define ETH_DMARXDESC_OWN ((uint32_t)0x80000000) 347 /*!< OWN bit: descriptor is owned by DMA engine */ 348 #define ETH_DMARXDESC_AFM ((uint32_t)0x40000000) 349 /*!< DA Filter Fail for the rx frame */ 350 #define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000) 351 /*!< Receive descriptor frame length */ 352 #define ETH_DMARXDESC_ES ((uint32_t)0x00008000) 353 /*!< Error summary: OR of the following bits: 354 * DE || OE || IPC || LC || RWT || RE || CE 355 */ 356 #define ETH_DMARXDESC_DE ((uint32_t)0x00004000) 357 /*!< Descriptor error: no more descriptors for receive frame */ 358 #define ETH_DMARXDESC_SAF ((uint32_t)0x00002000) 359 /*!< SA Filter Fail for the received frame */ 360 #define ETH_DMARXDESC_LE ((uint32_t)0x00001000) 361 /*!< Frame size not matching with length field */ 362 #define ETH_DMARXDESC_OE ((uint32_t)0x00000800) 363 /*!< Overflow Error: Frame was damaged due to buffer overflow */ 364 #define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400) 365 /*!< VLAN Tag: received frame is a VLAN frame */ 366 #define ETH_DMARXDESC_FS ((uint32_t)0x00000200) 367 /*!< First descriptor of the frame */ 368 #define ETH_DMARXDESC_LS ((uint32_t)0x00000100) 369 /*!< Last descriptor of the frame */ 370 #define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080) 371 /*!< IPC Checksum Error: Rx Ipv4 header checksum error */ 372 #define ETH_DMARXDESC_LC ((uint32_t)0x00000040) 373 /*!< Late collision occurred during reception */ 374 #define ETH_DMARXDESC_FT ((uint32_t)0x00000020) 375 /*!< Frame type - Ethernet, otherwise 802.3 */ 376 #define ETH_DMARXDESC_RWT ((uint32_t)0x00000010) 377 /*!< Receive Watchdog Timeout: watchdog timer expired during reception */ 378 #define ETH_DMARXDESC_RE ((uint32_t)0x00000008) 379 /*!< Receive error: error reported by MII interface */ 380 #define ETH_DMARXDESC_DBE ((uint32_t)0x00000004) 381 /*!< Dribble bit error: frame contains non int multiple of 8 bits */ 382 #define ETH_DMARXDESC_CE ((uint32_t)0x00000002) 383 /*!< CRC error */ 384 #define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001) 385 /* !< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ 386 * Rx Payload Checksum Error 387 */ 388 389 /* Bit definition of RDES1 register */ 390 #define ETH_DMARXDESC_DIC ((uint32_t)0x80000000) /*!< Disable Interrupt on Completion */ 391 #define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000) /*!< Receive Buffer2 Size */ 392 #define ETH_DMARXDESC_RER ((uint32_t)0x00008000) /*!< Receive End of Ring */ 393 #define ETH_DMARXDESC_RCH \ 394 ((uint32_t)0x00004000) /*!< Second Address Chained \ 395 */ 396 #define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFF) /*!< Receive Buffer1 Size */ 397 398 /* 399 *DMA Tx Descriptor 400 *----------------------------------------------------------------------------------------------- 401 *TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | 402 *Reserved[19:17] | Status[16:0] | 403 *----------------------------------------------------------------------------------------------- 404 *TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 405 *ByteCount[12:0] | 406 *----------------------------------------------------------------------------------------------- 407 *TDES2 | Buffer1 Address [31:0] 408 *| 409 *----------------------------------------------------------------------------------------------- 410 *TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] 411 *| 412 *----------------------------------------------------------------------------------------------- 413 */ 414 415 /* Bit definition of TDES0 register: DMA Tx descriptor status register */ 416 #define ETH_DMATXDESC_OWN ((uint32_t)0x80000000) 417 /*!< OWN bit: descriptor is owned by DMA engine */ 418 #define ETH_DMATXDESC_IC ((uint32_t)0x40000000) 419 /*!< Interrupt on Completion */ 420 #define ETH_DMATXDESC_LS ((uint32_t)0x20000000) 421 /*!< Last Segment */ 422 #define ETH_DMATXDESC_FS ((uint32_t)0x10000000) 423 /*!< First Segment */ 424 #define ETH_DMATXDESC_DC ((uint32_t)0x08000000) 425 /*!< Disable CRC */ 426 #define ETH_DMATXDESC_DP ((uint32_t)0x04000000) 427 /*!< Disable Padding */ 428 #define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000) 429 /*!< Transmit Time Stamp Enable */ 430 #define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000) 431 /*!< Checksum Insertion Control: 4 cases */ 432 #define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000) 433 /*!< Do Nothing: Checksum Engine is bypassed */ 434 #define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000) 435 /*!< IPV4 header Checksum Insertion */ 436 #define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000) 437 /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ 438 #define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000) 439 /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ 440 #define ETH_DMATXDESC_TER ((uint32_t)0x00200000) 441 /*!< Transmit End of Ring */ 442 #define ETH_DMATXDESC_TCH ((uint32_t)0x00100000) 443 /*!< Second Address Chained */ 444 #define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000) 445 /*!< Tx Time Stamp Status */ 446 #define ETH_DMATXDESC_IHE ((uint32_t)0x00010000) 447 /*!< IP Header Error */ 448 #define ETH_DMATXDESC_ES ((uint32_t)0x00008000) 449 /*!< Error summary: OR of the following bits: UE||ED||EC||LCO||NC||LCA||FF||JT 450 */ 451 #define ETH_DMATXDESC_JT ((uint32_t)0x00004000) 452 /*!< Jabber Timeout */ 453 #define ETH_DMATXDESC_FF ((uint32_t)0x00002000) 454 /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */ 455 #define ETH_DMATXDESC_PCE ((uint32_t)0x00001000) 456 /*!< Payload Checksum Error */ 457 #define ETH_DMATXDESC_LCA ((uint32_t)0x00000800) 458 /*!< Loss of Carrier: carrier lost during transmission */ 459 #define ETH_DMATXDESC_NC ((uint32_t)0x00000400) 460 /*!< No Carrier: no carrier signal from the transceiver */ 461 #define ETH_DMATXDESC_LCO ((uint32_t)0x00000200) 462 /*!< Late Collision: transmission aborted due to collision */ 463 #define ETH_DMATXDESC_EC ((uint32_t)0x00000100) 464 /*!< Excessive Collision: transmission aborted after 16 collisions */ 465 #define ETH_DMATXDESC_VF ((uint32_t)0x00000080) 466 /*!< VLAN Frame */ 467 #define ETH_DMATXDESC_CC ((uint32_t)0x00000078) 468 /*!< Collision Count */ 469 #define ETH_DMATXDESC_ED ((uint32_t)0x00000004) 470 /*!< Excessive Deferral */ 471 #define ETH_DMATXDESC_UF ((uint32_t)0x00000002) 472 /*!< Underflow Error: late data arrival from the memory */ 473 #define ETH_DMATXDESC_DB ((uint32_t)0x00000001) 474 /*!< Deferred Bit */ 475 476 /* Bit definition of TDES1 register */ 477 #define ETH_DMATXDESC_TBS2 \ 478 ((uint32_t)0x1FFF0000) /*!< Transmit Buffer2 Size \ 479 */ 480 #define ETH_DMATXDESC_TBS1 \ 481 ((uint32_t)0x00001FFF) /*!< Transmit Buffer1 Size \ 482 */ 483 484 /* Bit definition of TDES2 register */ 485 #define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */ 486 487 /* Bit definition of TDES3 register */ 488 #define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */ 489 490 491 static const uint32_t Rstmgr_Permodrst_Emac_Set_Msk[] = {RSTMGR_PERMODRST_EMAC0_SET_MSK, 492 RSTMGR_PERMODRST_EMAC1_SET_MSK}; 493 494 static const uint32_t Sysmgr_Core_Emac_Phy_Intf_Sel_Set_Msk[] = {SYSMGR_EMAC0_PHY_INTF_SEL_SET_MSK, 495 SYSMGR_EMAC1_PHY_INTF_SEL_SET_MSK}; 496 497 static const uint32_t Sysmgr_Fpgaintf_En_3_Emac_Set_Msk[] = {SYSMGR_FPGAINTF_MODULE_EMAC_0_SET_MSK, 498 SYSMGR_FPGAINTF_MODULE_EMAC_1_SET_MSK}; 499 500 static const uint32_t Sysmgr_Emac_Phy_Intf_Sel_E_Rgmii[] = {SYSMGR_EMAC0_PHY_INTF_SEL_E_RGMII, 501 SYSMGR_EMAC1_PHY_INTF_SEL_E_RGMII}; 502 503 #endif 504
