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Searched refs:DT_REG_ADDR (Results 1 – 25 of 258) sorted by relevance

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/Zephyr-Core-3.5.0/soc/arm64/nxp_imx/mimx9/
Dmmu_regions.c24 DT_REG_ADDR(DT_NODELABEL(ccm)),
29 DT_REG_ADDR(DT_NODELABEL(ana_pll)),
34 DT_REG_ADDR(DT_NODELABEL(lpuart2)),
39 DT_REG_ADDR(DT_NODELABEL(iomuxc)),
45 DT_REG_ADDR(DT_NODELABEL(mu2_a)),
50 DT_REG_ADDR(DT_NODELABEL(sai3)),
55 DT_REG_ADDR(DT_NODELABEL(edma2_ch0)),
60 DT_REG_ADDR(DT_NODELABEL(edma2_ch1)),
65 DT_REG_ADDR(DT_NODELABEL(outbox)),
70 DT_REG_ADDR(DT_NODELABEL(inbox)),
[all …]
/Zephyr-Core-3.5.0/soc/arm/st_stm32/stm32h7/
Dsections.ld12 . = ABSOLUTE(DT_REG_ADDR(DT_NODELABEL(sram3)));
14 . = ABSOLUTE(DT_REG_ADDR(DT_NODELABEL(sram3))) + 256;
16 . = ABSOLUTE(DT_REG_ADDR(DT_NODELABEL(sram3))) + 16K;
20 . = ABSOLUTE(DT_REG_ADDR(DT_NODELABEL(sram2)));
22 . = ABSOLUTE(DT_REG_ADDR(DT_NODELABEL(sram2))) + 256;
24 . = ABSOLUTE(DT_REG_ADDR(DT_NODELABEL(sram2))) + 16K;
Dmpu_regions.c27 DT_REG_ADDR(DT_NODELABEL(sram3)),
30 DT_REG_ADDR(DT_NODELABEL(sram3)),
34 DT_REG_ADDR(DT_NODELABEL(sram2)),
37 DT_REG_ADDR(DT_NODELABEL(sram2)),
/Zephyr-Core-3.5.0/soc/arc/snps_emsk/
Dsoc_config.c21 sys_write32(0, DT_REG_ADDR(DT_INST(0, ns16550))+0x4); in uart_ns16550_init()
22 sys_write32(0, DT_REG_ADDR(DT_INST(0, ns16550))+0x10); in uart_ns16550_init()
25 sys_write32(0, DT_REG_ADDR(DT_INST(1, ns16550))+0x4); in uart_ns16550_init()
26 sys_write32(0, DT_REG_ADDR(DT_INST(1, ns16550))+0x10); in uart_ns16550_init()
/Zephyr-Core-3.5.0/boards/arc/emsdp/
Darc_mpu_regions.c14 DT_REG_ADDR(DT_INST(0, arc_iccm)),
19 DT_REG_ADDR(DT_INST(0, arc_dccm)),
25 DT_REG_ADDR(DT_INST(0, arc_xccm)),
32 DT_REG_ADDR(DT_INST(0, arc_yccm)),
38 DT_REG_ADDR(DT_INST(0, mmio_sram)),
/Zephyr-Core-3.5.0/boards/arc/nsim/
Darc_mpu_regions.c30 DT_REG_ADDR(DT_INST(0, arc_iccm)),
37 DT_REG_ADDR(DT_INST(0, arc_dccm)),
44 DT_REG_ADDR(DT_INST(0, arc_xccm)),
51 DT_REG_ADDR(DT_INST(0, arc_yccm)),
62 DT_REG_ADDR(DT_CHOSEN(zephyr_sram)),
81 DT_REG_ADDR(DT_CHOSEN(zephyr_flash)),
/Zephyr-Core-3.5.0/boards/arc/em_starterkit/
Darc_mpu_regions.c19 DT_REG_ADDR(DT_INST(0, arc_iccm)),
26 DT_REG_ADDR(DT_INST(0, arc_dccm)),
34 DT_REG_ADDR(DT_INST(0, arc_xccm)),
41 DT_REG_ADDR(DT_INST(0, arc_yccm)),
49 DT_REG_ADDR(DT_INST(0, mmio_sram)),
/Zephyr-Core-3.5.0/soc/arm64/nxp_imx/mimx8m/
Dmmu_regions.c24 DT_REG_ADDR(DT_NODELABEL(ccm)),
29 DT_REG_ADDR(DT_NODELABEL(uart2)),
34 DT_REG_ADDR(DT_NODELABEL(ana_pll)),
39 DT_REG_ADDR(DT_NODELABEL(uart4)),
44 DT_REG_ADDR(DT_NODELABEL(iomuxc)),
/Zephyr-Core-3.5.0/boards/arm/mps2_an521/
Dpinmux.c32 ((volatile struct gpio_cmsdk_ahb *)DT_REG_ADDR(DT_NODELABEL(gpio0)))
34 ((volatile struct gpio_cmsdk_ahb *)DT_REG_ADDR(DT_NODELABEL(gpio1)))
36 ((volatile struct gpio_cmsdk_ahb *)DT_REG_ADDR(DT_NODELABEL(gpio2)))
38 ((volatile struct gpio_cmsdk_ahb *)DT_REG_ADDR(DT_NODELABEL(gpio3)))
/Zephyr-Core-3.5.0/soc/arm/xilinx_zynq7000/xc7zxxxs/
Dsoc.c21 DT_REG_ADDR(id),\
36 DT_REG_ADDR(DT_CHOSEN(zephyr_ocm)),
44 DT_REG_ADDR(DT_NODELABEL(gem0)),
50 DT_REG_ADDR(DT_NODELABEL(gem1)),
58 DT_REG_ADDR(DT_NODELABEL(psgpio)),
110 mm_reg_t addr = DT_REG_ADDR(DT_NODELABEL(slcr)); in z_arm_platform_init()
/Zephyr-Core-3.5.0/soc/arm/xilinx_zynq7000/xc7zxxx/
Dsoc.c21 DT_REG_ADDR(id),\
36 DT_REG_ADDR(DT_CHOSEN(zephyr_ocm)),
44 DT_REG_ADDR(DT_NODELABEL(gem0)),
50 DT_REG_ADDR(DT_NODELABEL(gem1)),
58 DT_REG_ADDR(DT_NODELABEL(psgpio)),
110 mm_reg_t addr = DT_REG_ADDR(DT_NODELABEL(slcr)); in z_arm_platform_init()
/Zephyr-Core-3.5.0/boards/arm/mps2_an385/
Dpinmux.c32 ((volatile struct gpio_cmsdk_ahb *)DT_REG_ADDR(DT_NODELABEL(gpio0)))
34 ((volatile struct gpio_cmsdk_ahb *)DT_REG_ADDR(DT_NODELABEL(gpio1)))
36 ((volatile struct gpio_cmsdk_ahb *)DT_REG_ADDR(DT_NODELABEL(gpio2)))
38 ((volatile struct gpio_cmsdk_ahb *)DT_REG_ADDR(DT_NODELABEL(gpio3)))
/Zephyr-Core-3.5.0/drivers/pinctrl/
Dpinctrl_kinetis.c15 (PORT_Type *)DT_REG_ADDR(DT_NODELABEL(porta)),
16 (PORT_Type *)DT_REG_ADDR(DT_NODELABEL(portb)),
17 (PORT_Type *)DT_REG_ADDR(DT_NODELABEL(portc)),
19 (PORT_Type *)DT_REG_ADDR(DT_NODELABEL(portd)),
22 (PORT_Type *)DT_REG_ADDR(DT_NODELABEL(porte)),
62 DT_REG_ADDR(DT_INST_PHANDLE(n, clocks)) + DT_INST_CLOCKS_CELL(n, name)
Dpinctrl_rv32m1.c17 (PORT_Type *)DT_REG_ADDR(DT_NODELABEL(porta)),
18 (PORT_Type *)DT_REG_ADDR(DT_NODELABEL(portb)),
19 (PORT_Type *)DT_REG_ADDR(DT_NODELABEL(portc)),
20 (PORT_Type *)DT_REG_ADDR(DT_NODELABEL(portd)),
21 (PORT_Type *)DT_REG_ADDR(DT_NODELABEL(porte)),
/Zephyr-Core-3.5.0/boards/arc/iotdk/
Darc_mpu_regions.c14 DT_REG_ADDR(DT_INST(0, arc_iccm)),
19 DT_REG_ADDR(DT_INST(0, arc_dccm)),
25 DT_REG_ADDR(DT_INST(0, arc_xccm)),
32 DT_REG_ADDR(DT_INST(0, arc_yccm)),
/Zephyr-Core-3.5.0/soc/arm/microchip_mec/mec172x/
Ddevice_power.c16 ((struct adc_regs *)(DT_REG_ADDR(DT_NODELABEL(adc0))))
18 ((struct ecia_named_regs *)(DT_REG_ADDR(DT_NODELABEL(ecia))))
20 ((struct ecs_regs *)(DT_REG_ADDR(DT_NODELABEL(ecs))))
22 ((struct peci_regs *)(DT_REG_ADDR(DT_NODELABEL(peci0))))
24 ((struct pcr_regs *)(DT_REG_ADDR(DT_NODELABEL(pcr))))
26 ((struct tfdp_regs *)(DT_REG_ADDR(DT_NODELABEL(tfdp0))))
28 ((struct uart_regs *)(DT_REG_ADDR(DT_NODELABEL(uart0))))
30 ((struct uart_regs *)(DT_REG_ADDR(DT_NODELABEL(uart1))))
34 ((uintptr_t)(DT_REG_ADDR(DT_NODELABEL(bbram))))
36 #define BTMR16_0_ADDR DT_REG_ADDR(DT_NODELABEL(timer0))
[all …]
/Zephyr-Core-3.5.0/include/zephyr/devicetree/
Dspi.h151 DT_GPIO_CTLR_BY_IDX(DT_BUS(spi_dev), cs_gpios, DT_REG_ADDR(spi_dev))
192 DT_GPIO_LABEL_BY_IDX(DT_BUS(spi_dev), cs_gpios, DT_REG_ADDR(spi_dev)) __DEPRECATED_MACRO
225 DT_GPIO_PIN_BY_IDX(DT_BUS(spi_dev), cs_gpios, DT_REG_ADDR(spi_dev))
253 DT_GPIO_FLAGS_BY_IDX(DT_BUS(spi_dev), cs_gpios, DT_REG_ADDR(spi_dev))
/Zephyr-Core-3.5.0/soc/arm/st_stm32/stm32h5/
Dsections.ld12 . = ABSOLUTE(DT_REG_ADDR(DT_NODELABEL(sram3)));
14 . = ABSOLUTE(DT_REG_ADDR(DT_NODELABEL(sram3))) + 256;
16 . = ABSOLUTE(DT_REG_ADDR(DT_NODELABEL(sram3))) + 16K;
/Zephyr-Core-3.5.0/soc/arm64/intel_socfpga/agilex/
Dmmu_regions.c15 DT_REG_ADDR(DT_NODELABEL(sysmgr)),
20 DT_REG_ADDR(DT_NODELABEL(clock)),
25 DT_REG_ADDR(DT_NODELABEL(uart0)),
/Zephyr-Core-3.5.0/soc/x86/raptor_lake/
Dsoc.h30 #define X86_SOC_EARLY_SERIAL_PCIDEV DT_REG_ADDR(DT_CHOSEN(zephyr_console))
32 #define X86_SOC_EARLY_SERIAL_MMIO8_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_console))
/Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/common/include/
Dintel_adsp_ipc_devtree.h28 #define INTEL_ADSP_IPC_REG_ADDRESS DT_REG_ADDR(INTEL_ADSP_IPC_HOST_DTNODE)
40 #define INTEL_ADSP_IDC_REG_ADDRESS DT_REG_ADDR(INTEL_ADSP_IDC_DTNODE)
/Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/cavs/include/intel_tgl_adsp/
Dadsp_memory.h12 #define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
15 #define LP_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1)))
33 #define L3_MEM_BASE_ADDR (DT_REG_ADDR(DT_NODELABEL(imr1)))
/Zephyr-Core-3.5.0/soc/arc/snps_arc_iot/
Dlinker.ld19 #define SRAM_START DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
25 #define FLASH_START DT_REG_ADDR(DT_CHOSEN(zephyr_flash))
32 #define ICCM_START DT_REG_ADDR(DT_INST(0, arc_iccm))
41 #define DCCM_START DT_REG_ADDR(DT_INST(0, arc_dccm))
/Zephyr-Core-3.5.0/soc/arm/gigadevice/gd32a50x/
Dsoc.c13 register unsigned r0 __asm("r0") = DT_REG_ADDR(DT_CHOSEN(zephyr_sram)); in z_arm_platform_init()
15 DT_REG_ADDR(DT_CHOSEN(zephyr_sram)) + DT_REG_SIZE(DT_CHOSEN(zephyr_sram)); in z_arm_platform_init()
/Zephyr-Core-3.5.0/soc/arm/nxp_s32/s32k/
Ds32k3xx_startup.S24 ldr r1, = DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
43 ldr r1, = DT_REG_ADDR(DT_CHOSEN(zephyr_itcm))
56 ldr r1, = DT_REG_ADDR(DT_CHOSEN(zephyr_dtcm))

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