Home
last modified time | relevance | path

Searched refs:DT_PROP (Results 1 – 25 of 290) sorted by relevance

12345678910>>...12

/Zephyr-Core-3.5.0/soc/arm/nxp_imx/rt/
Dpinctrl_rt11xx.h52 ((0x2 & ((!DT_PROP(node_id, bias_pull_down) && !DT_PROP(node_id, bias_pull_up)) << 1)) |\
53 (0x1 & ((!DT_PROP(node_id, bias_pull_down) && !DT_PROP(node_id, bias_pull_up)) << 0))) \
56 IF_ENABLED(DT_PROP(node_id, bias_pull_down), \
58 IF_ENABLED(DT_PROP(node_id, bias_pull_up), \
62 (DT_PROP(node_id, drive_open_drain) << MCUX_IMX_ODE_SHIFT) | \
63 (DT_PROP(node_id, input_enable) << MCUX_IMX_INPUT_ENABLE_SHIFT)
66 (DT_PROP(node_id, bias_pull_up) << MCUX_IMX_PUS_SHIFT) | \
67 ((DT_PROP(node_id, bias_pull_up) || DT_PROP(node_id, bias_pull_down)) \
71 (DT_PROP(node_id, drive_open_drain) << MCUX_IMX_ODE_SHIFT) | \
72 (DT_PROP(node_id, input_enable) << MCUX_IMX_INPUT_ENABLE_SHIFT)
[all …]
/Zephyr-Core-3.5.0/soc/arm/st_stm32/common/
Dpinctrl_soc.h44 #define Z_PINCTRL_STM32_PINMUX_INIT(node_id) DT_PROP(node_id, pinmux)
65 (((STM32_NO_PULL * DT_PROP(node_id, bias_disable)) << STM32_PUPD_SHIFT) | \
66 ((STM32_PULL_UP * DT_PROP(node_id, bias_pull_up)) << STM32_PUPD_SHIFT) | \
67 ((STM32_PULL_DOWN * DT_PROP(node_id, bias_pull_down)) << STM32_PUPD_SHIFT) | \
68 ((STM32_PUSH_PULL * DT_PROP(node_id, drive_push_pull)) << STM32_CNF_OUT_0_SHIFT) | \
69 ((STM32_OPEN_DRAIN * DT_PROP(node_id, drive_open_drain)) << STM32_CNF_OUT_0_SHIFT) | \
70 ((STM32_OUTPUT_LOW * DT_PROP(node_id, output_low)) << STM32_ODR_SHIFT) | \
71 ((STM32_OUTPUT_HIGH * DT_PROP(node_id, output_high)) << STM32_ODR_SHIFT) | \
80 (((STM32_NO_PULL * DT_PROP(node_id, bias_disable)) << STM32_PUPDR_SHIFT) | \
81 ((STM32_PULL_UP * DT_PROP(node_id, bias_pull_up)) << STM32_PUPDR_SHIFT) | \
[all …]
/Zephyr-Core-3.5.0/soc/arm/microchip_mec/common/
Dpinctrl_soc.h32 #define Z_PINCTRL_MCHP_XEC_PINMUX_INIT(node_id) (uint32_t)(DT_PROP(node_id, pinmux))
35 ((DT_PROP(node_id, bias_disable) << MCHP_XEC_NO_PUD_POS) \
36 | (DT_PROP(node_id, bias_pull_down) << MCHP_XEC_PD_POS) \
37 | (DT_PROP(node_id, bias_pull_up) << MCHP_XEC_PU_POS) \
38 | (DT_PROP(node_id, drive_push_pull) << MCHP_XEC_PUSH_PULL_POS) \
39 | (DT_PROP(node_id, drive_open_drain) << MCHP_XEC_OPEN_DRAIN_POS) \
40 | (DT_PROP(node_id, output_disable) << MCHP_XEC_OUT_DIS_POS) \
41 | (DT_PROP(node_id, output_enable) << MCHP_XEC_OUT_EN_POS) \
42 | (DT_PROP(node_id, output_high) << MCHP_XEC_OUT_HI_POS) \
43 | (DT_PROP(node_id, output_low) << MCHP_XEC_OUT_LO_POS) \
[all …]
/Zephyr-Core-3.5.0/include/zephyr/drivers/clock_control/
Dstm32_clock_control.h60 #define STM32_AHB_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb_prescaler)
61 #define STM32_APB1_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb1_prescaler)
62 #define STM32_APB2_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb2_prescaler)
63 #define STM32_APB3_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb3_prescaler)
64 #define STM32_APB7_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb7_prescaler)
65 #define STM32_AHB3_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb3_prescaler)
66 #define STM32_AHB4_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb4_prescaler)
68 #define STM32_CPU1_PRESCALER DT_PROP(DT_NODELABEL(rcc), cpu1_prescaler)
69 #define STM32_CPU2_PRESCALER DT_PROP(DT_NODELABEL(rcc), cpu2_prescaler)
85 #define STM32_ADC_PRESCALER DT_PROP(DT_NODELABEL(rcc), adc_prescaler)
[all …]
/Zephyr-Core-3.5.0/soc/arm/ti_simplelink/cc13x2_cc26x2/
Dpinctrl_soc.h22 (DT_PROP(node_id, bias_pull_up) * IOC_IOPULL_UP | \
23 DT_PROP(node_id, bias_pull_down) * IOC_IOPULL_DOWN | \
24 DT_PROP(node_id, bias_disable) * IOC_NO_IOPULL | \
25 DT_PROP(node_id, drive_open_drain) * IOC_IOMODE_OPEN_DRAIN_NORMAL | \
26 DT_PROP(node_id, drive_open_source) * IOC_IOMODE_OPEN_SRC_NORMAL | \
27 (DT_PROP(node_id, drive_strength) >> 2) << IOC_IOCFG0_IOCURR_S | \
28 DT_PROP(node_id, input_enable) * IOC_INPUT_ENABLE | \
29 DT_PROP(node_id, input_schmitt_enable) * IOC_HYST_ENABLE | \
30 DT_PROP(node_id, ti_input_edge_detect))
/Zephyr-Core-3.5.0/drivers/display/
Ddisplay_ili9342c.h71 .gamset = DT_PROP(DT_INST(n, ilitek_ili9342c), gamset), \
72 .ifmode = DT_PROP(DT_INST(n, ilitek_ili9342c), ifmode), \
73 .frmctr1 = DT_PROP(DT_INST(n, ilitek_ili9342c), frmctr1), \
74 .invtr = DT_PROP(DT_INST(n, ilitek_ili9342c), invtr), \
75 .disctrl = DT_PROP(DT_INST(n, ilitek_ili9342c), disctrl), \
76 .etmod = DT_PROP(DT_INST(n, ilitek_ili9342c), etmod), \
77 .pwctrl1 = DT_PROP(DT_INST(n, ilitek_ili9342c), pwctrl1), \
78 .pwctrl2 = DT_PROP(DT_INST(n, ilitek_ili9342c), pwctrl2), \
79 .pwctrl3 = DT_PROP(DT_INST(n, ilitek_ili9342c), pwctrl3), \
80 .vmctrl1 = DT_PROP(DT_INST(n, ilitek_ili9342c), vmctrl1), \
[all …]
Ddisplay_ili9340.h54 .gamset = DT_PROP(DT_INST(n, ilitek_ili9340), gamset), \
55 .frmctr1 = DT_PROP(DT_INST(n, ilitek_ili9340), frmctr1), \
56 .disctrl = DT_PROP(DT_INST(n, ilitek_ili9340), disctrl), \
57 .pwctrl1 = DT_PROP(DT_INST(n, ilitek_ili9340), pwctrl1), \
58 .pwctrl2 = DT_PROP(DT_INST(n, ilitek_ili9340), pwctrl2), \
59 .vmctrl1 = DT_PROP(DT_INST(n, ilitek_ili9340), vmctrl1), \
60 .vmctrl2 = DT_PROP(DT_INST(n, ilitek_ili9340), vmctrl2), \
61 .pgamctrl = DT_PROP(DT_INST(n, ilitek_ili9340), pgamctrl), \
62 .ngamctrl = DT_PROP(DT_INST(n, ilitek_ili9340), ngamctrl), \
Ddisplay_ili9341.h125 .gamset = DT_PROP(DT_INST(n, ilitek_ili9341), gamset), \
126 .ifmode = DT_PROP(DT_INST(n, ilitek_ili9341), ifmode), \
127 .frmctr1 = DT_PROP(DT_INST(n, ilitek_ili9341), frmctr1), \
128 .disctrl = DT_PROP(DT_INST(n, ilitek_ili9341), disctrl), \
129 .pwctrl1 = DT_PROP(DT_INST(n, ilitek_ili9341), pwctrl1), \
130 .pwctrl2 = DT_PROP(DT_INST(n, ilitek_ili9341), pwctrl2), \
131 .vmctrl1 = DT_PROP(DT_INST(n, ilitek_ili9341), vmctrl1), \
132 .vmctrl2 = DT_PROP(DT_INST(n, ilitek_ili9341), vmctrl2), \
133 .pgamctrl = DT_PROP(DT_INST(n, ilitek_ili9341), pgamctrl), \
134 .ngamctrl = DT_PROP(DT_INST(n, ilitek_ili9341), ngamctrl), \
[all …]
Ddisplay_ili9488.h48 .frmctr1 = DT_PROP(DT_INST(n, ilitek_ili9488), frmctr1), \
49 .disctrl = DT_PROP(DT_INST(n, ilitek_ili9488), disctrl), \
50 .pwctrl1 = DT_PROP(DT_INST(n, ilitek_ili9488), pwctrl1), \
51 .pwctrl2 = DT_PROP(DT_INST(n, ilitek_ili9488), pwctrl2), \
52 .vmctrl = DT_PROP(DT_INST(n, ilitek_ili9488), vmctrl), \
53 .pgamctrl = DT_PROP(DT_INST(n, ilitek_ili9488), pgamctrl), \
54 .ngamctrl = DT_PROP(DT_INST(n, ilitek_ili9488), ngamctrl), \
/Zephyr-Core-3.5.0/soc/riscv/espressif_esp32/esp32c3/
Dpinctrl_soc.h43 (((ESP32_NO_PULL * DT_PROP(node_id, bias_disable)) << ESP32_PIN_BIAS_SHIFT) | \
44 ((ESP32_PULL_UP * DT_PROP(node_id, bias_pull_up)) << ESP32_PIN_BIAS_SHIFT) | \
45 ((ESP32_PULL_DOWN * DT_PROP(node_id, bias_pull_down)) << ESP32_PIN_BIAS_SHIFT) | \
46 ((ESP32_PUSH_PULL * DT_PROP(node_id, drive_push_pull)) << ESP32_PIN_DRV_SHIFT) | \
47 ((ESP32_OPEN_DRAIN * DT_PROP(node_id, drive_open_drain)) << ESP32_PIN_DRV_SHIFT) | \
48 ((ESP32_PIN_OUT_HIGH * DT_PROP(node_id, output_high)) << ESP32_PIN_OUT_SHIFT) | \
49 ((ESP32_PIN_OUT_LOW * DT_PROP(node_id, output_low)) << ESP32_PIN_OUT_SHIFT) | \
50 ((ESP32_PIN_OUT_EN * DT_PROP(node_id, output_enable)) << ESP32_PIN_EN_DIR_SHIFT) | \
51 ((ESP32_PIN_IN_EN * DT_PROP(node_id, input_enable)) << ESP32_PIN_EN_DIR_SHIFT))
/Zephyr-Core-3.5.0/soc/xtensa/espressif_esp32/esp32s3/
Dpinctrl_soc.h45 (((ESP32_NO_PULL * DT_PROP(node_id, bias_disable)) << ESP32_PIN_BIAS_SHIFT) | \
46 ((ESP32_PULL_UP * DT_PROP(node_id, bias_pull_up)) << ESP32_PIN_BIAS_SHIFT) | \
47 ((ESP32_PULL_DOWN * DT_PROP(node_id, bias_pull_down)) << ESP32_PIN_BIAS_SHIFT) | \
48 ((ESP32_PUSH_PULL * DT_PROP(node_id, drive_push_pull)) << ESP32_PIN_DRV_SHIFT) | \
49 ((ESP32_OPEN_DRAIN * DT_PROP(node_id, drive_open_drain)) << ESP32_PIN_DRV_SHIFT) | \
50 ((ESP32_PIN_OUT_HIGH * DT_PROP(node_id, output_high)) << ESP32_PIN_OUT_SHIFT) | \
51 ((ESP32_PIN_OUT_LOW * DT_PROP(node_id, output_low)) << ESP32_PIN_OUT_SHIFT) | \
52 ((ESP32_PIN_OUT_EN * DT_PROP(node_id, output_enable)) << ESP32_PIN_EN_DIR_SHIFT) | \
53 ((ESP32_PIN_IN_EN * DT_PROP(node_id, input_enable)) << ESP32_PIN_EN_DIR_SHIFT))
/Zephyr-Core-3.5.0/soc/xtensa/espressif_esp32/esp32/
Dpinctrl_soc.h43 (((ESP32_NO_PULL * DT_PROP(node_id, bias_disable)) << ESP32_PIN_BIAS_SHIFT) | \
44 ((ESP32_PULL_UP * DT_PROP(node_id, bias_pull_up)) << ESP32_PIN_BIAS_SHIFT) | \
45 ((ESP32_PULL_DOWN * DT_PROP(node_id, bias_pull_down)) << ESP32_PIN_BIAS_SHIFT) | \
46 ((ESP32_PUSH_PULL * DT_PROP(node_id, drive_push_pull)) << ESP32_PIN_DRV_SHIFT) | \
47 ((ESP32_OPEN_DRAIN * DT_PROP(node_id, drive_open_drain)) << ESP32_PIN_DRV_SHIFT) | \
48 ((ESP32_PIN_OUT_HIGH * DT_PROP(node_id, output_high)) << ESP32_PIN_OUT_SHIFT) | \
49 ((ESP32_PIN_OUT_LOW * DT_PROP(node_id, output_low)) << ESP32_PIN_OUT_SHIFT) | \
50 ((ESP32_PIN_OUT_EN * DT_PROP(node_id, output_enable)) << ESP32_PIN_EN_DIR_SHIFT) | \
51 ((ESP32_PIN_IN_EN * DT_PROP(node_id, input_enable)) << ESP32_PIN_EN_DIR_SHIFT))
/Zephyr-Core-3.5.0/soc/xtensa/espressif_esp32/esp32s2/
Dpinctrl_soc.h43 (((ESP32_NO_PULL * DT_PROP(node_id, bias_disable)) << ESP32_PIN_BIAS_SHIFT) | \
44 ((ESP32_PULL_UP * DT_PROP(node_id, bias_pull_up)) << ESP32_PIN_BIAS_SHIFT) | \
45 ((ESP32_PULL_DOWN * DT_PROP(node_id, bias_pull_down)) << ESP32_PIN_BIAS_SHIFT) | \
46 ((ESP32_PUSH_PULL * DT_PROP(node_id, drive_push_pull)) << ESP32_PIN_DRV_SHIFT) | \
47 ((ESP32_OPEN_DRAIN * DT_PROP(node_id, drive_open_drain)) << ESP32_PIN_DRV_SHIFT) | \
48 ((ESP32_PIN_OUT_HIGH * DT_PROP(node_id, output_high)) << ESP32_PIN_OUT_SHIFT) | \
49 ((ESP32_PIN_OUT_LOW * DT_PROP(node_id, output_low)) << ESP32_PIN_OUT_SHIFT) | \
50 ((ESP32_PIN_OUT_EN * DT_PROP(node_id, output_enable)) << ESP32_PIN_EN_DIR_SHIFT) | \
51 ((ESP32_PIN_IN_EN * DT_PROP(node_id, input_enable)) << ESP32_PIN_EN_DIR_SHIFT))
/Zephyr-Core-3.5.0/soc/arm/nxp_lpc/lpc55xxx/
Dpinctrl_soc.h32 (IF_ENABLED(DT_PROP(node_id, bias_pull_down), (IOCON_PIO_MODE(0x1) |)) \
33 IF_ENABLED(DT_PROP(node_id, bias_pull_up), (IOCON_PIO_MODE(0x2) |)) \
34 IF_ENABLED(DT_PROP(node_id, drive_push_pull), (IOCON_PIO_MODE(0x3) |)) \
36 IOCON_PIO_INVERT(DT_PROP(node_id, nxp_invert)) | \
37 IOCON_PIO_DIGIMODE(!DT_PROP(node_id, nxp_analog_mode)) | \
38 IOCON_PIO_OD(DT_PROP(node_id, drive_open_drain)) | \
39 IOCON_PIO_ASW(DT_PROP(node_id, nxp_analog_mode)) | \
40 IOCON_PIO_ASW1(DT_PROP(node_id, nxp_analog_alt_mode)) | \
43 IOCON_PIO_ECS(DT_PROP(node_id, nxp_i2c_pullup)) | \
44 IOCON_PIO_EGP(!DT_PROP(node_id, nxp_i2c_mode)) | \
/Zephyr-Core-3.5.0/soc/arm/nxp_lpc/lpc11u6x/
Dpinctrl_soc.h23 (IF_ENABLED(DT_PROP(node_id, bias_pull_down), (IOCON_PIO_MODE(0x1) |)) \
24 IF_ENABLED(DT_PROP(node_id, bias_pull_up), (IOCON_PIO_MODE(0x2) |)) \
25 IF_ENABLED(DT_PROP(node_id, drive_push_pull), (IOCON_PIO_MODE(0x3) |)) \
26 IOCON_PIO_HYS(DT_PROP(node_id, input_schmitt_enable)) | \
27 IOCON_PIO_INVERT(DT_PROP(node_id, nxp_invert)) | \
28 IOCON_PIO_OD(DT_PROP(node_id, drive_open_drain)) | \
31 IOCON_PIO_ADMODE(!DT_PROP(node_id, nxp_analog_mode)) | \
32 IOCON_PIO_FILTER(DT_PROP(node_id, nxp_disable_analog_filter)) | \
33 IOCON_PIO_I2CMODE(!DT_PROP(node_id, nxp_i2c_mode)) | \
/Zephyr-Core-3.5.0/soc/arm/nxp_imx/mcimx7_m4/
Dpinctrl_soc.h30 ((DT_PROP(node_id, input_schmitt_enable) << MCUX_IMX_INPUT_SCHMITT_ENABLE_SHIFT) | \
31 IF_ENABLED(DT_PROP(node_id, bias_pull_up), (DT_ENUM_IDX(node_id, bias_pull_up_value) \
33 ((DT_PROP(node_id, bias_pull_down) | DT_PROP(node_id, bias_pull_up)) \
37 (DT_PROP(node_id, input_enable) << MCUX_IMX_INPUT_ENABLE_SHIFT))
41 (IF_ENABLED(DT_PROP(node_id, bias_pull_up), (DT_ENUM_IDX(node_id, bias_pull_up_value) \
43 IF_ENABLED(DT_PROP(node_id, bias_pull_down), (DT_ENUM_IDX(node_id, bias_pull_down_value)\
45 ((DT_PROP(node_id, bias_pull_down) | DT_PROP(node_id, bias_pull_up)) \
47 (DT_PROP(node_id, input_enable) << MCUX_IMX_INPUT_ENABLE_SHIFT))
83 DT_PROP(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx), pin_lpsr), \
/Zephyr-Core-3.5.0/soc/arm/infineon_cat1/common/
Dpinctrl_soc.h90 #define Z_PINCTRL_CAT1_PINMUX_INIT(node_id) DT_PROP(node_id, pinmux)
97 (DT_PROP(node_id, bias_pull_up) << SOC_GPIO_PULLUP_POS) | \
98 (DT_PROP(node_id, bias_pull_down) << SOC_GPIO_PULLDOWN_POS) | \
99 (DT_PROP(node_id, drive_open_drain) << SOC_GPIO_OPENDRAIN_POS) | \
100 (DT_PROP(node_id, drive_open_source) << SOC_GPIO_OPENSOURCE_POS) | \
101 (DT_PROP(node_id, drive_push_pull) << SOC_GPIO_PUSHPULL_POS) | \
102 (DT_PROP(node_id, input_enable) << SOC_GPIO_INPUTENABLE_POS) | \
103 (DT_PROP(node_id, bias_high_impedance) << SOC_GPIO_HIGHZ_POS))
/Zephyr-Core-3.5.0/soc/arm/ambiq/apollo4x/
Dpinctrl_soc.h55 DT_PROP(node_id, input_enable), \
58 DT_PROP(node_id, drive_push_pull), \
59 DT_PROP(node_id, drive_open_drain), \
60 DT_PROP(node_id, bias_high_impedance), \
61 DT_PROP(node_id, bias_pull_up), \
62 DT_PROP(node_id, bias_pull_down), \
64 DT_PROP(node_id, ambiq_iom_nce_module), \
/Zephyr-Core-3.5.0/soc/arm/nxp_lpc/lpc54xxx/
Dpinctrl_soc.h22 (IF_ENABLED(DT_PROP(node_id, bias_pull_down), (IOCON_PIO_MODE(0x1) |)) \
23 IF_ENABLED(DT_PROP(node_id, bias_pull_up), (IOCON_PIO_MODE(0x2) |)) \
24 IF_ENABLED(DT_PROP(node_id, drive_push_pull), (IOCON_PIO_MODE(0x3) |)) \
25 IOCON_PIO_INVERT(DT_PROP(node_id, nxp_invert)) | \
26 IOCON_PIO_DIGIMODE(!DT_PROP(node_id, nxp_analog_mode)) | \
29 IOCON_PIO_OD(DT_PROP(node_id, drive_open_drain)) | \
30 IOCON_PIO_I2CSLEW(!DT_PROP(node_id, nxp_i2c_mode)) | \
/Zephyr-Core-3.5.0/soc/arm/nxp_lpc/lpc51u68/
Dpinctrl_soc.h22 (IF_ENABLED(DT_PROP(node_id, bias_pull_down), (IOCON_PIO_MODE(0x1) |)) \
23 IF_ENABLED(DT_PROP(node_id, bias_pull_up), (IOCON_PIO_MODE(0x2) |)) \
24 IF_ENABLED(DT_PROP(node_id, drive_push_pull), (IOCON_PIO_MODE(0x3) |)) \
25 IOCON_PIO_INVERT(DT_PROP(node_id, nxp_invert)) | \
26 IOCON_PIO_DIGIMODE(!DT_PROP(node_id, nxp_analog_mode)) | \
29 IOCON_PIO_OD(DT_PROP(node_id, drive_open_drain)) | \
30 IOCON_PIO_I2CSLEW(!DT_PROP(node_id, nxp_i2c_mode)) | \
/Zephyr-Core-3.5.0/soc/arm/nxp_imx/rt5xx/
Dpinctrl_soc.h23 (IF_ENABLED(DT_PROP(node_id, bias_pull_down), \
25 IF_ENABLED(DT_PROP(node_id, bias_pull_up), \
27 IOPCTL_PIO_ODENA(DT_PROP(node_id, drive_open_drain)) | /* open drain */ \
28 IOPCTL_PIO_IBENA(DT_PROP(node_id, input_enable)) | /* input buffer */ \
31 IOPCTL_PIO_IIENA(DT_PROP(node_id, nxp_invert)) | /* invert input */ \
32 IOPCTL_PIO_AMENA(DT_PROP(node_id, nxp_analog_mode))) /* analog multiplexor */
/Zephyr-Core-3.5.0/soc/arm/nxp_imx/rt6xx/
Dpinctrl_soc.h23 (IF_ENABLED(DT_PROP(node_id, bias_pull_down), \
25 IF_ENABLED(DT_PROP(node_id, bias_pull_up), \
27 IOPCTL_PIO_ODENA(DT_PROP(node_id, drive_open_drain)) | /* open drain */ \
28 IOPCTL_PIO_IBENA(DT_PROP(node_id, input_enable)) | /* input buffer */ \
31 IOPCTL_PIO_IIENA(DT_PROP(node_id, nxp_invert)) | /* invert input */ \
32 IOPCTL_PIO_AMENA(DT_PROP(node_id, nxp_analog_mode))) /* analog multiplexor */
/Zephyr-Core-3.5.0/drivers/clock_control/
Dclock_control_litex.h46 #define LOCK_TIMEOUT DT_PROP(MMCM, litex_lock_timeout)
47 #define DRDY_TIMEOUT DT_PROP(MMCM, litex_drdy_timeout)
48 #define SYS_CLOCK_FREQUENCY DT_PROP(MMCM, litex_sys_clock_frequency)
49 #define DIVCLK_DIVIDE_MIN DT_PROP(MMCM, litex_divclk_divide_min)
50 #define DIVCLK_DIVIDE_MAX DT_PROP(MMCM, litex_divclk_divide_max)
51 #define CLKFBOUT_MULT_MIN DT_PROP(MMCM, litex_clkfbout_mult_min)
52 #define CLKFBOUT_MULT_MAX DT_PROP(MMCM, litex_clkfbout_mult_max)
53 #define VCO_FREQ_MIN DT_PROP(MMCM, litex_vco_freq_min)
54 #define VCO_FREQ_MAX DT_PROP(MMCM, litex_vco_freq_max)
55 #define CLKOUT_DIVIDE_MIN DT_PROP(MMCM, litex_clkout_divide_min)
[all …]
/Zephyr-Core-3.5.0/soc/arm/nuvoton_numicro/common/
Dpinctrl_soc.h34 .pull_down = DT_PROP(node_id, bias_pull_down), \
35 .pull_up = DT_PROP(node_id, bias_pull_up), \
36 .open_drain = DT_PROP(node_id, drive_open_drain), \
37 .schmitt_trigger = DT_PROP(node_id, input_schmitt_enable),\
39 .input_disable = DT_PROP(node_id, input_disable), \
40 .input_debounce = DT_PROP(node_id, input_debounce), \
/Zephyr-Core-3.5.0/include/zephyr/drivers/pinctrl/
Dpinctrl_soc_sam_common.h44 | (DT_PROP(node_id, bias_pull_up) << SAM_PINCTRL_PULLUP_POS) \
45 | (DT_PROP(node_id, bias_pull_down) << SAM_PINCTRL_PULLDOWN_POS) \
46 | (DT_PROP(node_id, drive_open_drain) << SAM_PINCTRL_OPENDRAIN_POS) \
51 | (DT_PROP(node_id, bias_pull_up) << SAM_PINCTRL_PULLUP_POS) \
52 | (DT_PROP(node_id, bias_pull_down) << SAM_PINCTRL_PULLDOWN_POS) \
53 | (DT_PROP(node_id, input_enable) << SAM_PINCTRL_INPUTENABLE_POS) \
54 | (DT_PROP(node_id, output_enable) << SAM_PINCTRL_OUTPUTENABLE_POS) \

12345678910>>...12