Searched refs:DGCS (Results 1 – 2 of 2) sorted by relevance
| /Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/common/include/ |
| D | intel_adsp_hda.h | 35 #define DGCS(base, regblock_size, stream) \ macro
105 sid, DGCS(base, regblock_size, sid), \
106 *DGCS(base, regblock_size, sid), \
126 *DGCS(base, regblock_size, sid) |= DGCS_FWCB; in intel_adsp_hda_init()
173 if (*DGCS(base, regblock_size, sid) & DGCS_GEN) { in intel_adsp_hda_set_buffer()
177 if (*DGCS(base, regblock_size, sid) & DGCS_GBUSY) { in intel_adsp_hda_set_buffer()
213 *DGCS(base, regblock_size, sid) |= DGCS_GEN; in intel_adsp_hda_enable()
216 *DGCS(base, regblock_size, sid) |= DGCS_FIFORDY; in intel_adsp_hda_enable()
229 *DGCS(base, regblock_size, sid) &= ~(DGCS_GEN | DGCS_FIFORDY); in intel_adsp_hda_disable()
241 return *DGCS(base, regblock_size, sid) & (DGCS_GEN | DGCS_FIFORDY); in intel_adsp_hda_is_enabled()
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| /Zephyr-Core-3.5.0/drivers/dma/ |
| D | dma_intel_adsp_hda.c | 225 stat->busy = *DGCS(cfg->base, cfg->regblock_size, channel) & DGCS_GBUSY; in intel_adsp_hda_dma_status()
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