Searched refs:DGBWP (Results 1 – 2 of 2) sorted by relevance
| /Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/common/include/ |
| D | intel_adsp_hda.h | 69 #define DGBWP(base, regblock_size, stream) \ macro
110 *DGBWP(base, regblock_size, sid), \
271 int32_t wp = *DGBWP(base, regblock_size, sid); in intel_adsp_hda_unused()
362 return *DGBWP(base, regblock_size, sid) == *DGBRP(base, regblock_size, sid); in intel_adsp_hda_wp_rp_eq()
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| /Zephyr-Core-3.5.0/drivers/dma/ |
| D | dma_intel_adsp_hda.c | 195 const uint32_t wp = *DGBWP(cfg->base, cfg->regblock_size, channel); in intel_adsp_hda_dma_host_reload()
226 stat->write_position = *DGBWP(cfg->base, cfg->regblock_size, channel); in intel_adsp_hda_dma_status()
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