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/Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/common/include/
Dintel_adsp_hda.h53 #define DGBBA(base, regblock_size, stream) \ macro
107 *DGBBA(base, regblock_size, sid), \
181 *DGBBA(base, regblock_size, sid) = aligned_addr; in intel_adsp_hda_set_buffer()