DCACHE_INVALID (reference) in projects: Zephyr-Core-3.5.0

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Searched refs:DCACHE_INVALID (Results 1 – 1 of 1) sorted by relevance

/Zephyr-Core-3.5.0/drivers/cache/
D	cache_aspeed.c	`33 #define DCACHE_INVALID(addr) (BIT(31) \| ((addr & GENMASK(10, 0)) << 16)) macro 181 syscon_write_reg(dev, CACHE_INVALID_REG, DCACHE_INVALID(aligned_addr)); in cache_data_invd_range()`

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
Zephyr-Core-3.4.0
Zephyr-Core-3.5.0
Zephyr-Core-3.6.0
Zephyr-Core-3.7.0
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babblesim_ext_2G4_channel_multiatt-3.4.0
babblesim_ext_2G4_channel_multiatt-3.7.0-3.6.0-3.5.0
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babblesim_ext_2G4_device_burst_interferer-3.7.0-3.6.0-3.5.0-3.4.0
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babblesim_ext_2G4_libPhyComv1-3.7.0
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