Searched refs:CLOCK_DIVIDER (Results 1 – 7 of 7) sorted by relevance
33 #define CLOCK_DIVIDER(clk) \ macro65 .clkdiv1 = SIM_CLKDIV1_OUTDIV1(CLOCK_DIVIDER(core_clk)) |66 SIM_CLKDIV1_OUTDIV2(CLOCK_DIVIDER(bus_clk)) |67 SIM_CLKDIV1_OUTDIV3(CLOCK_DIVIDER(flexbus_clk)) |68 SIM_CLKDIV1_OUTDIV4(CLOCK_DIVIDER(flash_clk)),
24 #define CLOCK_DIVIDER(clk) \ macro59 .clkdiv1 = SIM_CLKDIV1_OUTDIV1(CLOCK_DIVIDER(core_clk)) |60 SIM_CLKDIV1_OUTDIV2(CLOCK_DIVIDER(bus_clk)) |61 SIM_CLKDIV1_OUTDIV3(CLOCK_DIVIDER(flexbus_clk)) |62 SIM_CLKDIV1_OUTDIV4(CLOCK_DIVIDER(flash_clk)),
28 #define CLOCK_DIVIDER(clk) \ macro63 .clkdiv1 = SIM_CLKDIV1_OUTDIV1(CLOCK_DIVIDER(core_clk)) |64 SIM_CLKDIV1_OUTDIV2(CLOCK_DIVIDER(bus_clk)) |65 SIM_CLKDIV1_OUTDIV3(CLOCK_DIVIDER(flexbus_clk)) |66 SIM_CLKDIV1_OUTDIV4(CLOCK_DIVIDER(flash_clk)),
35 #define CLOCK_DIVIDER(clk) \ macro70 .clkdiv1 = SIM_CLKDIV1_OUTDIV1(CLOCK_DIVIDER(core_clk)) |71 SIM_CLKDIV1_OUTDIV2(CLOCK_DIVIDER(bus_clk)) |72 SIM_CLKDIV1_OUTDIV3(CLOCK_DIVIDER(flexbus_clk)) |73 SIM_CLKDIV1_OUTDIV4(CLOCK_DIVIDER(flash_clk)),
32 #define CLOCK_DIVIDER(clk) \ macro67 .clkdiv1 = SIM_CLKDIV1_OUTDIV1(CLOCK_DIVIDER(core_clk)) |68 SIM_CLKDIV1_OUTDIV2(CLOCK_DIVIDER(bus_clk)) |69 SIM_CLKDIV1_OUTDIV4(CLOCK_DIVIDER(flash_clk)),
21 #define CLOCK_DIVIDER(clk) \ macro40 .clkdiv1 = SIM_CLKDIV1_OUTDIV1(CLOCK_DIVIDER(core_clk)) |41 SIM_CLKDIV1_OUTDIV4(CLOCK_DIVIDER(flash_clk)),
20 #define CLOCK_DIVIDER(clk) \ macro39 .clkdiv1 = SIM_CLKDIV1_OUTDIV1(CLOCK_DIVIDER(core_clk)) | in clock_init()40 SIM_CLKDIV1_OUTDIV4(CLOCK_DIVIDER(flash_clk)), in clock_init()
