1 /* ieee802154_cc1200_regs.h - Registers definition for TI CC1200 */ 2 3 /* 4 * Copyright (c) 2017 Intel Corporation. 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 */ 8 9 #ifndef ZEPHYR_DRIVERS_IEEE802154_IEEE802154_CC1200_REGS_H_ 10 #define ZEPHYR_DRIVERS_IEEE802154_IEEE802154_CC1200_REGS_H_ 11 12 /* Access types (see Section 3.2) */ 13 14 #define CC1200_ACCESS_RD BIT(7) 15 #define CC1200_ACCESS_WR (0x00) 16 #define CC1200_ACCESS_BURST BIT(6) 17 18 /* Configuration registers (see Section 12 for the details) */ 19 20 #define CC1200_REG_IOCFG3 (0x00) 21 #define GPIO3_ATRAN BIT(7) 22 #define GPIO3_INV BIT(6) 23 #define GPIO3_CFG(_cfg_) (_cfg_ & 0x3F) 24 25 #define CC1200_REG_IOCFG2 (0x01) 26 #define GPIO2_ATRAN BIT(7) 27 #define GPIO2_INV BIT(6) 28 #define GPIO2_CFG(_cfg_) (_cfg_ & 0x3F) 29 30 #define CC1200_REG_IOCFG1 (0x02) 31 #define GPIO1_ATRAN BIT(7) 32 #define GPIO1_INV BIT(6) 33 #define GPIO1_CFG(_cfg_) (_cfg_ & 0x3F) 34 35 #define CC1200_REG_IOCFG0 (0x03) 36 #define GPIO0_ATRAN BIT(7) 37 #define GPIO0_INV BIT(6) 38 #define GPIO0_CFG(_cfg_) (_cfg_ & 0x3F) 39 40 #define CC1200_REG_SYNC3 (0x04) 41 #define CC1200_REG_SYNC2 (0x05) 42 #define CC1200_REG_SYNC1 (0x06) 43 #define CC1200_REG_SYNC0 (0x07) 44 45 #define CC1200_REG_SYNC_CFG1 (0x08) 46 #define SYNC_MODE(_cfg_) (_cfg_ & 0xE0) 47 #define SYNC_THR(_cfg_) (_cfg_ & 0x1F) 48 49 50 #define CC1200_REG_SYNC_CFG0 (0x09) 51 #define AUTO_CLEAR BIT(5) 52 #define RX_CONFIG_LIMITATION BIT(4) 53 #define PQT_GATING_EN BIT(3) 54 #define EXT_SYNC_DETECT BIT(2) 55 #define STRICT_SYNC_CHECK(_cfg_) (_cfg_ & 0x03) 56 57 #define CC1200_REG_DEVIATION_M (0x0A) 58 59 #define CC1200_REG_MODCFG_DEV_E (0x0B) 60 #define MODEM_MODE(_cfg_) (_cfg_ & 0xC0) 61 #define MOD_FORMAT(_cfg_) (_cfg_ & 0x38) 62 #define DEV_E(_cfg_) (_cfg_ & 0x07) 63 64 #define CC1200_REG_DCFILT_CFG (0x0C) 65 #define DCFILT_FREEZE_COEFF BIT(6) 66 #define DCFILT_BW_SETTLE(_cfg_) (_cfg_ & 0x38) 67 #define DCFILT_BW(_cfg_) (_cfg_ & 0x07) 68 69 #define CC1200_REG_PREAMBLE_CFG1 (0x0D) 70 #define NUM_PREAMBL(_cfg_) (_cfg_ & 0x3C) 71 #define PREAMBLE_WORD(_cfg_) (_cfg_ & 0x03) 72 73 #define CC1200_REG_PREAMBLE_CFG0 (0x0E) 74 #define PQT_EN BIT(7) 75 #define PQT_VALID_TIMEOUT(_cfg_) (_cfg_ & 0x70) 76 #define PQT(_cfg_) (_cfg_ & 0x0F) 77 78 #define CC1200_REG_IQIC (0x0F) 79 #define IQIC_EN BIT(7) 80 #define IQIC_UPDATE_COEFF_EN BIT(6) 81 #define IQIC_BLEN_SETTLE(_cfg_) (_cfg_ & 0x30) 82 #define IQIC_BLEN(_cfg_) (_cfg_ & 0x0C) 83 #define IQIC_IMGCH_LEVEL_THR(_cfg_) (_cfg_ & 0x03) 84 85 #define CC1200_REG_CHAN_BW (0x10) 86 #define ADC_CIC_DECFACT(_cfg_) (_cfg_ & 0xC0) 87 #define BB_CIC_DECFAC(_cfg_) (_cfg_ & 0x3F) 88 89 /* Is it mentioned anywhere apart from chapter 12? No known address at least 90 * #define CC1200_REG_MDMCFG2 () 91 * #define ASK_SHAPE(_cfg_) (_cfg_ & 0xC0) 92 * #define SYMBOL_MAP_CFG(_cfg_) (_cfg_ & 0x30) 93 * #define UPSAMPLER_P(_cfg_) (_cfg_ & 0x0E) 94 * #define CFM_DATA_EN BIT(0) 95 */ 96 97 #define CC1200_REG_MDMCFG1 (0x11) 98 #define CARRIER_SENSE_GATE BIT(7) 99 #define FIFO_EN BIT(6) 100 #define MANCHESTER_EN BIT(5) 101 #define INVERT_DATA_EN BIT(4) 102 #define COLLISION_DETECT_EN BIT(3) 103 #define DVGA_GAIN(_cfg_) (_cfg_ & 0x06) 104 #define SINGLE_ADC_EN BIT(0) 105 106 #define CC1200_REG_MDMCFG0 (0x12) 107 #define TRANSPARENT_MODE_EN BIT(6) 108 #define TRANSPARENT_INTFACT(_cfg_) (_cfg_ & 0x30) 109 #define DATA_FILTER_EN BIT(3) 110 #define VITERBI_EN BIT(2) 111 112 #define CC1200_REG_SYMBOL_RATE2 (0x13) 113 #define SRATE_E(_cfg_) (_cfg_ & 0xF0) 114 #define SRATE_M_19_16(_cfg_) (_cfg_ & 0x0F) 115 116 #define CC1200_REG_SYMBOL_RATE1 (0x14) 117 #define CC1200_REG_SYMBOL_RATE0 (0x15) 118 #define CC1200_REG_AGC_REF (0x16) 119 #define CC1200_REG_AGC_CS_THR (0x17) 120 #define CC1200_REG_AGC_GAIN_ADJUST (0x18) 121 122 #define CC1200_REG_AGC_CFG3 (0x19) 123 #define AGC_SYNC_BEHAVIOUR(_cfg_) (_cfg_ & 0xE0) 124 #define AGC_MIN_GAIN(_cfg_) (_cfg_ & 0x1F) 125 126 #define CC1200_REG_AGC_CFG2 (0x1A) 127 #define START_PREVIOUS_GAIN_EN BIT(7) 128 #define FE_PERFORMANCE_MODE(_cfg_) (_cfg_ & 0x60) 129 #define AGC_MAX_GAIN(_cfg_) (_cfg_ & 0x1F) 130 131 #define CC1200_REG_AGC_CFG1 (0x1B) 132 #define RSSI_STEP_THR BIT(6) 133 #define AGC_WIN_SIZE(_cfg_) (_cfg_ & 0x38) 134 #define AGC_SETTLE_WAIT(_cfg_) (_cfg_ & 0x07) 135 136 #define CC1200_REG_AGC_CFG0 (0x1C) 137 #define AGC_HYST_LEVEL(_cfg_) (_cfg_ & 0xC0) 138 #define AGC_SLEWRATE_LIMIT(_cfg_) (_cfg_ & 0x30) 139 #define RSSI_VALID_CNT(_cfg_) (_cfg_ & 0x0C) 140 #define AGC_ASK_DECAY(_cfg_) (_cfg_ & 0x03) 141 142 #define CC1200_REG_FIFO_CFG (0x1D) 143 #define CRC_AUTOFLUSH BIT(7) 144 #define FIFO_THR(_cfg_) (_cfg_ & 0x7F) 145 146 #define CC1200_REG_DEV_ADDR (0x1E) 147 148 #define CC1200_REG_SETTLING_CFG (0x1F) 149 #define FS_AUTOCAL(_cfg_) (_cfg_ & 0x18) 150 #define LOCK_TIME(_cfg_) (_cfg_ & 0x06) 151 #define FSREG_TIME BIT(0) 152 153 #define CC1200_REG_FS_CFG (0x20) 154 #define FS_LOCK_EN BIT(4) 155 #define FSD_BANDSELECT(_cfg_) (_cfg_ & 0x0F) 156 157 #define CC1200_REG_WOR_CFG1 (0x21) 158 #define WOR_RES(_cfg_) (_cfg_ & 0xC0) 159 #define WOR_MODE(_cfg_) (_cfg_ & 0x38) 160 #define EVENT1(_cfg_) (_cfg_ & 0x07) 161 162 #define CC1200_REG_WOR_CFG0 (0x22) 163 #define RX_DUTY_CYCLE_MODE(_cfg_) (_cfg_ & 0xC0) 164 #define DIV_256HZ_EN BIT(5) 165 #define EVENT2_CFG(_cfg_) (_cfg_ & 0x18) 166 #define RC_MODE(_cfg_) (_cfg_ & 0x06) 167 #define RC_PD BIT(0) 168 169 #define CC1200_REG_WOR_EVENT0_MSB (0x23) 170 #define CC1200_REG_WOR_EVENT0_LSB (0x24) 171 #define CC1200_REG_RXDCM_TIME (0x25) 172 173 #define CC1200_REG_PKT_CFG2 (0x26) 174 #define BYTE_SWAP_EN BIT(6) 175 #define FG_MODE_EN BIT(5) 176 #define CCA_MODE(_cfg_) (_cfg_ & 0x1C) 177 #define CCA_ALWAYS_CLEAR (0) 178 #define CCA_RSSI_BELOW (1 << 2) 179 #define CCA_NO_RX (2 << 2) 180 #define CCA_RSSI_BELOW_NO_RX (3 << 2) 181 #define CCA_RSSI_BELOW_ETSI_LBT (4 << 2) 182 #define PKT_FORMAT(_cfg_) (_cfg_ & 0x03) 183 #define PKT_FORMAT_NORMAL_MODE (0) 184 #define PKT_FORMAT_SYNCHRONOUS_MODE (1) 185 #define PKT_FORMAT_RANDOM_MODE (2) 186 #define PKT_FORMAT_TRANSPARENT_MODE (3) 187 188 #define CC1200_REG_PKT_CFG1 (0x27) 189 #define FEC_EN BIT(7) 190 #define WHITE_DATA BIT(6) 191 #define PN9_SWAP_EN BIT(5) 192 #define ADDR_CHECK_CFG(_cfg_) (_cfg_ & 0x18) 193 #define ADDR_NO_CHK (0) 194 #define ADDR_CHK_NO_BROADCAST (1 << 3) 195 #define ADDR_CHK_BROADCAST_00 (2 << 3) 196 #define ADDR_CHK_BROADCAST_FF (3 << 3) 197 #define CRC_CFG(_cfg_) (_cfg_ & 0x06) 198 #define CRC_NONE (0) 199 #define CRC_FFFF (1 << 1) 200 #define CRC_0000 (2 << 1) 201 #define CRC_1D0F (3 << 1) 202 #define APPEND_STATUS BIT(0) 203 204 #define CC1200_REG_PKT_CFG0 (0x28) 205 #define LENGTH_CONFIG(_cfg_) (_cfg_ & 0x60) 206 #define LENGTH_FIXED (0) 207 #define LENGTH_VAR_1 (1 << 5) 208 #define LENGTH_INFINITE (2 << 5) 209 #define LENGTH_VAR_2 (3 << 5) 210 #define PKT_BIT_LEN(_cfg_) (_cfg_ & 0x1C) 211 #define UART_MODE_EN BIT(1) 212 #define UART_SWAP_EN BIT(0) 213 214 #define CC1200_REG_RFEND_CFG1 (0x29) 215 #define RXOFF_MODE(_cfg_) (_cfg_ & 0x30) 216 #define RX_TIME(_cfg_) (_cfg_ & 0x0E) 217 #define RX_TIME_QUAL BIT(0) 218 219 #define CC1200_REG_RFEND_CFG0 (0x2A) 220 #define CAL_END_WAKE_UP_EN BIT(6) 221 #define TXOFF_MODE(_cfg_) (_cfg_ & 0x30) 222 #define TERM_ON_BAD_PACKET_EN BIT(3) 223 #define ANT_DIV_RX_TERM_CFG(_cfg_) (_cfg_ & 0x07) 224 225 /* Common RFEND tx/rx mode */ 226 #define RFEND_TXRX_MODE_IDLE (0) 227 #define RFEND_TXRX_MODE_FSTXON (1 << 4) 228 #define RFEND_TXRX_MODE_TX (2 << 4) 229 #define RFEND_TXRX_MODE_RX (3 << 4) 230 231 #define CC1200_REG_PA_CFG1 (0x2B) 232 #define PA_RAMP_SHAPE_EN BIT(6) 233 #define PA_POWER_RAMP_MASK (0x3F) 234 235 #define CC1200_REG_PA_CFG0 (0x2C) 236 #define FIRST_IPL(_cfg_) (_cfg_ & 0xE0) 237 #define SECOND_IPL(_cfg_) (_cfg_ & 0x1C) 238 #define RAMP_SHAPE(_cfg_) (_cfg_ & 0x03) 239 240 #define CC1200_REG_ASK_CFG (0x2D) 241 #define AGC_ASK_BW(_cfg_) (_cfg_ & 0xC0) 242 #define ASK_DEPTH(_cfg_) (_cfg_ & 0x3F) 243 244 #define CC1200_REG_PKT_LEN (0x2E) 245 #define CC1200_REG_EXTENDED_ADDRESS (0x2F) 246 247 /* Command strobes */ 248 #define CC1200_INS_SRES (0x30) 249 #define CC1200_INS_SFSTXON (0x31) 250 #define CC1200_INS_SXOFF (0x32) 251 #define CC1200_INS_SCAL (0x33) 252 #define CC1200_INS_SRX (0x34) 253 #define CC1200_INS_STX (0x35) 254 #define CC1200_INS_SIDLE (0x36) 255 #define CC1200_INS_SAFC (0x37) 256 #define CC1200_INS_SWOR (0x38) 257 #define CC1200_INS_SPWD (0x39) 258 #define CC1200_INS_SFRX (0x3A) 259 #define CC1200_INS_SFTX (0x3B) 260 #define CC1200_INS_SWORRST (0x3C) 261 #define CC1200_INS_SNOP (0x3D) 262 263 /* Memory access */ 264 #define CC1200_MEM_DMA (0x3E) 265 #define CC1200_MEM_STD (0x3F) 266 267 /* FIFO access */ 268 #define CC1200_REG_TXFIFO (0x3F) 269 #define CC1200_REG_RXFIFO (0x3F) 270 271 /* Configuration registers (Extended register space) */ 272 #define CC1200_REG_IF_MIX_CFG (0x00) 273 #define CC1200_REG_FREQOFF_CFG (0x01) 274 #define CC1200_REG_TOC_CFG (0x02) 275 #define CC1200_REG_MARC_SPARE (0x03) 276 #define CC1200_REG_ECG_CFG (0x04) 277 #define CC1200_REG_MDMCFG2 (0x05) 278 #define CC1200_REG_EXT_CTRL (0x06) 279 #define CC1200_REG_RCCAL_FINE (0x07) 280 #define CC1200_REG_RCCAL_COARSE (0x08) 281 #define CC1200_REG_RCCAL_OFFSET (0x09) 282 #define CC1200_REG_FREQOFF1 (0x0A) 283 #define CC1200_REG_FREQOFF0 (0x0B) 284 #define CC1200_REG_FREQ2 (0x0C) 285 #define CC1200_REG_FREQ1 (0x0D) 286 #define CC1200_REG_FREQ0 (0x0E) 287 #define CC1200_REG_IF_ADC2 (0x0F) 288 #define CC1200_REG_IF_ADC1 (0x10) 289 #define CC1200_REG_IF_ADC0 (0x11) 290 #define CC1200_REG_FS_DIG1 (0x12) 291 #define CC1200_REG_FS_DIG0 (0x13) 292 #define CC1200_REG_FS_CAL3 (0x14) 293 #define CC1200_REG_FS_CAL2 (0x15) 294 #define CC1200_REG_FS_CAL1 (0x16) 295 #define CC1200_REG_FS_CAL0 (0x17) 296 #define CC1200_REG_FS_CHP (0x18) 297 #define CC1200_REG_FS_DIVTWO (0x19) 298 #define CC1200_REG_FS_DSM1 (0x1A) 299 #define CC1200_REG_FS_DSM0 (0x1B) 300 #define CC1200_REG_FS_DVC1 (0x1C) 301 #define CC1200_REG_FS_DVC0 (0x1D) 302 #define CC1200_REG_FS_LBI (0x1E) 303 #define CC1200_REG_FS_PFD (0x1F) 304 #define CC1200_REG_FS_PRE (0x20) 305 #define CC1200_REG_FS_REG_DIV_CML (0x21) 306 #define CC1200_REG_FS_SPARE (0x22) 307 #define CC1200_REG_FS_VCO4 (0x23) 308 #define CC1200_REG_FS_VCO3 (0x24) 309 #define CC1200_REG_FS_VCO2 (0x25) 310 #define CC1200_REG_FS_VCO1 (0x26) 311 #define CC1200_REG_FS_VCO0 (0x27) 312 #define CC1200_REG_GBIAS6 (0x28) 313 #define CC1200_REG_GBIAS5 (0x29) 314 #define CC1200_REG_GBIAS4 (0x2A) 315 #define CC1200_REG_GBIAS3 (0x2B) 316 #define CC1200_REG_GBIAS2 (0x2C) 317 #define CC1200_REG_GBIAS1 (0x2D) 318 #define CC1200_REG_GBIAS0 (0x2E) 319 #define CC1200_REG_IFAMP (0x2F) 320 #define CC1200_REG_LNA (0x30) 321 #define CC1200_REG_RXMIX (0x31) 322 #define CC1200_REG_XOSC5 (0x32) 323 #define CC1200_REG_XOSC4 (0x33) 324 #define CC1200_REG_XOSC3 (0x34) 325 #define CC1200_REG_XOSC2 (0x35) 326 #define CC1200_REG_XOSC1 (0x36) 327 #define CC1200_REG_XOSC0 (0x37) 328 #define CC1200_REG_ANALOG_SPARE (0x38) 329 #define CC1200_REG_PA_CFG3 (0x39) 330 /* All addresses in between are unused ones */ 331 #define CC1200_REG_WOR_TIME1 (0x64) 332 #define CC1200_REG_WOR_TIME0 (0x65) 333 #define CC1200_REG_WOR_CAPTURE1 (0x66) 334 #define CC1200_REG_WOR_CAPTURE0 (0x67) 335 #define CC1200_REG_BIST (0x68) 336 #define CC1200_REG_DCFILTOFFSET_I1 (0x69) 337 #define CC1200_REG_DCFILTOFFSET_I0 (0x6A) 338 #define CC1200_REG_DCFILTOFFSET_Q1 (0x6B) 339 #define CC1200_REG_DCFILTOFFSET_Q0 (0x6C) 340 #define CC1200_REG_IQIE_I1 (0x6D) 341 #define CC1200_REG_IQIE_I0 (0x6E) 342 #define CC1200_REG_IQIE_Q1 (0x6F) 343 #define CC1200_REG_IQIE_Q0 (0x70) 344 #define CC1200_REG_RSSI1 (0x71) 345 346 #define CC1200_REG_RSSI0 (0x72) 347 #define RSSI(_reg_) ((_reg_ & 0x78) >> 3) 348 #define CARRIER_SENSE BIT(2) 349 #define CARRIER_SENSE_VALID BIT(1) 350 #define RSSI_VALID BIT(0) 351 352 #define CC1200_REG_MARCSTATE (0x73) 353 #define CC1200_REG_LQI_VAL (0x74) 354 #define CC1200_REG_PQT_SYNC_ERR (0x75) 355 #define CC1200_REG_DEM_STATUS (0x76) 356 #define CC1200_REG_FREQOFF_EST1 (0x77) 357 #define CC1200_REG_FREQOFF_EST0 (0x78) 358 #define CC1200_REG_AGC_GAIN3 (0x79) 359 #define CC1200_REG_AGC_GAIN2 (0x7A) 360 #define CC1200_REG_AGC_GAIN1 (0x7B) 361 #define CC1200_REG_AGC_GAIN0 (0x7C) 362 #define CC1200_REG_CFM_RX_DATA_OUT (0x7D) 363 #define CC1200_REG_CFM_RX_DATA_IN (0x7E) 364 #define CC1200_REG_ASK_SOFT_RX_DATA (0x7F) 365 #define CC1200_REG_RNDGEN (0x80) 366 #define CC1200_REG_MAGN2 (0x81) 367 #define CC1200_REG_MAGN1 (0x82) 368 #define CC1200_REG_MAGN0 (0x83) 369 #define CC1200_REG_ANG1 (0x84) 370 #define CC1200_REG_ANG0 (0x85) 371 #define CC1200_REG_CHFILT_I2 (0x86) 372 #define CC1200_REG_CHFILT_I1 (0x87) 373 #define CC1200_REG_CHFILT_I0 (0x88) 374 #define CC1200_REG_CHFILT_Q2 (0x89) 375 #define CC1200_REG_CHFILT_Q1 (0x8A) 376 #define CC1200_REG_CHFILT_Q0 (0x8B) 377 #define CC1200_REG_GPIO_STATUS (0x8C) 378 #define CC1200_REG_FSCAL_CTRL (0x8D) 379 #define CC1200_REG_PHASE_ADJUST (0x8E) 380 #define CC1200_REG_PARTNUMBER (0x8F) 381 #define CC1200_REG_PARTVERSION (0x90) 382 #define CC1200_REG_SERIAL_STATUS (0x91) 383 #define CC1200_REG_MODEM_STATUS1 (0x92) 384 #define CC1200_REG_MODEM_STATUS0 (0x93) 385 #define CC1200_REG_MARC_STATUS1 (0x94) 386 #define CC1200_REG_MARC_STATUS0 (0x95) 387 #define CC1200_REG_PA_IFAMP_TEST (0x96) 388 #define CC1200_REG_FSRF_TEST (0x97) 389 #define CC1200_REG_PRE_TEST (0x98) 390 #define CC1200_REG_PRE_OVR (0x99) 391 #define CC1200_REG_ADC_TEST (0x9A) 392 #define CC1200_REG_DVC_TEST (0x9B) 393 #define CC1200_REG_ATEST (0x9C) 394 #define CC1200_REG_ATEST_LVDS (0x9D) 395 #define CC1200_REG_ATEST_MODE (0x9E) 396 #define CC1200_REG_XOSC_TEST1 (0x9F) 397 #define CC1200_REG_XOSC_TEST0 (0xA0) 398 #define CC1200_REG_AES (0xA1) 399 #define CC1200_REG_MDM_TEST (0xA2) 400 /* All addresses in between are unused ones */ 401 #define CC1200_REG_RXFIRST (0xD2) 402 #define CC1200_REG_TXFIRST (0xD3) 403 #define CC1200_REG_RXLAST (0xD4) 404 #define CC1200_REG_TXLAST (0xD5) 405 #define CC1200_REG_NUM_TXBYTES (0xD6) 406 #define CC1200_REG_NUM_RXBYTES (0xD7) 407 #define CC1200_REG_FIFO_NUM_TXBYTES (0xD8) 408 #define CC1200_REG_FIFO_NUM_RXBYTES (0xD9) 409 #define CC1200_REG_RXFIFO_PRE_BUF (0xDA) 410 /* All addresses in between are unused ones */ 411 #define CC1200_REG_AES_WORKSPACE (0xE0) 412 413 414 /* Useful values 415 *************** 416 */ 417 418 419 /* GPIO signals - See Section 3.4.1.1 420 * Note: some signals are only available on certain GPIO 421 * thus the number CC1200_GPIOn_(...) on some which 422 * tells the GPIO line where that signal is valid. 423 */ 424 #define CC1200_GPIO_SIG_RXFIFO_THR (0) 425 #define CC1200_GPIO_SIG_RXFIFO_THR_PKT (1) 426 #define CC1200_GPIO_SIG_TXFIFO_THR (2) 427 #define CC1200_GPIO_SIG_TXFIFO_THR_PKT (3) 428 #define CC1200_GPIO_SIG_RXFIFO_OVERFLOW (4) 429 #define CC1200_GPIO_SIG_TXFIFO_UNDERFLOW (5) 430 #define CC1200_GPIO_SIG_PKT_SYNC_RXTX (6) 431 #define CC1200_GPIO_SIG_CRC_OK (7) 432 #define CC1200_GPIO_SIG_SERIAL_CLK (8) 433 #define CC1200_GPIO_SIG_SERIAL_RX (9) 434 #define CC1200_GPIO_SIG_PQT_REACHED (11) 435 #define CC1200_GPIO_SIG_PQT_VALID (12) 436 #define CC1200_GPIO_SIG_RSSI_VALID (13) 437 #define CC1200_GPIO3_SIG_RSSI_UPDATE (14) 438 #define CC1200_GPIO2_SIG_RSSI_UPDATE (14) 439 #define CC1200_GPIO1_SIG_AGC_HOLD (14) 440 #define CC1200_GPIO0_SIG_AGC_UPDATE (14) 441 #define CC1200_GPIO3_SIG_CCA_STATUS (15) 442 #define CC1200_GPIO2_SIG_TXONCCA_DONE (15) 443 #define CC1200_GPIO1_SIG_CCA_STATUS (15) 444 #define CC1200_GPIO0_SIG_TXONCCA_FAILED (15) 445 #define CC1200_GPIO_SIG_CARRIER_SENSE_VALID (16) 446 #define CC1200_GPIO_SIG_CARRIER_SENSE (17) 447 #define CC1200_GPIO3_SIG_DSSS_CLK (18) 448 #define CC1200_GPIO2_SIG_DSSS_DATA0 (18) 449 #define CC1200_GPIO1_SIG_DSSS_CLK (18) 450 #define CC1200_GPIO0_SIG_DSSS_DATA1 (18) 451 #define CC1200_GPIO_SIG_PKT_CRC_OK (19) 452 #define CC1200_GPIO_SIG_MCU_WAKEUP (20) 453 #define CC1200_GPIO_SIG_SYNC_LOW0_HIGH1 (21) 454 #define CC1200_GPIO0_SIG_AES_COMMAND_ACTIVE (22) 455 #define CC1200_GPIO_SIG_LNA_PA_REG_PD (23) 456 #define CC1200_GPIO_SIG_LNA_PD (24) 457 #define CC1200_GPIO_SIG_PA_PD (25) 458 #define CC1200_GPIO_SIG_RX0TX1_CFG (26) 459 #define CC1200_GPIO_SIG_IMAGE_FOUND (28) 460 #define CC1200_GPIO_SIG_CLKEN_CFM (29) 461 #define CC1200_GPIO_SIG_CFM_TX_DATA_CLK (30) 462 #define CC1200_GPIO_SIG_RSSI_STEP_FOUND (33) 463 #define CC1200_GPIO3_SIG_AES_RUN (34) 464 #define CC1200_GPIO2_SIG_AES_RUN (34) 465 #define CC1200_GPIO1_SIG_RSSI_STEP_EVENT (34) 466 #define CC1200_GPIO0_SIG_RSSI_STEP_EVENT (34) 467 #define CC1200_GPIO1_SIG_LOCK (35) 468 #define CC1200_GPIO0_SIG_LOCK (35) 469 #define CC1200_GPIO_SIG_ANTENNA_SELECT (36) 470 #define CC1200_GPIO_SIG_MARC_2PIN_STATUS_1 (37) 471 #define CC1200_GPIO_SIG_MARC_2PIN_STATUS_0 (38) 472 #define CC1200_GPIO2_SIG_TXFIFO_OVERFLOW (39) 473 #define CC1200_GPIO0_SIG_RXFIFO_UNDERFLOW (39) 474 #define CC1200_GPIO3_SIG_MAGN_VALID (40) 475 #define CC1200_GPIO2_SIG_CHFILT_VALID (40) 476 #define CC1200_GPIO1_SIG_RCC_CAL_VALID (40) 477 #define CC1200_GPIO0_SIG_CHFILT_STARTUP_VALID (40) 478 #define CC1200_GPIO3_SIG_COLLISION_FOUND (41) 479 #define CC1200_GPIO2_SIG_SYNC_EVENT (41) 480 #define CC1200_GPIO1_SIG_COLLISION_FOUND (41) 481 #define CC1200_GPIO0_SIG_COLLISION_EVENT (41) 482 #define CC1200_GPIO_SIG_PA_RAMP_UP (42) 483 #define CC1200_GPIO3_SIG_CRC_FAILED (43) 484 #define CC1200_GPIO2_SIG_LENGTH_FAILED (43) 485 #define CC1200_GPIO1_SIG_ADDR_FAILED (43) 486 #define CC1200_GPIO0_SIG_UART_FRAMING_ERROR (43) 487 #define CC1200_GPIO_SIG_AGC_STABLE_GAIN (44) 488 #define CC1200_GPIO_SIG_AGC_UPDATE (45) 489 #define CC1200_GPIO3_SIG_ADC_CLOCK (46) 490 #define CC1200_GPIO2_SIG_ADC_Q_DATA_SAMPLE (46) 491 #define CC1200_GPIO1_SIG_ADC_CLOCK (46) 492 #define CC1200_GPIO0_SIG_ADC_I_DATA_SAMPLE (46) 493 #define CC1200_GPIO_SIG_HIGHZ (48) 494 #define CC1200_GPIO_SIG_EXT_CLOCK (49) 495 #define CC1200_GPIO_SIG_CHIP_RDYn (50) 496 #define CC1200_GPIO_SIG_HW0 (51) 497 #define CC1200_GPIO_SIG_CLOCK_40K (54) 498 #define CC1200_GPIO_SIG_WOR_EVENT0 (55) 499 #define CC1200_GPIO_SIG_WOR_EVENT1 (56) 500 #define CC1200_GPIO_SIG_WOR_EVENT2 (57) 501 #define CC1200_GPIO_SIG_XOSC_STABLE (59) 502 #define CC1200_GPIO_SIG_EXT_OSC_EN (60) 503 504 /* Chip status - See Section 3.1.2 */ 505 #define CC1200_STATUS_CHIP_NOT_READY BIT(7) 506 #define CC1200_STATUS_IDLE (0x00) 507 #define CC1200_STATUS_RX (0x01 << 4) 508 #define CC1200_STATUS_TX (0x02 << 4) 509 #define CC1200_STATUS_FSTXON (0x03 << 4) 510 #define CC1200_STATUS_CALIBRATE (0x04 << 4) 511 #define CC1200_STATUS_SETTLING (0x05 << 4) 512 #define CC1200_STATUS_RX_FIFO_ERROR (0x06 << 4) 513 #define CC1200_STATUS_TX_FIFO_ERROR (0x07 << 4) 514 #define CC1200_STATUS_MASK (0x70) 515 516 /* Appended FCS - See Section 8 */ 517 #define CC1200_FCS_LEN (2) 518 #define CC1200_FCS_CRC_OK BIT(7) 519 #define CC1200_FCS_LQI_MASK (0x7F) 520 521 /* ToDo: supporting 802.15.4g will make this header of a different size */ 522 #define CC1200_PHY_HDR_LEN (1) 523 524 #endif /* ZEPHYR_DRIVERS_IEEE802154_IEEE802154_CC1200_REGS_H_ */ 525
