1 /*
2 * Copyright (c) 2022 Vestas Wind Systems A/S
3 * Copyright (c) 2020 Alexander Wachter
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #include <zephyr/drivers/can.h>
9 #include <zephyr/drivers/can/can_mcan.h>
10 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
11 #include <zephyr/drivers/clock_control.h>
12 #include <zephyr/drivers/pinctrl.h>
13 #include <zephyr/kernel.h>
14 #include <zephyr/sys/__assert.h>
15 #include <soc.h>
16 #include <stm32_ll_rcc.h>
17 #include <zephyr/logging/log.h>
18 #include <zephyr/irq.h>
19
20 LOG_MODULE_REGISTER(can_stm32fd, CONFIG_CAN_LOG_LEVEL);
21
22 #define DT_DRV_COMPAT st_stm32_fdcan
23
24 /*
25 * The STMicroelectronics STM32 FDCAN definitions correspond to those found in the
26 * STMicroelectronics STM32G4 Series Reference manual (RM0440), Rev 7.
27 *
28 * This controller uses a Bosch M_CAN like register layout, but some registers are unimplemented,
29 * some registers are mapped to other register offsets, and some registers have had their bit fields
30 * remapped.
31 *
32 * Apart from the definitions below please note the following limitations:
33 * - TEST register SVAL, TXBNS, PVAL, and TXBNP bits are not available.
34 * - CCCR register VMM and UTSU bits are not available.
35 * - TXBC register TFQS, NDTB, and TBSA fields are not available.
36 */
37
38 /* Interrupt register */
39 #define CAN_STM32FD_IR_ARA BIT(23)
40 #define CAN_STM32FD_IR_PED BIT(22)
41 #define CAN_STM32FD_IR_PEA BIT(21)
42 #define CAN_STM32FD_IR_WDI BIT(20)
43 #define CAN_STM32FD_IR_BO BIT(19)
44 #define CAN_STM32FD_IR_EW BIT(18)
45 #define CAN_STM32FD_IR_EP BIT(17)
46 #define CAN_STM32FD_IR_ELO BIT(16)
47 #define CAN_STM32FD_IR_TOO BIT(15)
48 #define CAN_STM32FD_IR_MRAF BIT(14)
49 #define CAN_STM32FD_IR_TSW BIT(13)
50 #define CAN_STM32FD_IR_TEFL BIT(12)
51 #define CAN_STM32FD_IR_TEFF BIT(11)
52 #define CAN_STM32FD_IR_TEFN BIT(10)
53 #define CAN_STM32FD_IR_TFE BIT(9)
54 #define CAN_STM32FD_IR_TCF BIT(8)
55 #define CAN_STM32FD_IR_TC BIT(7)
56 #define CAN_STM32FD_IR_HPM BIT(6)
57 #define CAN_STM32FD_IR_RF1L BIT(5)
58 #define CAN_STM32FD_IR_RF1F BIT(4)
59 #define CAN_STM32FD_IR_RF1N BIT(3)
60 #define CAN_STM32FD_IR_RF0L BIT(2)
61 #define CAN_STM32FD_IR_RF0F BIT(1)
62 #define CAN_STM32FD_IR_RF0N BIT(0)
63
64 /* Interrupt Enable register */
65 #define CAN_STM32FD_IE_ARAE BIT(23)
66 #define CAN_STM32FD_IE_PEDE BIT(22)
67 #define CAN_STM32FD_IE_PEAE BIT(21)
68 #define CAN_STM32FD_IE_WDIE BIT(20)
69 #define CAN_STM32FD_IE_BOE BIT(19)
70 #define CAN_STM32FD_IE_EWE BIT(18)
71 #define CAN_STM32FD_IE_EPE BIT(17)
72 #define CAN_STM32FD_IE_ELOE BIT(16)
73 #define CAN_STM32FD_IE_TOOE BIT(15)
74 #define CAN_STM32FD_IE_MRAFE BIT(14)
75 #define CAN_STM32FD_IE_TSWE BIT(13)
76 #define CAN_STM32FD_IE_TEFLE BIT(12)
77 #define CAN_STM32FD_IE_TEFFE BIT(11)
78 #define CAN_STM32FD_IE_TEFNE BIT(10)
79 #define CAN_STM32FD_IE_TFEE BIT(9)
80 #define CAN_STM32FD_IE_TCFE BIT(8)
81 #define CAN_STM32FD_IE_TCE BIT(7)
82 #define CAN_STM32FD_IE_HPME BIT(6)
83 #define CAN_STM32FD_IE_RF1LE BIT(5)
84 #define CAN_STM32FD_IE_RF1FE BIT(4)
85 #define CAN_STM32FD_IE_RF1NE BIT(3)
86 #define CAN_STM32FD_IE_RF0LE BIT(2)
87 #define CAN_STM32FD_IE_RF0FE BIT(1)
88 #define CAN_STM32FD_IE_RF0NE BIT(0)
89
90 /* Interrupt Line Select register */
91 #define CAN_STM32FD_ILS_PERR BIT(6)
92 #define CAN_STM32FD_ILS_BERR BIT(5)
93 #define CAN_STM32FD_ILS_MISC BIT(4)
94 #define CAN_STM32FD_ILS_TFERR BIT(3)
95 #define CAN_STM32FD_ILS_SMSG BIT(2)
96 #define CAN_STM32FD_ILS_RXFIFO1 BIT(1)
97 #define CAN_STM32FD_ILS_RXFIFO0 BIT(0)
98
99 /* Global filter configuration register */
100 #define CAN_STM32FD_RXGFC 0x080
101 #define CAN_STM32FD_RXGFC_LSE GENMASK(27, 24)
102 #define CAN_STM32FD_RXGFC_LSS GENMASK(20, 16)
103 #define CAN_STM32FD_RXGFC_F0OM BIT(9)
104 #define CAN_STM32FD_RXGFC_F1OM BIT(8)
105 #define CAN_STM32FD_RXGFC_ANFS GENMASK(5, 4)
106 #define CAN_STM32FD_RXGFC_ANFE GENMASK(3, 2)
107 #define CAN_STM32FD_RXGFC_RRFS BIT(1)
108 #define CAN_STM32FD_RXGFC_RRFE BIT(0)
109
110 /* Extended ID AND Mask register */
111 #define CAN_STM32FD_XIDAM 0x084
112
113 /* High Priority Message Status register */
114 #define CAN_STM32FD_HPMS 0x088
115
116 /* Rx FIFO 0 Status register */
117 #define CAN_STM32FD_RXF0S 0x090
118
119 /* Rx FIFO 0 Acknowledge register */
120 #define CAN_STM32FD_RXF0A 0x094
121
122 /* Rx FIFO 1 Status register */
123 #define CAN_STM32FD_RXF1S 0x098
124
125 /* Rx FIFO 1 Acknowledge register */
126 #define CAN_STM32FD_RXF1A 0x09C
127
128 /* Tx Buffer Configuration register */
129 #define CAN_STM32FD_TXBC_TFQM BIT(24)
130
131 /* Tx Buffer Request Pending register */
132 #define CAN_STM32FD_TXBRP 0x0C8
133
134 /* Tx Buffer Add Request register */
135 #define CAN_STM32FD_TXBAR 0x0CC
136
137 /* Tx Buffer Cancellation Request register */
138 #define CAN_STM32FD_TXBCR 0x0D0
139
140 /* Tx Buffer Transmission Occurred register */
141 #define CAN_STM32FD_TXBTO 0x0D4
142
143 /* Tx Buffer Cancellation Finished register */
144 #define CAN_STM32FD_TXBCF 0x0D8
145
146 /* Tx Buffer Transmission Interrupt Enable register */
147 #define CAN_STM32FD_TXBTIE 0x0DC
148
149 /* Tx Buffer Cancellation Finished Interrupt Enable register */
150 #define CAN_STM32FD_TXBCIE 0x0E0
151
152 /* Tx Event FIFO Status register */
153 #define CAN_STM32FD_TXEFS 0x0E4
154
155 /* Tx Event FIFO Acknowledge register */
156 #define CAN_STM32FD_TXEFA 0x0E8
157
158 /* Register address indicating unsupported register */
159 #define CAN_STM32FD_REGISTER_UNSUPPORTED UINT16_MAX
160
161 /* This symbol takes the value 1 if one of the device instances */
162 /* is configured in dts with a domain clock */
163 #if STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT
164 #define STM32_CANFD_DOMAIN_CLOCK_SUPPORT 1
165 #else
166 #define STM32_CANFD_DOMAIN_CLOCK_SUPPORT 0
167 #endif
168
169 struct can_stm32fd_config {
170 mm_reg_t base;
171 mem_addr_t mram;
172 size_t pclk_len;
173 const struct stm32_pclken *pclken;
174 void (*config_irq)(void);
175 const struct pinctrl_dev_config *pcfg;
176 uint8_t clock_divider;
177 };
178
can_stm32fd_remap_reg(uint16_t reg)179 static inline uint16_t can_stm32fd_remap_reg(uint16_t reg)
180 {
181 uint16_t remap;
182
183 switch (reg) {
184 case CAN_MCAN_SIDFC:
185 __fallthrough;
186 case CAN_MCAN_XIDFC:
187 __fallthrough;
188 case CAN_MCAN_NDAT1:
189 __fallthrough;
190 case CAN_MCAN_NDAT2:
191 __fallthrough;
192 case CAN_MCAN_RXF0C:
193 __fallthrough;
194 case CAN_MCAN_RXBC:
195 __fallthrough;
196 case CAN_MCAN_RXF1C:
197 __fallthrough;
198 case CAN_MCAN_RXESC:
199 __fallthrough;
200 case CAN_MCAN_TXESC:
201 __fallthrough;
202 case CAN_MCAN_TXEFC:
203 __ASSERT_NO_MSG(false);
204 remap = CAN_STM32FD_REGISTER_UNSUPPORTED;
205 case CAN_MCAN_XIDAM:
206 remap = CAN_STM32FD_XIDAM;
207 break;
208 case CAN_MCAN_RXF0S:
209 remap = CAN_STM32FD_RXF0S;
210 break;
211 case CAN_MCAN_RXF0A:
212 remap = CAN_STM32FD_RXF0A;
213 break;
214 case CAN_MCAN_RXF1S:
215 remap = CAN_STM32FD_RXF1S;
216 break;
217 case CAN_MCAN_RXF1A:
218 remap = CAN_STM32FD_RXF1A;
219 break;
220 case CAN_MCAN_TXBRP:
221 remap = CAN_STM32FD_TXBRP;
222 break;
223 case CAN_MCAN_TXBAR:
224 remap = CAN_STM32FD_TXBAR;
225 break;
226 case CAN_MCAN_TXBCR:
227 remap = CAN_STM32FD_TXBCR;
228 break;
229 case CAN_MCAN_TXBTO:
230 remap = CAN_STM32FD_TXBTO;
231 break;
232 case CAN_MCAN_TXBCF:
233 remap = CAN_STM32FD_TXBCF;
234 break;
235 case CAN_MCAN_TXBTIE:
236 remap = CAN_STM32FD_TXBTIE;
237 break;
238 case CAN_MCAN_TXBCIE:
239 remap = CAN_STM32FD_TXBCIE;
240 break;
241 case CAN_MCAN_TXEFS:
242 remap = CAN_STM32FD_TXEFS;
243 break;
244 case CAN_MCAN_TXEFA:
245 remap = CAN_STM32FD_TXEFA;
246 break;
247 default:
248 /* No register address remap needed */
249 remap = reg;
250 break;
251 };
252
253 return remap;
254 }
255
can_stm32fd_read_reg(const struct device * dev,uint16_t reg,uint32_t * val)256 static int can_stm32fd_read_reg(const struct device *dev, uint16_t reg, uint32_t *val)
257 {
258 const struct can_mcan_config *mcan_config = dev->config;
259 const struct can_stm32fd_config *stm32fd_config = mcan_config->custom;
260 uint16_t remap;
261 uint32_t bits;
262 int err;
263
264 remap = can_stm32fd_remap_reg(reg);
265 if (remap == CAN_STM32FD_REGISTER_UNSUPPORTED) {
266 return -ENOTSUP;
267 }
268
269 err = can_mcan_sys_read_reg(stm32fd_config->base, remap, &bits);
270 if (err != 0) {
271 return err;
272 }
273
274 *val = 0U;
275
276 switch (reg) {
277 case CAN_MCAN_IR:
278 /* Remap IR bits */
279 *val |= FIELD_PREP(CAN_MCAN_IR_ARA, FIELD_GET(CAN_STM32FD_IR_ARA, bits));
280 *val |= FIELD_PREP(CAN_MCAN_IR_PED, FIELD_GET(CAN_STM32FD_IR_PED, bits));
281 *val |= FIELD_PREP(CAN_MCAN_IR_PEA, FIELD_GET(CAN_STM32FD_IR_PEA, bits));
282 *val |= FIELD_PREP(CAN_MCAN_IR_WDI, FIELD_GET(CAN_STM32FD_IR_WDI, bits));
283 *val |= FIELD_PREP(CAN_MCAN_IR_BO, FIELD_GET(CAN_STM32FD_IR_BO, bits));
284 *val |= FIELD_PREP(CAN_MCAN_IR_EW, FIELD_GET(CAN_STM32FD_IR_EW, bits));
285 *val |= FIELD_PREP(CAN_MCAN_IR_EP, FIELD_GET(CAN_STM32FD_IR_EP, bits));
286 *val |= FIELD_PREP(CAN_MCAN_IR_ELO, FIELD_GET(CAN_STM32FD_IR_ELO, bits));
287 *val |= FIELD_PREP(CAN_MCAN_IR_TOO, FIELD_GET(CAN_STM32FD_IR_TOO, bits));
288 *val |= FIELD_PREP(CAN_MCAN_IR_MRAF, FIELD_GET(CAN_STM32FD_IR_MRAF, bits));
289 *val |= FIELD_PREP(CAN_MCAN_IR_TSW, FIELD_GET(CAN_STM32FD_IR_TSW, bits));
290 *val |= FIELD_PREP(CAN_MCAN_IR_TEFL, FIELD_GET(CAN_STM32FD_IR_TEFL, bits));
291 *val |= FIELD_PREP(CAN_MCAN_IR_TEFF, FIELD_GET(CAN_STM32FD_IR_TEFF, bits));
292 *val |= FIELD_PREP(CAN_MCAN_IR_TEFN, FIELD_GET(CAN_STM32FD_IR_TEFN, bits));
293 *val |= FIELD_PREP(CAN_MCAN_IR_TFE, FIELD_GET(CAN_STM32FD_IR_TFE, bits));
294 *val |= FIELD_PREP(CAN_MCAN_IR_TCF, FIELD_GET(CAN_STM32FD_IR_TCF, bits));
295 *val |= FIELD_PREP(CAN_MCAN_IR_TC, FIELD_GET(CAN_STM32FD_IR_TC, bits));
296 *val |= FIELD_PREP(CAN_MCAN_IR_HPM, FIELD_GET(CAN_STM32FD_IR_HPM, bits));
297 *val |= FIELD_PREP(CAN_MCAN_IR_RF1L, FIELD_GET(CAN_STM32FD_IR_RF1L, bits));
298 *val |= FIELD_PREP(CAN_MCAN_IR_RF1F, FIELD_GET(CAN_STM32FD_IR_RF1F, bits));
299 *val |= FIELD_PREP(CAN_MCAN_IR_RF1N, FIELD_GET(CAN_STM32FD_IR_RF1N, bits));
300 *val |= FIELD_PREP(CAN_MCAN_IR_RF0L, FIELD_GET(CAN_STM32FD_IR_RF0L, bits));
301 *val |= FIELD_PREP(CAN_MCAN_IR_RF0F, FIELD_GET(CAN_STM32FD_IR_RF0F, bits));
302 *val |= FIELD_PREP(CAN_MCAN_IR_RF0N, FIELD_GET(CAN_STM32FD_IR_RF0N, bits));
303 break;
304 case CAN_MCAN_IE:
305 /* Remap IE bits */
306 *val |= FIELD_PREP(CAN_MCAN_IE_ARAE, FIELD_GET(CAN_STM32FD_IE_ARAE, bits));
307 *val |= FIELD_PREP(CAN_MCAN_IE_PEDE, FIELD_GET(CAN_STM32FD_IE_PEDE, bits));
308 *val |= FIELD_PREP(CAN_MCAN_IE_PEAE, FIELD_GET(CAN_STM32FD_IE_PEAE, bits));
309 *val |= FIELD_PREP(CAN_MCAN_IE_WDIE, FIELD_GET(CAN_STM32FD_IE_WDIE, bits));
310 *val |= FIELD_PREP(CAN_MCAN_IE_BOE, FIELD_GET(CAN_STM32FD_IE_BOE, bits));
311 *val |= FIELD_PREP(CAN_MCAN_IE_EWE, FIELD_GET(CAN_STM32FD_IE_EWE, bits));
312 *val |= FIELD_PREP(CAN_MCAN_IE_EPE, FIELD_GET(CAN_STM32FD_IE_EPE, bits));
313 *val |= FIELD_PREP(CAN_MCAN_IE_ELOE, FIELD_GET(CAN_STM32FD_IE_ELOE, bits));
314 *val |= FIELD_PREP(CAN_MCAN_IE_TOOE, FIELD_GET(CAN_STM32FD_IE_TOOE, bits));
315 *val |= FIELD_PREP(CAN_MCAN_IE_MRAFE, FIELD_GET(CAN_STM32FD_IE_MRAFE, bits));
316 *val |= FIELD_PREP(CAN_MCAN_IE_TSWE, FIELD_GET(CAN_STM32FD_IE_TSWE, bits));
317 *val |= FIELD_PREP(CAN_MCAN_IE_TEFLE, FIELD_GET(CAN_STM32FD_IE_TEFLE, bits));
318 *val |= FIELD_PREP(CAN_MCAN_IE_TEFFE, FIELD_GET(CAN_STM32FD_IE_TEFFE, bits));
319 *val |= FIELD_PREP(CAN_MCAN_IE_TEFNE, FIELD_GET(CAN_STM32FD_IE_TEFNE, bits));
320 *val |= FIELD_PREP(CAN_MCAN_IE_TFEE, FIELD_GET(CAN_STM32FD_IE_TFEE, bits));
321 *val |= FIELD_PREP(CAN_MCAN_IE_TCFE, FIELD_GET(CAN_STM32FD_IE_TCFE, bits));
322 *val |= FIELD_PREP(CAN_MCAN_IE_TCE, FIELD_GET(CAN_STM32FD_IE_TCE, bits));
323 *val |= FIELD_PREP(CAN_MCAN_IE_HPME, FIELD_GET(CAN_STM32FD_IE_HPME, bits));
324 *val |= FIELD_PREP(CAN_MCAN_IE_RF1LE, FIELD_GET(CAN_STM32FD_IE_RF1LE, bits));
325 *val |= FIELD_PREP(CAN_MCAN_IE_RF1FE, FIELD_GET(CAN_STM32FD_IE_RF1FE, bits));
326 *val |= FIELD_PREP(CAN_MCAN_IE_RF1NE, FIELD_GET(CAN_STM32FD_IE_RF1NE, bits));
327 *val |= FIELD_PREP(CAN_MCAN_IE_RF0LE, FIELD_GET(CAN_STM32FD_IE_RF0LE, bits));
328 *val |= FIELD_PREP(CAN_MCAN_IE_RF0FE, FIELD_GET(CAN_STM32FD_IE_RF0FE, bits));
329 *val |= FIELD_PREP(CAN_MCAN_IE_RF0NE, FIELD_GET(CAN_STM32FD_IE_RF0NE, bits));
330 break;
331 case CAN_MCAN_ILS:
332 /* Only remap ILS groups used in can_mcan.c */
333 if ((bits & CAN_STM32FD_ILS_RXFIFO1) != 0U) {
334 *val |= CAN_MCAN_ILS_RF1LL | CAN_MCAN_ILS_RF1FL | CAN_MCAN_ILS_RF1NL;
335 }
336
337 if ((bits & CAN_STM32FD_ILS_RXFIFO0) != 0U) {
338 *val |= CAN_MCAN_ILS_RF0LL | CAN_MCAN_ILS_RF0FL | CAN_MCAN_ILS_RF0NL;
339 }
340 break;
341 case CAN_MCAN_GFC:
342 /* Map fields from RXGFC excluding STM32 FDCAN LSS and LSE fields */
343 *val = bits & (CAN_MCAN_GFC_ANFS | CAN_MCAN_GFC_ANFE |
344 CAN_MCAN_GFC_RRFS | CAN_MCAN_GFC_RRFE);
345 break;
346 default:
347 /* No field remap needed */
348 *val = bits;
349 break;
350 };
351
352 return 0;
353 }
354
can_stm32fd_write_reg(const struct device * dev,uint16_t reg,uint32_t val)355 static int can_stm32fd_write_reg(const struct device *dev, uint16_t reg, uint32_t val)
356 {
357 const struct can_mcan_config *mcan_config = dev->config;
358 const struct can_stm32fd_config *stm32fd_config = mcan_config->custom;
359 uint32_t bits = 0U;
360 uint16_t remap;
361
362 remap = can_stm32fd_remap_reg(reg);
363 if (remap == CAN_STM32FD_REGISTER_UNSUPPORTED) {
364 return -ENOTSUP;
365 }
366
367 switch (reg) {
368 case CAN_MCAN_IR:
369 /* Remap IR bits, ignoring unsupported bits */
370 bits |= FIELD_PREP(CAN_STM32FD_IR_ARA, FIELD_GET(CAN_MCAN_IR_ARA, val));
371 bits |= FIELD_PREP(CAN_STM32FD_IR_PED, FIELD_GET(CAN_MCAN_IR_PED, val));
372 bits |= FIELD_PREP(CAN_STM32FD_IR_PEA, FIELD_GET(CAN_MCAN_IR_PEA, val));
373 bits |= FIELD_PREP(CAN_STM32FD_IR_WDI, FIELD_GET(CAN_MCAN_IR_WDI, val));
374 bits |= FIELD_PREP(CAN_STM32FD_IR_BO, FIELD_GET(CAN_MCAN_IR_BO, val));
375 bits |= FIELD_PREP(CAN_STM32FD_IR_EW, FIELD_GET(CAN_MCAN_IR_EW, val));
376 bits |= FIELD_PREP(CAN_STM32FD_IR_EP, FIELD_GET(CAN_MCAN_IR_EP, val));
377 bits |= FIELD_PREP(CAN_STM32FD_IR_ELO, FIELD_GET(CAN_MCAN_IR_ELO, val));
378 bits |= FIELD_PREP(CAN_STM32FD_IR_TOO, FIELD_GET(CAN_MCAN_IR_TOO, val));
379 bits |= FIELD_PREP(CAN_STM32FD_IR_MRAF, FIELD_GET(CAN_MCAN_IR_MRAF, val));
380 bits |= FIELD_PREP(CAN_STM32FD_IR_TSW, FIELD_GET(CAN_MCAN_IR_TSW, val));
381 bits |= FIELD_PREP(CAN_STM32FD_IR_TEFL, FIELD_GET(CAN_MCAN_IR_TEFL, val));
382 bits |= FIELD_PREP(CAN_STM32FD_IR_TEFF, FIELD_GET(CAN_MCAN_IR_TEFF, val));
383 bits |= FIELD_PREP(CAN_STM32FD_IR_TEFN, FIELD_GET(CAN_MCAN_IR_TEFN, val));
384 bits |= FIELD_PREP(CAN_STM32FD_IR_TFE, FIELD_GET(CAN_MCAN_IR_TFE, val));
385 bits |= FIELD_PREP(CAN_STM32FD_IR_TCF, FIELD_GET(CAN_MCAN_IR_TCF, val));
386 bits |= FIELD_PREP(CAN_STM32FD_IR_TC, FIELD_GET(CAN_MCAN_IR_TC, val));
387 bits |= FIELD_PREP(CAN_STM32FD_IR_HPM, FIELD_GET(CAN_MCAN_IR_HPM, val));
388 bits |= FIELD_PREP(CAN_STM32FD_IR_RF1L, FIELD_GET(CAN_MCAN_IR_RF1L, val));
389 bits |= FIELD_PREP(CAN_STM32FD_IR_RF1F, FIELD_GET(CAN_MCAN_IR_RF1F, val));
390 bits |= FIELD_PREP(CAN_STM32FD_IR_RF1N, FIELD_GET(CAN_MCAN_IR_RF1N, val));
391 bits |= FIELD_PREP(CAN_STM32FD_IR_RF0L, FIELD_GET(CAN_MCAN_IR_RF0L, val));
392 bits |= FIELD_PREP(CAN_STM32FD_IR_RF0F, FIELD_GET(CAN_MCAN_IR_RF0F, val));
393 bits |= FIELD_PREP(CAN_STM32FD_IR_RF0N, FIELD_GET(CAN_MCAN_IR_RF0N, val));
394 break;
395 case CAN_MCAN_IE:
396 /* Remap IE bits, ignoring unsupported bits */
397 bits |= FIELD_PREP(CAN_STM32FD_IE_ARAE, FIELD_GET(CAN_MCAN_IE_ARAE, val));
398 bits |= FIELD_PREP(CAN_STM32FD_IE_PEDE, FIELD_GET(CAN_MCAN_IE_PEDE, val));
399 bits |= FIELD_PREP(CAN_STM32FD_IE_PEAE, FIELD_GET(CAN_MCAN_IE_PEAE, val));
400 bits |= FIELD_PREP(CAN_STM32FD_IE_WDIE, FIELD_GET(CAN_MCAN_IE_WDIE, val));
401 bits |= FIELD_PREP(CAN_STM32FD_IE_BOE, FIELD_GET(CAN_MCAN_IE_BOE, val));
402 bits |= FIELD_PREP(CAN_STM32FD_IE_EWE, FIELD_GET(CAN_MCAN_IE_EWE, val));
403 bits |= FIELD_PREP(CAN_STM32FD_IE_EPE, FIELD_GET(CAN_MCAN_IE_EPE, val));
404 bits |= FIELD_PREP(CAN_STM32FD_IE_ELOE, FIELD_GET(CAN_MCAN_IE_ELOE, val));
405 bits |= FIELD_PREP(CAN_STM32FD_IE_TOOE, FIELD_GET(CAN_MCAN_IE_TOOE, val));
406 bits |= FIELD_PREP(CAN_STM32FD_IE_MRAFE, FIELD_GET(CAN_MCAN_IE_MRAFE, val));
407 bits |= FIELD_PREP(CAN_STM32FD_IE_TSWE, FIELD_GET(CAN_MCAN_IE_TSWE, val));
408 bits |= FIELD_PREP(CAN_STM32FD_IE_TEFLE, FIELD_GET(CAN_MCAN_IE_TEFLE, val));
409 bits |= FIELD_PREP(CAN_STM32FD_IE_TEFFE, FIELD_GET(CAN_MCAN_IE_TEFFE, val));
410 bits |= FIELD_PREP(CAN_STM32FD_IE_TEFNE, FIELD_GET(CAN_MCAN_IE_TEFNE, val));
411 bits |= FIELD_PREP(CAN_STM32FD_IE_TFEE, FIELD_GET(CAN_MCAN_IE_TFEE, val));
412 bits |= FIELD_PREP(CAN_STM32FD_IE_TCFE, FIELD_GET(CAN_MCAN_IE_TCFE, val));
413 bits |= FIELD_PREP(CAN_STM32FD_IE_TCE, FIELD_GET(CAN_MCAN_IE_TCE, val));
414 bits |= FIELD_PREP(CAN_STM32FD_IE_HPME, FIELD_GET(CAN_MCAN_IE_HPME, val));
415 bits |= FIELD_PREP(CAN_STM32FD_IE_RF1LE, FIELD_GET(CAN_MCAN_IE_RF1LE, val));
416 bits |= FIELD_PREP(CAN_STM32FD_IE_RF1FE, FIELD_GET(CAN_MCAN_IE_RF1FE, val));
417 bits |= FIELD_PREP(CAN_STM32FD_IE_RF1NE, FIELD_GET(CAN_MCAN_IE_RF1NE, val));
418 bits |= FIELD_PREP(CAN_STM32FD_IE_RF0LE, FIELD_GET(CAN_MCAN_IE_RF0LE, val));
419 bits |= FIELD_PREP(CAN_STM32FD_IE_RF0FE, FIELD_GET(CAN_MCAN_IE_RF0FE, val));
420 bits |= FIELD_PREP(CAN_STM32FD_IE_RF0NE, FIELD_GET(CAN_MCAN_IE_RF0NE, val));
421 break;
422 case CAN_MCAN_ILS:
423 /* Only remap ILS groups used in can_mcan.c */
424 if ((val & (CAN_MCAN_ILS_RF1LL | CAN_MCAN_ILS_RF1FL | CAN_MCAN_ILS_RF1NL)) != 0U) {
425 bits |= CAN_STM32FD_ILS_RXFIFO1;
426 }
427
428 if ((val & (CAN_MCAN_ILS_RF0LL | CAN_MCAN_ILS_RF0FL | CAN_MCAN_ILS_RF0NL)) != 0U) {
429 bits |= CAN_STM32FD_ILS_RXFIFO0;
430 }
431 break;
432 case CAN_MCAN_GFC:
433 /* Map fields to RXGFC including STM32 FDCAN LSS and LSE fields */
434 bits |= FIELD_PREP(CAN_STM32FD_RXGFC_LSS, CONFIG_CAN_MAX_STD_ID_FILTER) |
435 FIELD_PREP(CAN_STM32FD_RXGFC_LSE, CONFIG_CAN_MAX_EXT_ID_FILTER);
436 bits |= val & (CAN_MCAN_GFC_ANFS | CAN_MCAN_GFC_ANFE |
437 CAN_MCAN_GFC_RRFS | CAN_MCAN_GFC_RRFE);
438 break;
439 default:
440 /* No field remap needed */
441 bits = val;
442 break;
443 };
444
445 return can_mcan_sys_write_reg(stm32fd_config->base, remap, bits);
446 }
447
can_stm32fd_read_mram(const struct device * dev,uint16_t offset,void * dst,size_t len)448 static int can_stm32fd_read_mram(const struct device *dev, uint16_t offset, void *dst, size_t len)
449 {
450 const struct can_mcan_config *mcan_config = dev->config;
451 const struct can_stm32fd_config *stm32fd_config = mcan_config->custom;
452
453 return can_mcan_sys_read_mram(stm32fd_config->mram, offset, dst, len);
454 }
455
can_stm32fd_write_mram(const struct device * dev,uint16_t offset,const void * src,size_t len)456 static int can_stm32fd_write_mram(const struct device *dev, uint16_t offset, const void *src,
457 size_t len)
458 {
459 const struct can_mcan_config *mcan_config = dev->config;
460 const struct can_stm32fd_config *stm32fd_config = mcan_config->custom;
461
462 return can_mcan_sys_write_mram(stm32fd_config->mram, offset, src, len);
463 }
464
can_stm32fd_clear_mram(const struct device * dev,uint16_t offset,size_t len)465 static int can_stm32fd_clear_mram(const struct device *dev, uint16_t offset, size_t len)
466 {
467 const struct can_mcan_config *mcan_config = dev->config;
468 const struct can_stm32fd_config *stm32fd_config = mcan_config->custom;
469
470 return can_mcan_sys_clear_mram(stm32fd_config->mram, offset, len);
471 }
472
can_stm32fd_get_core_clock(const struct device * dev,uint32_t * rate)473 static int can_stm32fd_get_core_clock(const struct device *dev, uint32_t *rate)
474 {
475 const uint32_t rate_tmp = LL_RCC_GetFDCANClockFreq(LL_RCC_FDCAN_CLKSOURCE);
476
477 ARG_UNUSED(dev);
478
479 if (rate_tmp == LL_RCC_PERIPH_FREQUENCY_NO) {
480 LOG_ERR("Can't read core clock");
481 return -EIO;
482 }
483
484 if (FDCAN_CONFIG->CKDIV == 0) {
485 *rate = rate_tmp;
486 } else {
487 *rate = rate_tmp / (FDCAN_CONFIG->CKDIV << 1);
488 }
489
490 return 0;
491 }
492
can_stm32fd_clock_enable(const struct device * dev)493 static int can_stm32fd_clock_enable(const struct device *dev)
494 {
495 int ret;
496 const struct can_mcan_config *mcan_cfg = dev->config;
497 const struct can_stm32fd_config *stm32fd_cfg = mcan_cfg->custom;
498 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
499
500 if (!device_is_ready(clk)) {
501 return -ENODEV;
502 }
503
504 if (IS_ENABLED(STM32_CANFD_DOMAIN_CLOCK_SUPPORT) && (stm32fd_cfg->pclk_len > 1)) {
505 ret = clock_control_configure(clk,
506 (clock_control_subsys_t)&stm32fd_cfg->pclken[1],
507 NULL);
508 if (ret < 0) {
509 LOG_ERR("Could not select can_stm32fd domain clock");
510 return ret;
511 }
512 }
513
514 ret = clock_control_on(clk, (clock_control_subsys_t)&stm32fd_cfg->pclken[0]);
515 if (ret < 0) {
516 return ret;
517 }
518
519 if (stm32fd_cfg->clock_divider != 0) {
520 can_mcan_enable_configuration_change(dev);
521 FDCAN_CONFIG->CKDIV = stm32fd_cfg->clock_divider >> 1;
522 }
523
524 return 0;
525 }
526
can_stm32fd_init(const struct device * dev)527 static int can_stm32fd_init(const struct device *dev)
528 {
529 const struct can_mcan_config *mcan_cfg = dev->config;
530 const struct can_stm32fd_config *stm32fd_cfg = mcan_cfg->custom;
531 uint32_t rxgfc;
532 int ret;
533
534 /* Configure dt provided device signals when available */
535 ret = pinctrl_apply_state(stm32fd_cfg->pcfg, PINCTRL_STATE_DEFAULT);
536 if (ret < 0) {
537 LOG_ERR("CAN pinctrl setup failed (%d)", ret);
538 return ret;
539 }
540
541 ret = can_stm32fd_clock_enable(dev);
542 if (ret < 0) {
543 LOG_ERR("Could not turn on CAN clock (%d)", ret);
544 return ret;
545 }
546
547 can_mcan_enable_configuration_change(dev);
548
549 /* Setup STM32 FDCAN Global Filter Configuration register */
550 ret = can_mcan_read_reg(dev, CAN_STM32FD_RXGFC, &rxgfc);
551 if (ret != 0) {
552 return ret;
553 }
554
555 rxgfc |= FIELD_PREP(CAN_STM32FD_RXGFC_LSS, CONFIG_CAN_MAX_STD_ID_FILTER) |
556 FIELD_PREP(CAN_STM32FD_RXGFC_LSE, CONFIG_CAN_MAX_EXT_ID_FILTER);
557
558 ret = can_mcan_write_reg(dev, CAN_STM32FD_RXGFC, rxgfc);
559 if (ret != 0) {
560 return ret;
561 }
562
563 /* Setup STM32 FDCAN Tx buffer configuration register */
564 ret = can_mcan_write_reg(dev, CAN_MCAN_TXBC, CAN_STM32FD_TXBC_TFQM);
565 if (ret != 0) {
566 return ret;
567 }
568
569 ret = can_mcan_init(dev);
570 if (ret != 0) {
571 return ret;
572 }
573
574 stm32fd_cfg->config_irq();
575
576 return ret;
577 }
578
579 static const struct can_driver_api can_stm32fd_driver_api = {
580 .get_capabilities = can_mcan_get_capabilities,
581 .start = can_mcan_start,
582 .stop = can_mcan_stop,
583 .set_mode = can_mcan_set_mode,
584 .set_timing = can_mcan_set_timing,
585 .send = can_mcan_send,
586 .add_rx_filter = can_mcan_add_rx_filter,
587 .remove_rx_filter = can_mcan_remove_rx_filter,
588 .get_state = can_mcan_get_state,
589 #ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY
590 .recover = can_mcan_recover,
591 #endif /* CONFIG_CAN_AUTO_BUS_OFF_RECOVERY */
592 .get_core_clock = can_stm32fd_get_core_clock,
593 .get_max_bitrate = can_mcan_get_max_bitrate,
594 .get_max_filters = can_mcan_get_max_filters,
595 .set_state_change_callback = can_mcan_set_state_change_callback,
596 .timing_min = CAN_MCAN_TIMING_MIN_INITIALIZER,
597 .timing_max = CAN_MCAN_TIMING_MAX_INITIALIZER,
598 #ifdef CONFIG_CAN_FD_MODE
599 .set_timing_data = can_mcan_set_timing_data,
600 .timing_data_min = CAN_MCAN_TIMING_DATA_MIN_INITIALIZER,
601 .timing_data_max = CAN_MCAN_TIMING_DATA_MAX_INITIALIZER,
602 #endif /* CONFIG_CAN_FD_MODE */
603 };
604
605 static const struct can_mcan_ops can_stm32fd_ops = {
606 .read_reg = can_stm32fd_read_reg,
607 .write_reg = can_stm32fd_write_reg,
608 .read_mram = can_stm32fd_read_mram,
609 .write_mram = can_stm32fd_write_mram,
610 .clear_mram = can_stm32fd_clear_mram,
611 };
612
613 #define CAN_STM32FD_BUILD_ASSERT_MRAM_CFG(inst) \
614 BUILD_ASSERT(CAN_MCAN_DT_INST_MRAM_STD_FILTER_ELEMENTS(inst) == 28, \
615 "Standard filter elements must be 28"); \
616 BUILD_ASSERT(CAN_MCAN_DT_INST_MRAM_EXT_FILTER_ELEMENTS(inst) == 8, \
617 "Extended filter elements must be 8"); \
618 BUILD_ASSERT(CAN_MCAN_DT_INST_MRAM_RX_FIFO0_ELEMENTS(inst) == 3, \
619 "Rx FIFO 0 elements must be 3"); \
620 BUILD_ASSERT(CAN_MCAN_DT_INST_MRAM_RX_FIFO1_ELEMENTS(inst) == 3, \
621 "Rx FIFO 1 elements must be 3"); \
622 BUILD_ASSERT(CAN_MCAN_DT_INST_MRAM_RX_BUFFER_ELEMENTS(inst) == 0, \
623 "Rx Buffer elements must be 0"); \
624 BUILD_ASSERT(CAN_MCAN_DT_INST_MRAM_TX_EVENT_FIFO_ELEMENTS(inst) == 3, \
625 "Tx Event FIFO elements must be 3"); \
626 BUILD_ASSERT(CAN_MCAN_DT_INST_MRAM_TX_BUFFER_ELEMENTS(inst) == 3, \
627 "Tx Buffer elements must be 0");
628
629 #define CAN_STM32FD_IRQ_CFG_FUNCTION(inst) \
630 static void config_can_##inst##_irq(void) \
631 { \
632 LOG_DBG("Enable CAN" #inst " IRQ"); \
633 IRQ_CONNECT(DT_INST_IRQ_BY_NAME(inst, line_0, irq), \
634 DT_INST_IRQ_BY_NAME(inst, line_0, priority), \
635 can_mcan_line_0_isr, DEVICE_DT_INST_GET(inst), 0); \
636 irq_enable(DT_INST_IRQ_BY_NAME(inst, line_0, irq)); \
637 IRQ_CONNECT(DT_INST_IRQ_BY_NAME(inst, line_1, irq), \
638 DT_INST_IRQ_BY_NAME(inst, line_1, priority), \
639 can_mcan_line_1_isr, DEVICE_DT_INST_GET(inst), 0); \
640 irq_enable(DT_INST_IRQ_BY_NAME(inst, line_1, irq)); \
641 }
642
643 #define CAN_STM32FD_CFG_INST(inst) \
644 BUILD_ASSERT(CAN_MCAN_DT_INST_MRAM_ELEMENTS_SIZE(inst) <= \
645 CAN_MCAN_DT_INST_MRAM_SIZE(inst), \
646 "Insufficient Message RAM size to hold elements"); \
647 \
648 PINCTRL_DT_INST_DEFINE(inst); \
649 CAN_MCAN_CALLBACKS_DEFINE(can_stm32fd_cbs_##inst, \
650 CAN_MCAN_DT_INST_MRAM_TX_BUFFER_ELEMENTS(inst), \
651 CONFIG_CAN_MAX_STD_ID_FILTER, \
652 CONFIG_CAN_MAX_EXT_ID_FILTER); \
653 \
654 static const struct stm32_pclken can_stm32fd_pclken_##inst[] = \
655 STM32_DT_INST_CLOCKS(inst); \
656 \
657 static const struct can_stm32fd_config can_stm32fd_cfg_##inst = { \
658 .base = CAN_MCAN_DT_INST_MCAN_ADDR(inst), \
659 .mram = CAN_MCAN_DT_INST_MRAM_ADDR(inst), \
660 .pclken = can_stm32fd_pclken_##inst, \
661 .pclk_len = DT_INST_NUM_CLOCKS(inst), \
662 .config_irq = config_can_##inst##_irq, \
663 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
664 .clock_divider = DT_INST_PROP_OR(inst, clk_divider, 0) \
665 }; \
666 \
667 static const struct can_mcan_config can_mcan_cfg_##inst = \
668 CAN_MCAN_DT_CONFIG_INST_GET(inst, &can_stm32fd_cfg_##inst, \
669 &can_stm32fd_ops, \
670 &can_stm32fd_cbs_##inst);
671
672 #define CAN_STM32FD_DATA_INST(inst) \
673 static struct can_mcan_data can_mcan_data_##inst = \
674 CAN_MCAN_DATA_INITIALIZER(NULL);
675
676 #define CAN_STM32FD_DEVICE_INST(inst) \
677 CAN_DEVICE_DT_INST_DEFINE(inst, can_stm32fd_init, NULL, \
678 &can_mcan_data_##inst, &can_mcan_cfg_##inst, \
679 POST_KERNEL, CONFIG_CAN_INIT_PRIORITY, \
680 &can_stm32fd_driver_api);
681
682 #define CAN_STM32FD_INST(inst) \
683 CAN_STM32FD_BUILD_ASSERT_MRAM_CFG(inst) \
684 CAN_STM32FD_IRQ_CFG_FUNCTION(inst) \
685 CAN_STM32FD_CFG_INST(inst) \
686 CAN_STM32FD_DATA_INST(inst) \
687 CAN_STM32FD_DEVICE_INST(inst)
688
689 DT_INST_FOREACH_STATUS_OKAY(CAN_STM32FD_INST)
690
