Home
last modified time | relevance | path

Searched refs:CACHED_SRAM_END (Results 1 – 1 of 1) sorted by relevance

/Zephyr-Core-3.5.0/drivers/cache/
Dcache_aspeed.c28 #define CACHED_SRAM_END (CACHED_SRAM_ADDR + CACHED_SRAM_SIZE - 1) macro
61 end_bit = MIN(max_bit, CACHED_SRAM_END >> CACHE_AREA_SIZE_LOG2); in aspeed_cache_init()
168 ((uint32_t)addr > CACHED_SRAM_END)) { in cache_data_invd_range()
229 ((uint32_t)addr > CACHED_SRAM_END)) { in cache_instr_invd_range()