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Searched refs:CACHED_SRAM_ADDR (Results 1 – 1 of 1) sorted by relevance

/Zephyr-Core-3.5.0/drivers/cache/
Dcache_aspeed.c26 #define CACHED_SRAM_ADDR CONFIG_SRAM_BASE_ADDRESS macro
28 #define CACHED_SRAM_END (CACHED_SRAM_ADDR + CACHED_SRAM_SIZE - 1)
60 start_bit = MIN(max_bit, CACHED_SRAM_ADDR >> CACHE_AREA_SIZE_LOG2); in aspeed_cache_init()
167 if (((uint32_t)addr < CACHED_SRAM_ADDR) || in cache_data_invd_range()
228 if (((uint32_t)addr < CACHED_SRAM_ADDR) || in cache_instr_invd_range()