1 /*
2 * Copyright (c) 2022 ITE Corporation. All Rights Reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT ite_it8xxx2_peci
8
9 #include <zephyr/drivers/gpio.h>
10 #include <zephyr/drivers/pinctrl.h>
11 #include <zephyr/drivers/peci.h>
12 #include <zephyr/kernel.h>
13 #include <errno.h>
14 #include <zephyr/device.h>
15 #include <zephyr/drivers/peci.h>
16 #include <soc.h>
17 #include <soc_dt.h>
18 #include <zephyr/logging/log.h>
19 #include <zephyr/sys/util.h>
20 #include <zephyr/irq.h>
21
22 LOG_MODULE_REGISTER(peci_ite_it8xxx2, CONFIG_PECI_LOG_LEVEL);
23
24 BUILD_ASSERT(IS_ENABLED(CONFIG_PECI_INTERRUPT_DRIVEN),
25 "Please enable the option CONFIG_PECI_INTERRUPT_DRIVEN");
26
27 /*
28 * This driver is single-instance. If the devicetree contains multiple
29 * instances, this will fail and the driver needs to be revisited.
30 */
31 BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) <= 1,
32 "Unsupported PECI Instance");
33
34 /* The following constants describes the bitrate of it8xxx2 PECI,
35 * for the frequency are 2000KHz, 1000KHz, and 1600KHz. (Unit: KHz)
36 */
37 #define PECI_IT8XXX2_BITRATE_2MHZ 2000
38 #define PECI_IT8XXX2_BITRATE_1MHZ 1000
39 #define PECI_IT8XXX2_BITRATE_1P6MHZ 1600
40
41 /* The following masks are designed for the PECI bitrate settings,
42 * for the bits[7:3] are not related to this features.
43 */
44 #define PECI_IT8XXX2_BITRATE_BITS_MASK 0x07
45 #define PECI_IT8XXX2_BITRATE_2MHZ_BITS 0x00
46 #define PECI_IT8XXX2_BITRATE_1MHZ_BITS 0x01
47 #define PECI_IT8XXX2_BITRATE_1P6MHZ_BITS 0x04
48
49 /* The Transaction Timeout */
50 #define PECI_TIMEOUT_MS 30
51
52 /* PECI interface 0 */
53 #define PECI0 0
54
55 /* HOSTAR (F02C00h) */
56 #define HOBY BIT(0)
57 #define FINISH BIT(1)
58 #define RD_FCS_ERR BIT(2)
59 #define WR_FCS_ERR BIT(3)
60 #define EXTERR BIT(5)
61 #define BUS_ER BIT(6)
62 #define TEMPERR BIT(7)
63 #define HOSTAR_RST_ANYBIT \
64 (TEMPERR|BUS_ER|EXTERR|WR_FCS_ERR|RD_FCS_ERR|FINISH)
65
66 /* HOCTLR (F02C01h) */
67 #define START BIT(0)
68 #define AWFCS_EN BIT(1)
69 #define CONTROL BIT(2)
70 #define PECIHEN BIT(3)
71 #define FCSERR_ABT BIT(4)
72 #define FIFOCLR BIT(5)
73
74 /*
75 * TODO: The Voltage Configuration
76 * Related DTSi and registers settings should be fulfilled
77 * in the future.
78 */
79 /* PADCTLR (F02C0Eh) */
80 #define PECI_DVIE 0x04
81
82 enum peci_vtts {
83 HOVTTS0P85V = 0x00,
84 HOVTTS0P90V = 0x01,
85 HOVTTS0P95V = 0x02,
86 HOVTTS1P00V = 0x03,
87 HOVTTS1P05V = 0x08,
88 HOVTTS1P10V = 0x09,
89 HOVTTS1P15V = 0x0A,
90 HOVTTS1P20V = 0x0B,
91 HOVTTS1P25V = 0x10,
92 };
93
94 struct peci_it8xxx2_config {
95 uintptr_t base_addr;
96 uint8_t irq_no;
97 const struct pinctrl_dev_config *pcfg;
98 };
99
100 struct peci_it8xxx2_data {
101 struct peci_msg *msgs;
102 struct k_sem device_sync_sem;
103 uint32_t bitrate;
104 };
105
106 PINCTRL_DT_INST_DEFINE(0);
107
108 static const struct peci_it8xxx2_config peci_it8xxx2_config0 = {
109 .base_addr = DT_INST_REG_ADDR(0),
110 .irq_no = DT_INST_IRQN(0),
111 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
112 };
113
114 static struct peci_it8xxx2_data peci_it8xxx2_data0;
115
116 /* ITE IT8XXX2 PECI Functions */
117
peci_it8xxx2_init_vtts(struct peci_it8xxx2_regs * reg_base,enum peci_vtts vol_opt)118 static void peci_it8xxx2_init_vtts(struct peci_it8xxx2_regs *reg_base,
119 enum peci_vtts vol_opt)
120 {
121 reg_base->PADCTLR = (reg_base->PADCTLR & PECI_DVIE) | vol_opt;
122 }
123
peci_it8xxx2_rst_status(struct peci_it8xxx2_regs * reg_base)124 static void peci_it8xxx2_rst_status(struct peci_it8xxx2_regs *reg_base)
125 {
126 reg_base->HOSTAR = HOSTAR_RST_ANYBIT;
127 }
128
peci_it8xxx2_check_host_busy(struct peci_it8xxx2_regs * reg_base)129 static int peci_it8xxx2_check_host_busy(struct peci_it8xxx2_regs *reg_base)
130 {
131 return (reg_base->HOSTAR & HOBY) ? (-EBUSY) : 0;
132 }
133
peci_it8xxx2_check_host_finish(const struct device * dev)134 static int peci_it8xxx2_check_host_finish(const struct device *dev)
135 {
136 struct peci_it8xxx2_data *data = dev->data;
137 const struct peci_it8xxx2_config *config = dev->config;
138 struct peci_it8xxx2_regs *const peci_regs =
139 (struct peci_it8xxx2_regs *)config->base_addr;
140
141 int ret = k_sem_take(&data->device_sync_sem, K_MSEC(PECI_TIMEOUT_MS));
142
143 if (ret == -EAGAIN) {
144 LOG_ERR("%s: Timeout", __func__);
145 return -ETIMEDOUT;
146 }
147
148 if (peci_regs->HOSTAR != FINISH) {
149 LOG_ERR("[PECI] Error: HOSTAR=0x%02X\r\n", peci_regs->HOSTAR);
150 return -EIO;
151 }
152
153 return 0;
154 }
155
peci_it8xxx2_configure(const struct device * dev,uint32_t bitrate)156 static int peci_it8xxx2_configure(const struct device *dev, uint32_t bitrate)
157 {
158 struct peci_it8xxx2_data *data = dev->data;
159 const struct peci_it8xxx2_config *config = dev->config;
160 struct peci_it8xxx2_regs *const peci_regs =
161 (struct peci_it8xxx2_regs *)config->base_addr;
162
163 uint8_t hoctl2r_to_write;
164
165 data->bitrate = bitrate;
166
167 hoctl2r_to_write =
168 (peci_regs->HOCTL2R) & (~(PECI_IT8XXX2_BITRATE_BITS_MASK));
169
170 switch (bitrate) {
171 case PECI_IT8XXX2_BITRATE_2MHZ:
172 break;
173
174 case PECI_IT8XXX2_BITRATE_1MHZ:
175 hoctl2r_to_write |= PECI_IT8XXX2_BITRATE_1MHZ_BITS;
176 break;
177
178 case PECI_IT8XXX2_BITRATE_1P6MHZ:
179 hoctl2r_to_write |= PECI_IT8XXX2_BITRATE_1P6MHZ_BITS;
180 break;
181
182 default:
183 LOG_ERR("[PECI] Error: Specified Bitrate Not Supported\r\n");
184 hoctl2r_to_write |= PECI_IT8XXX2_BITRATE_1MHZ_BITS;
185 data->bitrate = PECI_IT8XXX2_BITRATE_1MHZ;
186 peci_regs->HOCTL2R = hoctl2r_to_write;
187 return -ENOTSUP;
188 }
189
190 peci_regs->HOCTL2R = hoctl2r_to_write;
191
192 return 0;
193 }
194
peci_it8xxx2_enable(const struct device * dev)195 static int peci_it8xxx2_enable(const struct device *dev)
196 {
197 const struct peci_it8xxx2_config *config = dev->config;
198 struct peci_it8xxx2_regs *const peci_regs =
199 (struct peci_it8xxx2_regs *)config->base_addr;
200
201 peci_regs->HOCTLR |= (FIFOCLR|FCSERR_ABT|PECIHEN|CONTROL);
202
203 return 0;
204 }
205
peci_it8xxx2_disable(const struct device * dev)206 static int peci_it8xxx2_disable(const struct device *dev)
207 {
208 const struct peci_it8xxx2_config *config = dev->config;
209 struct peci_it8xxx2_regs *const peci_regs =
210 (struct peci_it8xxx2_regs *)config->base_addr;
211
212 peci_regs->HOCTLR &= ~(PECIHEN);
213 return 0;
214 }
215
peci_it8xxx2_rst_module(const struct device * dev)216 static void peci_it8xxx2_rst_module(const struct device *dev)
217 {
218 const struct peci_it8xxx2_config *config = dev->config;
219 struct peci_it8xxx2_regs *const peci_regs =
220 (struct peci_it8xxx2_regs *)config->base_addr;
221 struct gctrl_it8xxx2_regs *const gctrl_regs = GCTRL_IT8XXX2_REGS_BASE;
222
223 LOG_ERR("[PECI] Module Reset for Status Error.\r\n");
224 /* Reset IT8XXX2 PECI Module Thoroughly */
225 gctrl_regs->GCTRL_RSTC4 |= IT8XXX2_GCTRL_RPECI;
226 /*
227 * Due to the fact that we've checked if the peci_enable()
228 * called before calling the peci_transfer(), so the peci
229 * were definitely enabled before the error occurred.
230 * Here is the recovery mechanism for recovering the PECI
231 * bus when the errors occur.
232 */
233 peci_regs->PADCTLR |= PECI_DVIE;
234 peci_it8xxx2_init_vtts(peci_regs, HOVTTS0P95V);
235 peci_it8xxx2_configure(dev, PECI_IT8XXX2_BITRATE_1MHZ);
236 peci_it8xxx2_enable(dev);
237 LOG_ERR("[PECI] Reinitialization Finished.\r\n");
238 }
239
peci_it8xxx2_transfer(const struct device * dev,struct peci_msg * msg)240 static int peci_it8xxx2_transfer(const struct device *dev, struct peci_msg *msg)
241 {
242 const struct peci_it8xxx2_config *config = dev->config;
243 struct peci_it8xxx2_regs *const peci_regs =
244 (struct peci_it8xxx2_regs *)config->base_addr;
245
246 struct peci_buf *peci_rx_buf = &msg->rx_buffer;
247 struct peci_buf *peci_tx_buf = &msg->tx_buffer;
248
249 int cnt, ret_code;
250
251 ret_code = 0;
252
253 if (!(peci_regs->HOCTLR & PECIHEN)) {
254 LOG_ERR("[PECI] Please call the peci_enable() first.\r\n");
255 return -ECONNREFUSED;
256 }
257
258 if (peci_it8xxx2_check_host_busy(peci_regs) != 0) {
259 return -EBUSY;
260 }
261
262 peci_regs->HOTRADDR = msg->addr;
263 peci_regs->HOWRLR = peci_tx_buf->len;
264 peci_regs->HORDLR = peci_rx_buf->len;
265 peci_regs->HOCMDR = msg->cmd_code;
266
267 if (msg->cmd_code != PECI_CMD_PING) {
268 for (cnt = 0; cnt < (peci_tx_buf->len - 1); cnt++) {
269 peci_regs->HOWRDR = peci_tx_buf->buf[cnt];
270 }
271 }
272
273 /* Host Available */
274 irq_enable(config->irq_no);
275 peci_regs->HOCTLR |= START;
276 ret_code = peci_it8xxx2_check_host_finish(dev);
277
278 if (!ret_code) {
279 /* Host Transactions Finished, Fetch Data from the regs */
280 if (peci_rx_buf->len) {
281 for (cnt = 0; cnt < (peci_rx_buf->len); cnt++) {
282 peci_rx_buf->buf[cnt] = peci_regs->HORDDR;
283 }
284 }
285 peci_it8xxx2_rst_status(peci_regs);
286
287 } else {
288 /* Host Transactions Failure */
289 peci_it8xxx2_rst_module(dev);
290 }
291
292 return (ret_code);
293 }
294
peci_it8xxx2_isr(const struct device * dev)295 static void peci_it8xxx2_isr(const struct device *dev)
296 {
297 struct peci_it8xxx2_data *data = dev->data;
298 const struct peci_it8xxx2_config *config = dev->config;
299
300 irq_disable(config->irq_no);
301 k_sem_give(&data->device_sync_sem);
302 }
303
304 static const struct peci_driver_api peci_it8xxx2_driver_api = {
305 .config = peci_it8xxx2_configure,
306 .enable = peci_it8xxx2_enable,
307 .disable = peci_it8xxx2_disable,
308 .transfer = peci_it8xxx2_transfer,
309 };
310
peci_it8xxx2_init(const struct device * dev)311 static int peci_it8xxx2_init(const struct device *dev)
312 {
313 struct peci_it8xxx2_data *data = dev->data;
314 const struct peci_it8xxx2_config *config = dev->config;
315 struct peci_it8xxx2_regs *const peci_regs =
316 (struct peci_it8xxx2_regs *)config->base_addr;
317 int status;
318
319 /* Initialize Semaphore */
320 k_sem_init(&data->device_sync_sem, 0, 1);
321
322 /* Configure the GPF6 to Alternative Function 3: PECI */
323 status = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
324 if (status < 0) {
325 LOG_ERR("Failed to configure PECI pins");
326 return status;
327 }
328
329 peci_regs->PADCTLR |= PECI_DVIE;
330 peci_it8xxx2_init_vtts(peci_regs, HOVTTS0P95V);
331 peci_it8xxx2_configure(dev, PECI_IT8XXX2_BITRATE_1MHZ);
332
333 /* Interrupt Assignment */
334 IRQ_CONNECT(DT_INST_IRQN(0),
335 0,
336 peci_it8xxx2_isr,
337 DEVICE_DT_INST_GET(0),
338 0);
339
340 return 0;
341 }
342
343 DEVICE_DT_INST_DEFINE(0,
344 &peci_it8xxx2_init,
345 NULL,
346 &peci_it8xxx2_data0,
347 &peci_it8xxx2_config0,
348 POST_KERNEL, CONFIG_PECI_INIT_PRIORITY,
349 &peci_it8xxx2_driver_api);
350
