1 /*
2 * Copyright (c) 2022 Meta Platforms, Inc. and its affiliates.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <errno.h>
8
9 #include <zephyr/drivers/i3c.h>
10 #include <zephyr/init.h>
11 #include <zephyr/kernel.h>
12 #include <zephyr/logging/log.h>
13 #include <zephyr/sys/byteorder.h>
14 #include <zephyr/sys/sys_io.h>
15 #include <zephyr/sys/util.h>
16
17 #define DEV_ID 0x0
18 #define DEV_ID_I3C_MASTER 0x5034
19
20 #define CONF_STATUS0 0x4
21 #define CONF_STATUS0_CMDR_DEPTH(x) (4 << (((x)&GENMASK(31, 29)) >> 29))
22 #define CONF_STATUS0_ECC_CHK BIT(28)
23 #define CONF_STATUS0_INTEG_CHK BIT(27)
24 #define CONF_STATUS0_CSR_DAP_CHK BIT(26)
25 #define CONF_STATUS0_TRANS_TOUT_CHK BIT(25)
26 #define CONF_STATUS0_PROT_FAULTS_CHK BIT(24)
27 #define CONF_STATUS0_GPO_NUM(x) (((x)&GENMASK(23, 16)) >> 16)
28 #define CONF_STATUS0_GPI_NUM(x) (((x)&GENMASK(15, 8)) >> 8)
29 #define CONF_STATUS0_IBIR_DEPTH(x) (4 << (((x)&GENMASK(7, 6)) >> 7))
30 #define CONF_STATUS0_SUPPORTS_DDR BIT(5)
31 #define CONF_STATUS0_SEC_MASTER BIT(4)
32 #define CONF_STATUS0_DEVS_NUM(x) ((x)&GENMASK(3, 0))
33
34 #define CONF_STATUS1 0x8
35 #define CONF_STATUS1_IBI_HW_RES(x) ((((x)&GENMASK(31, 28)) >> 28) + 1)
36 #define CONF_STATUS1_CMD_DEPTH(x) (4 << (((x)&GENMASK(27, 26)) >> 26))
37 #define CONF_STATUS1_SLVDDR_RX_DEPTH(x) (8 << (((x)&GENMASK(25, 21)) >> 21))
38 #define CONF_STATUS1_SLVDDR_TX_DEPTH(x) (8 << (((x)&GENMASK(20, 16)) >> 16))
39 #define CONF_STATUS1_IBI_DEPTH(x) (2 << (((x)&GENMASK(12, 10)) >> 10))
40 #define CONF_STATUS1_RX_DEPTH(x) (8 << (((x)&GENMASK(9, 5)) >> 5))
41 #define CONF_STATUS1_TX_DEPTH(x) (8 << ((x)&GENMASK(4, 0)))
42
43 #define REV_ID 0xc
44 #define REV_ID_VID(id) (((id)&GENMASK(31, 20)) >> 20)
45 #define REV_ID_PID(id) (((id)&GENMASK(19, 8)) >> 8)
46 #define REV_ID_REV(id) ((id)&GENMASK(7, 0))
47 #define REV_ID_VERSION(m, n) ((m << 5) | (n))
48 #define REV_ID_REV_MAJOR(id) (((id)&GENMASK(7, 5)) >> 5)
49 #define REV_ID_REV_MINOR(id) ((id)&GENMASK(4, 0))
50
51 #define CTRL 0x10
52 #define CTRL_DEV_EN BIT(31)
53 #define CTRL_HALT_EN BIT(30)
54 #define CTRL_MCS BIT(29)
55 #define CTRL_MCS_EN BIT(28)
56 #define CTRL_I3C_11_SUPP BIT(26)
57 #define CTRL_THD_DELAY(x) (((x) << 24) & GENMASK(25, 24))
58 #define CTRL_HJ_DISEC BIT(8)
59 #define CTRL_MST_ACK BIT(7)
60 #define CTRL_HJ_ACK BIT(6)
61 #define CTRL_HJ_INIT BIT(5)
62 #define CTRL_MST_INIT BIT(4)
63 #define CTRL_AHDR_OPT BIT(3)
64 #define CTRL_PURE_BUS_MODE 0
65 #define CTRL_MIXED_FAST_BUS_MODE 2
66 #define CTRL_MIXED_SLOW_BUS_MODE 3
67 #define CTRL_BUS_MODE_MASK GENMASK(1, 0)
68 #define THD_DELAY_MAX 3
69
70 #define PRESCL_CTRL0 0x14
71 #define PRESCL_CTRL0_I2C(x) ((x) << 16)
72 #define PRESCL_CTRL0_I3C(x) (x)
73 #define PRESCL_CTRL0_MAX GENMASK(9, 0)
74
75 #define PRESCL_CTRL1 0x18
76 #define PRESCL_CTRL1_PP_LOW_MASK GENMASK(15, 8)
77 #define PRESCL_CTRL1_PP_LOW(x) ((x) << 8)
78 #define PRESCL_CTRL1_OD_LOW_MASK GENMASK(7, 0)
79 #define PRESCL_CTRL1_OD_LOW(x) (x)
80
81 #define MST_IER 0x20
82 #define MST_IDR 0x24
83 #define MST_IMR 0x28
84 #define MST_ICR 0x2c
85 #define MST_ISR 0x30
86 #define MST_INT_HALTED BIT(18)
87 #define MST_INT_MR_DONE BIT(17)
88 #define MST_INT_IMM_COMP BIT(16)
89 #define MST_INT_TX_THR BIT(15)
90 #define MST_INT_TX_OVF BIT(14)
91 #define MST_INT_IBID_THR BIT(12)
92 #define MST_INT_IBID_UNF BIT(11)
93 #define MST_INT_IBIR_THR BIT(10)
94 #define MST_INT_IBIR_UNF BIT(9)
95 #define MST_INT_IBIR_OVF BIT(8)
96 #define MST_INT_RX_THR BIT(7)
97 #define MST_INT_RX_UNF BIT(6)
98 #define MST_INT_CMDD_EMP BIT(5)
99 #define MST_INT_CMDD_THR BIT(4)
100 #define MST_INT_CMDD_OVF BIT(3)
101 #define MST_INT_CMDR_THR BIT(2)
102 #define MST_INT_CMDR_UNF BIT(1)
103 #define MST_INT_CMDR_OVF BIT(0)
104 #define MST_INT_MASK GENMASK(18, 0)
105
106 #define MST_STATUS0 0x34
107 #define MST_STATUS0_IDLE BIT(18)
108 #define MST_STATUS0_HALTED BIT(17)
109 #define MST_STATUS0_MASTER_MODE BIT(16)
110 #define MST_STATUS0_TX_FULL BIT(13)
111 #define MST_STATUS0_IBID_FULL BIT(12)
112 #define MST_STATUS0_IBIR_FULL BIT(11)
113 #define MST_STATUS0_RX_FULL BIT(10)
114 #define MST_STATUS0_CMDD_FULL BIT(9)
115 #define MST_STATUS0_CMDR_FULL BIT(8)
116 #define MST_STATUS0_TX_EMP BIT(5)
117 #define MST_STATUS0_IBID_EMP BIT(4)
118 #define MST_STATUS0_IBIR_EMP BIT(3)
119 #define MST_STATUS0_RX_EMP BIT(2)
120 #define MST_STATUS0_CMDD_EMP BIT(1)
121 #define MST_STATUS0_CMDR_EMP BIT(0)
122
123 #define CMDR 0x38
124 #define CMDR_NO_ERROR 0
125 #define CMDR_DDR_PREAMBLE_ERROR 1
126 #define CMDR_DDR_PARITY_ERROR 2
127 #define CMDR_DDR_RX_FIFO_OVF 3
128 #define CMDR_DDR_TX_FIFO_UNF 4
129 #define CMDR_M0_ERROR 5
130 #define CMDR_M1_ERROR 6
131 #define CMDR_M2_ERROR 7
132 #define CMDR_MST_ABORT 8
133 #define CMDR_NACK_RESP 9
134 #define CMDR_INVALID_DA 10
135 #define CMDR_DDR_DROPPED 11
136 #define CMDR_ERROR(x) (((x)&GENMASK(27, 24)) >> 24)
137 #define CMDR_XFER_BYTES(x) (((x)&GENMASK(19, 8)) >> 8)
138 #define CMDR_CMDID_HJACK_DISEC 0xfe
139 #define CMDR_CMDID_HJACK_ENTDAA 0xff
140 #define CMDR_CMDID(x) ((x)&GENMASK(7, 0))
141
142 #define IBIR 0x3c
143 #define IBIR_ACKED BIT(12)
144 #define IBIR_SLVID(x) (((x)&GENMASK(11, 8)) >> 8)
145 #define IBIR_SLVID_INV 0xF
146 #define IBIR_ERROR BIT(7)
147 #define IBIR_XFER_BYTES(x) (((x)&GENMASK(6, 2)) >> 2)
148 #define IBIR_TYPE_IBI 0
149 #define IBIR_TYPE_HJ 1
150 #define IBIR_TYPE_MR 2
151 #define IBIR_TYPE(x) ((x)&GENMASK(1, 0))
152
153 #define SLV_IER 0x40
154 #define SLV_IDR 0x44
155 #define SLV_IMR 0x48
156 #define SLV_ICR 0x4c
157 #define SLV_ISR 0x50
158 #define SLV_INT_DEFSLVS BIT(21)
159 #define SLV_INT_TM BIT(20)
160 #define SLV_INT_ERROR BIT(19)
161 #define SLV_INT_EVENT_UP BIT(18)
162 #define SLV_INT_HJ_DONE BIT(17)
163 #define SLV_INT_MR_DONE BIT(16)
164 #define SLV_INT_DA_UPD BIT(15)
165 #define SLV_INT_SDR_FAIL BIT(14)
166 #define SLV_INT_DDR_FAIL BIT(13)
167 #define SLV_INT_M_RD_ABORT BIT(12)
168 #define SLV_INT_DDR_RX_THR BIT(11)
169 #define SLV_INT_DDR_TX_THR BIT(10)
170 #define SLV_INT_SDR_RX_THR BIT(9)
171 #define SLV_INT_SDR_TX_THR BIT(8)
172 #define SLV_INT_DDR_RX_UNF BIT(7)
173 #define SLV_INT_DDR_TX_OVF BIT(6)
174 #define SLV_INT_SDR_RX_UNF BIT(5)
175 #define SLV_INT_SDR_TX_OVF BIT(4)
176 #define SLV_INT_DDR_RD_COMP BIT(3)
177 #define SLV_INT_DDR_WR_COMP BIT(2)
178 #define SLV_INT_SDR_RD_COMP BIT(1)
179 #define SLV_INT_SDR_WR_COMP BIT(0)
180 #define SLV_INT_MASK GENMASK(20, 0)
181
182 #define SLV_STATUS0 0x54
183 #define SLV_STATUS0_REG_ADDR(s) (((s)&GENMASK(23, 16)) >> 16)
184 #define SLV_STATUS0_XFRD_BYTES(s) ((s)&GENMASK(15, 0))
185
186 #define SLV_STATUS1 0x58
187 #define SLV_STATUS1_AS(s) (((s)&GENMASK(21, 20)) >> 20)
188 #define SLV_STATUS1_VEN_TM BIT(19)
189 #define SLV_STATUS1_HJ_DIS BIT(18)
190 #define SLV_STATUS1_MR_DIS BIT(17)
191 #define SLV_STATUS1_PROT_ERR BIT(16)
192 #define SLV_STATUS1_DA(s) (((s)&GENMASK(15, 9)) >> 9)
193 #define SLV_STATUS1_HAS_DA BIT(8)
194 #define SLV_STATUS1_DDR_RX_FULL BIT(7)
195 #define SLV_STATUS1_DDR_TX_FULL BIT(6)
196 #define SLV_STATUS1_DDR_RX_EMPTY BIT(5)
197 #define SLV_STATUS1_DDR_TX_EMPTY BIT(4)
198 #define SLV_STATUS1_SDR_RX_FULL BIT(3)
199 #define SLV_STATUS1_SDR_TX_FULL BIT(2)
200 #define SLV_STATUS1_SDR_RX_EMPTY BIT(1)
201 #define SLV_STATUS1_SDR_TX_EMPTY BIT(0)
202
203 #define CMD0_FIFO 0x60
204 #define CMD0_FIFO_IS_DDR BIT(31)
205 #define CMD0_FIFO_IS_CCC BIT(30)
206 #define CMD0_FIFO_BCH BIT(29)
207 #define XMIT_BURST_STATIC_SUBADDR 0
208 #define XMIT_SINGLE_INC_SUBADDR 1
209 #define XMIT_SINGLE_STATIC_SUBADDR 2
210 #define XMIT_BURST_WITHOUT_SUBADDR 3
211 #define CMD0_FIFO_PRIV_XMIT_MODE(m) ((m) << 27)
212 #define CMD0_FIFO_SBCA BIT(26)
213 #define CMD0_FIFO_RSBC BIT(25)
214 #define CMD0_FIFO_IS_10B BIT(24)
215 #define CMD0_FIFO_PL_LEN(l) ((l) << 12)
216 #define CMD0_FIFO_PL_LEN_MAX 4095
217 #define CMD0_FIFO_DEV_ADDR(a) ((a) << 1)
218 #define CMD0_FIFO_RNW BIT(0)
219
220 #define CMD1_FIFO 0x64
221 #define CMD1_FIFO_CMDID(id) ((id) << 24)
222 #define CMD1_FIFO_CSRADDR(a) (a)
223 #define CMD1_FIFO_CCC(id) (id)
224
225 #define TX_FIFO 0x68
226
227 #define IMD_CMD0 0x70
228 #define IMD_CMD0_PL_LEN(l) ((l) << 12)
229 #define IMD_CMD0_DEV_ADDR(a) ((a) << 1)
230 #define IMD_CMD0_RNW BIT(0)
231
232 #define IMD_CMD1 0x74
233 #define IMD_CMD1_CCC(id) (id)
234
235 #define IMD_DATA 0x78
236 #define RX_FIFO 0x80
237 #define IBI_DATA_FIFO 0x84
238 #define SLV_DDR_TX_FIFO 0x88
239 #define SLV_DDR_RX_FIFO 0x8c
240
241 #define CMD_IBI_THR_CTRL 0x90
242 #define IBIR_THR(t) ((t) << 24)
243 #define CMDR_THR(t) ((t) << 16)
244 #define CMDR_THR_MASK (GENMASK(20, 16))
245 #define IBI_THR(t) ((t) << 8)
246 #define CMD_THR(t) (t)
247
248 #define TX_RX_THR_CTRL 0x94
249 #define RX_THR(t) ((t) << 16)
250 #define RX_THR_MASK (GENMASK(31, 16))
251 #define TX_THR(t) (t)
252 #define TX_THR_MASK (GENMASK(15, 0))
253
254 #define SLV_DDR_TX_RX_THR_CTRL 0x98
255 #define SLV_DDR_RX_THR(t) ((t) << 16)
256 #define SLV_DDR_TX_THR(t) (t)
257
258 #define FLUSH_CTRL 0x9c
259 #define FLUSH_IBI_RESP BIT(23)
260 #define FLUSH_CMD_RESP BIT(22)
261 #define FLUSH_SLV_DDR_RX_FIFO BIT(22)
262 #define FLUSH_SLV_DDR_TX_FIFO BIT(21)
263 #define FLUSH_IMM_FIFO BIT(20)
264 #define FLUSH_IBI_FIFO BIT(19)
265 #define FLUSH_RX_FIFO BIT(18)
266 #define FLUSH_TX_FIFO BIT(17)
267 #define FLUSH_CMD_FIFO BIT(16)
268
269 #define TTO_PRESCL_CTRL0 0xb0
270 #define TTO_PRESCL_CTRL0_PRESCL_I2C(x) ((x) << 16)
271 #define TTO_PRESCL_CTRL0_PRESCL_I3C(x) (x)
272
273 #define TTO_PRESCL_CTRL1 0xb4
274 #define TTO_PRESCL_CTRL1_DIVB(x) ((x) << 16)
275 #define TTO_PRESCL_CTRL1_DIVA(x) (x)
276 #define TTO_PRESCL_CTRL1_PP_LOW(x) ((x) << 8)
277 #define TTO_PRESCL_CTRL1_OD_LOW(x) (x)
278
279 #define DEVS_CTRL 0xb8
280 #define DEVS_CTRL_DEV_CLR_SHIFT 16
281 #define DEVS_CTRL_DEV_CLR_ALL GENMASK(31, 16)
282 #define DEVS_CTRL_DEV_CLR(dev) BIT(16 + (dev))
283 #define DEVS_CTRL_DEV_ACTIVE(dev) BIT(dev)
284 #define DEVS_CTRL_DEVS_ACTIVE_MASK GENMASK(15, 0)
285 #define MAX_DEVS 16
286
287 #define DEV_ID_RR0(d) (0xc0 + ((d)*0x10))
288 #define DEV_ID_RR0_LVR_EXT_ADDR BIT(11)
289 #define DEV_ID_RR0_HDR_CAP BIT(10)
290 #define DEV_ID_RR0_IS_I3C BIT(9)
291 #define DEV_ID_RR0_DEV_ADDR_MASK (GENMASK(6, 0) | GENMASK(15, 13))
292 #define DEV_ID_RR0_SET_DEV_ADDR(a) (((a)&GENMASK(6, 0)) | (((a)&GENMASK(9, 7)) << 6))
293 #define DEV_ID_RR0_GET_DEV_ADDR(x) ((((x) >> 1) & GENMASK(6, 0)) | (((x) >> 6) & GENMASK(9, 7)))
294
295 #define DEV_ID_RR1(d) (0xc4 + ((d)*0x10))
296 #define DEV_ID_RR1_PID_MSB(pid) (pid)
297
298 #define DEV_ID_RR2(d) (0xc8 + ((d)*0x10))
299 #define DEV_ID_RR2_PID_LSB(pid) ((pid) << 16)
300 #define DEV_ID_RR2_BCR(bcr) ((bcr) << 8)
301 #define DEV_ID_RR2_DCR(dcr) (dcr)
302 #define DEV_ID_RR2_LVR(lvr) (lvr)
303
304 #define SIR_MAP(x) (0x180 + ((x)*4))
305 #define SIR_MAP_DEV_REG(d) SIR_MAP((d) / 2)
306 #define SIR_MAP_DEV_SHIFT(d, fs) ((fs) + (((d) % 2) ? 16 : 0))
307 #define SIR_MAP_DEV_CONF_MASK(d) (GENMASK(15, 0) << (((d) % 2) ? 16 : 0))
308 #define SIR_MAP_DEV_CONF(d, c) ((c) << (((d) % 2) ? 16 : 0))
309 #define DEV_ROLE_SLAVE 0
310 #define DEV_ROLE_MASTER 1
311 #define SIR_MAP_DEV_ROLE(role) ((role) << 14)
312 #define SIR_MAP_DEV_SLOW BIT(13)
313 #define SIR_MAP_DEV_PL(l) ((l) << 8)
314 #define SIR_MAP_PL_MAX GENMASK(4, 0)
315 #define SIR_MAP_DEV_DA(a) ((a) << 1)
316 #define SIR_MAP_DEV_ACK BIT(0)
317
318 #define GPIR_WORD(x) (0x200 + ((x)*4))
319 #define GPI_REG(val, id) (((val) >> (((id) % 4) * 8)) & GENMASK(7, 0))
320
321 #define GPOR_WORD(x) (0x220 + ((x)*4))
322 #define GPO_REG(val, id) (((val) >> (((id) % 4) * 8)) & GENMASK(7, 0))
323
324 #define ASF_INT_STATUS 0x300
325 #define ASF_INT_RAW_STATUS 0x304
326 #define ASF_INT_MASK 0x308
327 #define ASF_INT_TEST 0x30c
328 #define ASF_INT_FATAL_SELECT 0x310
329 #define ASF_INTEGRITY_ERR BIT(6)
330 #define ASF_PROTOCOL_ERR BIT(5)
331 #define ASF_TRANS_TIMEOUT_ERR BIT(4)
332 #define ASF_CSR_ERR BIT(3)
333 #define ASF_DAP_ERR BIT(2)
334 #define ASF_SRAM_UNCORR_ERR BIT(1)
335 #define ASF_SRAM_CORR_ERR BIT(0)
336
337 #define ASF_SRAM_CORR_FAULT_STATUS 0x320
338 #define ASF_SRAM_UNCORR_FAULT_STATUS 0x324
339 #define ASF_SRAM_CORR_FAULT_INSTANCE(x) ((x) >> 24)
340 #define ASF_SRAM_CORR_FAULT_ADDR(x) ((x)&GENMASK(23, 0))
341
342 #define ASF_SRAM_FAULT_STATS 0x328
343 #define ASF_SRAM_FAULT_UNCORR_STATS(x) ((x) >> 16)
344 #define ASF_SRAM_FAULT_CORR_STATS(x) ((x)&GENMASK(15, 0))
345
346 #define ASF_TRANS_TOUT_CTRL 0x330
347 #define ASF_TRANS_TOUT_EN BIT(31)
348 #define ASF_TRANS_TOUT_VAL(x) (x)
349
350 #define ASF_TRANS_TOUT_FAULT_MASK 0x334
351 #define ASF_TRANS_TOUT_FAULT_STATUS 0x338
352 #define ASF_TRANS_TOUT_FAULT_APB BIT(3)
353 #define ASF_TRANS_TOUT_FAULT_SCL_LOW BIT(2)
354 #define ASF_TRANS_TOUT_FAULT_SCL_HIGH BIT(1)
355 #define ASF_TRANS_TOUT_FAULT_FSCL_HIGH BIT(0)
356
357 #define ASF_PROTO_FAULT_MASK 0x340
358 #define ASF_PROTO_FAULT_STATUS 0x344
359 #define ASF_PROTO_FAULT_SLVSDR_RD_ABORT BIT(31)
360 #define ASF_PROTO_FAULT_SLVDDR_FAIL BIT(30)
361 #define ASF_PROTO_FAULT_S(x) BIT(16 + (x))
362 #define ASF_PROTO_FAULT_MSTSDR_RD_ABORT BIT(15)
363 #define ASF_PROTO_FAULT_MSTDDR_FAIL BIT(14)
364 #define ASF_PROTO_FAULT_M(x) BIT(x)
365
366 /*******************************************************************************
367 * Local Constants Definition
368 ******************************************************************************/
369
370 /* TODO: this needs to be configurable in the dts...somehow */
371 #define I3C_CONTROLLER_ADDR 0x08
372
373 /* Maximum i3c devices that the IP can be built with */
374 #define I3C_MAX_DEVS 11
375 #define I3C_MAX_MSGS 10
376 #define I3C_SIR_DEFAULT_DA 0x7F
377 #define I3C_MAX_IDLE_CANCEL_WAIT_RETRIES 50
378 #define I3C_MAX_IDLE_WAIT_RETRIES 5000
379 #define I3C_PRESCL_REG_SCALE (4)
380 #define I2C_PRESCL_REG_SCALE (5)
381
382 /* Target T_LOW period in open-drain mode. */
383 #define I3C_BUS_TLOW_OD_MIN_NS 200
384
385 /* MIPI I3C v1.1.1 Spec defines tsco max as 12ns */
386 #define I3C_TSCO_DEFAULT_NS 10
387
388 /* Interrupt thresholds. */
389 /* command response fifo threshold */
390 #define I3C_CMDR_THR 1
391 /* command tx fifo threshold - unused */
392 #define I3C_CMDD_THR 1
393 /* in-band-interrupt data fifo threshold - unused */
394 #define I3C_IBID_THR 1
395 /* in-band-interrupt response queue threshold */
396 #define I3C_IBIR_THR 1
397 /* tx data threshold - unused */
398 #define I3C_TX_THR 1
399
400 #define LOG_MODULE_NAME I3C_CADENCE
401 LOG_MODULE_REGISTER(I3C_CADENCE, CONFIG_I3C_CADENCE_LOG_LEVEL);
402
403 /*******************************************************************************
404 * Local Types Definition
405 ******************************************************************************/
406
407 /** Describes peripheral HW configuration determined from CONFx registers. */
408 struct cdns_i3c_hw_config {
409 /* The maxiumum command queue depth. */
410 uint32_t cmd_mem_depth;
411 /* The maxiumum command response queue depth. */
412 uint32_t cmdr_mem_depth;
413 /* The maximum RX FIFO depth. */
414 uint32_t rx_mem_depth;
415 /* The maximum TX FIFO depth. */
416 uint32_t tx_mem_depth;
417 /* The maximum IBIR FIFO depth. */
418 uint32_t ibir_mem_depth;
419 };
420
421 /* Cadence I3C/I2C Device Private Data */
422 struct cdns_i3c_i2c_dev_data {
423 /* Device id within the retaining registers. This is set after bus initialization by the
424 * controller.
425 */
426 uint8_t id;
427 };
428
429 /* Single command/transfer */
430 struct cdns_i3c_cmd {
431 uint32_t cmd0;
432 uint32_t cmd1;
433 uint32_t len;
434 void *buf;
435 uint32_t error;
436 };
437
438 /* Transfer data */
439 struct cdns_i3c_xfer {
440 struct k_sem complete;
441 int ret;
442 int num_cmds;
443 struct cdns_i3c_cmd cmds[I3C_MAX_MSGS];
444 };
445
446 /* Driver config */
447 struct cdns_i3c_config {
448 struct i3c_driver_config common;
449 /** base address of the controller */
450 uintptr_t base;
451 /** input frequency to the I3C Cadence */
452 uint32_t input_frequency;
453 /** Interrupt configuration function. */
454 void (*irq_config_func)(const struct device *dev);
455 };
456
457 /* Driver instance data */
458 struct cdns_i3c_data {
459 struct i3c_driver_data common;
460 struct cdns_i3c_hw_config hw_cfg;
461 struct k_mutex bus_lock;
462 struct cdns_i3c_i2c_dev_data cdns_i3c_i2c_priv_data[I3C_MAX_DEVS];
463 struct cdns_i3c_xfer xfer;
464 struct i3c_target_config *target_config;
465 struct k_sem ibi_hj_complete;
466 uint32_t free_rr_slots;
467 uint8_t max_devs;
468 };
469
470 /*******************************************************************************
471 * Global Variables Declaration
472 ******************************************************************************/
473
474 /*******************************************************************************
475 * Local Functions Declaration
476 ******************************************************************************/
477
478 /*******************************************************************************
479 * Private Functions Code
480 ******************************************************************************/
481
482 /* Computes and sets parity */
483 /* Returns [7:1] 7-bit addr, [0] even/xor parity */
cdns_i3c_even_parity(uint8_t byte)484 static uint8_t cdns_i3c_even_parity(uint8_t byte)
485 {
486 uint8_t parity = 0;
487 uint8_t b = byte;
488
489 while (b) {
490 parity = !parity;
491 b = b & (b - 1);
492 }
493 b = (byte << 1) | !parity;
494
495 return b;
496 }
497
498 /* Check if command response fifo is empty */
cdns_i3c_cmd_rsp_fifo_empty(const struct cdns_i3c_config * config)499 static inline bool cdns_i3c_cmd_rsp_fifo_empty(const struct cdns_i3c_config *config)
500 {
501 uint32_t mst_st = sys_read32(config->base + MST_STATUS0);
502
503 return ((mst_st & MST_STATUS0_CMDR_EMP) ? true : false);
504 }
505
506 /* Check if command fifo is empty */
cdns_i3c_cmd_fifo_empty(const struct cdns_i3c_config * config)507 static inline bool cdns_i3c_cmd_fifo_empty(const struct cdns_i3c_config *config)
508 {
509 uint32_t mst_st = sys_read32(config->base + MST_STATUS0);
510
511 return ((mst_st & MST_STATUS0_CMDD_EMP) ? true : false);
512 }
513
514 /* Check if command fifo is full */
cdns_i3c_cmd_fifo_full(const struct cdns_i3c_config * config)515 static inline bool cdns_i3c_cmd_fifo_full(const struct cdns_i3c_config *config)
516 {
517 uint32_t mst_st = sys_read32(config->base + MST_STATUS0);
518
519 return ((mst_st & MST_STATUS0_CMDD_FULL) ? true : false);
520 }
521
522 /* Check if ibi response fifo is empty */
cdns_i3c_ibi_rsp_fifo_empty(const struct cdns_i3c_config * config)523 static inline bool cdns_i3c_ibi_rsp_fifo_empty(const struct cdns_i3c_config *config)
524 {
525 uint32_t mst_st = sys_read32(config->base + MST_STATUS0);
526
527 return ((mst_st & MST_STATUS0_IBIR_EMP) ? true : false);
528 }
529
530 /* Check if tx fifo is full */
cdns_i3c_tx_fifo_full(const struct cdns_i3c_config * config)531 static inline bool cdns_i3c_tx_fifo_full(const struct cdns_i3c_config *config)
532 {
533 uint32_t mst_st = sys_read32(config->base + MST_STATUS0);
534
535 return ((mst_st & MST_STATUS0_TX_FULL) ? true : false);
536 }
537
538 /* Check if rx fifo is full */
cdns_i3c_rx_fifo_full(const struct cdns_i3c_config * config)539 static inline bool cdns_i3c_rx_fifo_full(const struct cdns_i3c_config *config)
540 {
541 uint32_t mst_st = sys_read32(config->base + MST_STATUS0);
542
543 return ((mst_st & MST_STATUS0_RX_FULL) ? true : false);
544 }
545
546 /* Check if rx fifo is empty */
cdns_i3c_rx_fifo_empty(const struct cdns_i3c_config * config)547 static inline bool cdns_i3c_rx_fifo_empty(const struct cdns_i3c_config *config)
548 {
549 uint32_t mst_st = sys_read32(config->base + MST_STATUS0);
550
551 return ((mst_st & MST_STATUS0_RX_EMP) ? true : false);
552 }
553
554 /* Check if ibi fifo is empty */
cdns_i3c_ibi_fifo_empty(const struct cdns_i3c_config * config)555 static inline bool cdns_i3c_ibi_fifo_empty(const struct cdns_i3c_config *config)
556 {
557 uint32_t mst_st = sys_read32(config->base + MST_STATUS0);
558
559 return ((mst_st & MST_STATUS0_IBID_EMP) ? true : false);
560 }
561
562 /* Interrupt handling */
cdns_i3c_interrupts_disable(const struct cdns_i3c_config * config)563 static inline void cdns_i3c_interrupts_disable(const struct cdns_i3c_config *config)
564 {
565 sys_write32(MST_INT_MASK, config->base + MST_IDR);
566 }
567
cdns_i3c_interrupts_clear(const struct cdns_i3c_config * config)568 static inline void cdns_i3c_interrupts_clear(const struct cdns_i3c_config *config)
569 {
570 sys_write32(MST_INT_MASK, config->base + MST_ICR);
571 }
572
573 /* FIFO mgmt */
cdns_i3c_write_tx_fifo(const struct cdns_i3c_config * config,const void * buf,uint32_t len)574 static void cdns_i3c_write_tx_fifo(const struct cdns_i3c_config *config, const void *buf,
575 uint32_t len)
576 {
577 const uint32_t *ptr = buf;
578 uint32_t remain, val;
579
580 for (remain = len; remain >= 4; remain -= 4) {
581 val = *ptr++;
582 sys_write32(val, config->base + TX_FIFO);
583 }
584
585 if (remain > 0) {
586 val = 0;
587 memcpy(&val, ptr, remain);
588 sys_write32(val, config->base + TX_FIFO);
589 }
590 }
591
cdns_i3c_read_rx_fifo(const struct cdns_i3c_config * config,void * buf,uint32_t len)592 static int cdns_i3c_read_rx_fifo(const struct cdns_i3c_config *config, void *buf, uint32_t len)
593 {
594 uint32_t *ptr = buf;
595 uint32_t remain, val;
596
597 for (remain = len; remain >= 4; remain -= 4) {
598 if (cdns_i3c_rx_fifo_empty(config)) {
599 return -EIO;
600 }
601 val = sys_le32_to_cpu(sys_read32(config->base + RX_FIFO));
602 *ptr++ = val;
603 }
604
605 if (remain > 0) {
606 if (cdns_i3c_rx_fifo_empty(config)) {
607 return -EIO;
608 }
609 val = sys_le32_to_cpu(sys_read32(config->base + RX_FIFO));
610 memcpy(ptr, &val, remain);
611 }
612
613 return 0;
614 }
615
cdns_i3c_set_prescalers(const struct device * dev)616 static void cdns_i3c_set_prescalers(const struct device *dev)
617 {
618 struct cdns_i3c_data *data = dev->data;
619 const struct cdns_i3c_config *config = dev->config;
620 struct i3c_config_controller *ctrl_config = &data->common.ctrl_config;
621
622 /* These formulas are from section 6.2.1 of the Cadence I3C Master User Guide. */
623 uint32_t prescl_i3c = DIV_ROUND_UP(config->input_frequency,
624 (ctrl_config->scl.i3c * I3C_PRESCL_REG_SCALE)) -
625 1;
626 uint32_t prescl_i2c = DIV_ROUND_UP(config->input_frequency,
627 (ctrl_config->scl.i2c * I2C_PRESCL_REG_SCALE)) -
628 1;
629
630 /* update with actual value */
631 ctrl_config->scl.i3c = config->input_frequency / ((prescl_i3c + 1) * I3C_PRESCL_REG_SCALE);
632 ctrl_config->scl.i2c = config->input_frequency / ((prescl_i2c + 1) * I2C_PRESCL_REG_SCALE);
633
634 LOG_DBG("%s: I3C speed = %u, PRESCL_CTRL0.i3c = 0x%x", dev->name, ctrl_config->scl.i3c,
635 prescl_i3c);
636 LOG_DBG("%s: I2C speed = %u, PRESCL_CTRL0.i2c = 0x%x", dev->name, ctrl_config->scl.i2c,
637 prescl_i2c);
638
639 /* Calculate the OD_LOW value assuming a desired T_low period of 210ns. */
640 uint32_t pres_step = 1000000000 / (ctrl_config->scl.i3c * 4);
641 int32_t od_low = DIV_ROUND_UP(I3C_BUS_TLOW_OD_MIN_NS, pres_step) - 2;
642
643 if (od_low < 0) {
644 od_low = 0;
645 }
646 LOG_DBG("%s: PRESCL_CTRL1.od_low = 0x%x", dev->name, od_low);
647
648 /* disable in order to update timing */
649 uint32_t ctrl = sys_read32(config->base + CTRL);
650
651 if (ctrl & CTRL_DEV_EN) {
652 sys_write32(~CTRL_DEV_EN & ctrl, config->base + CTRL);
653 }
654
655 sys_write32(PRESCL_CTRL0_I3C(prescl_i3c) | PRESCL_CTRL0_I2C(prescl_i2c),
656 config->base + PRESCL_CTRL0);
657
658 /* Sets the open drain low time relative to the push-pull. */
659 sys_write32(PRESCL_CTRL1_OD_LOW(od_low & PRESCL_CTRL1_OD_LOW_MASK),
660 config->base + PRESCL_CTRL1);
661
662 /* reenable */
663 if (ctrl & CTRL_DEV_EN) {
664 sys_write32(CTRL_DEV_EN | ctrl, config->base + CTRL);
665 }
666 }
667
668 /**
669 * @brief Compute RR0 Value from addr
670 *
671 * @param addr Address of the target
672 *
673 * @return RR0 value
674 */
prepare_rr0_dev_address(uint16_t addr)675 static uint32_t prepare_rr0_dev_address(uint16_t addr)
676 {
677 /* RR0[7:1] = addr[6:0] | parity^[0] */
678 uint32_t ret = cdns_i3c_even_parity(addr);
679
680 if (addr & GENMASK(9, 7)) {
681 /* RR0[15:13] = addr[9:7] */
682 ret |= (addr & GENMASK(9, 7)) << 6;
683 /* RR0[11] = 10b lvr addr */
684 ret |= DEV_ID_RR0_LVR_EXT_ADDR;
685 }
686
687 return ret;
688 }
689
690 /**
691 * @brief Program Retaining Registers with device lists
692 *
693 * This will program the retaining register with the controller itself
694 *
695 * @param dev Pointer to controller device driver instance.
696 */
cdns_i3c_program_controller_retaining_reg(const struct device * dev)697 static void cdns_i3c_program_controller_retaining_reg(const struct device *dev)
698 {
699 const struct cdns_i3c_config *config = dev->config;
700 struct cdns_i3c_data *data = dev->data;
701 /* Set controller retaining register */
702 uint8_t controller_da = I3C_CONTROLLER_ADDR;
703
704 if (!i3c_addr_slots_is_free(&data->common.attached_dev.addr_slots, controller_da)) {
705 controller_da =
706 i3c_addr_slots_next_free_find(&data->common.attached_dev.addr_slots);
707 LOG_DBG("%s: 0x%02x DA selected for controller", dev->name, controller_da);
708 }
709 sys_write32(prepare_rr0_dev_address(controller_da), config->base + DEV_ID_RR0(0));
710 /* Mark the address as I3C device */
711 i3c_addr_slots_mark_i3c(&data->common.attached_dev.addr_slots, controller_da);
712 }
713
714 #ifdef CONFIG_I3C_USE_IBI
cdns_i3c_controller_ibi_enable(const struct device * dev,struct i3c_device_desc * target)715 static int cdns_i3c_controller_ibi_enable(const struct device *dev, struct i3c_device_desc *target)
716 {
717 uint32_t sir_map;
718 uint32_t sir_cfg;
719 const struct cdns_i3c_config *config = dev->config;
720 struct cdns_i3c_i2c_dev_data *cdns_i3c_device_data = target->controller_priv;
721 struct i3c_ccc_events i3c_events;
722 int ret = 0;
723
724 if (!i3c_device_is_ibi_capable(target)) {
725 ret = -EINVAL;
726 return ret;
727 }
728
729 /* TODO: check for duplicate in SIR */
730
731 sir_cfg = SIR_MAP_DEV_ROLE(I3C_BCR_DEVICE_ROLE(target->bcr)) |
732 SIR_MAP_DEV_DA(target->dynamic_addr) |
733 SIR_MAP_DEV_PL(target->data_length.max_ibi);
734 if (target->ibi_cb != NULL) {
735 sir_cfg |= SIR_MAP_DEV_ACK;
736 }
737 if (target->bcr & I3C_BCR_MAX_DATA_SPEED_LIMIT) {
738 sir_cfg |= SIR_MAP_DEV_SLOW;
739 }
740
741 LOG_DBG("%s: IBI enabling for 0x%02x (BCR 0x%02x)", dev->name, target->dynamic_addr,
742 target->bcr);
743
744 /* Tell target to enable IBI */
745 i3c_events.events = I3C_CCC_EVT_INTR;
746 ret = i3c_ccc_do_events_set(target, true, &i3c_events);
747 if (ret != 0) {
748 LOG_ERR("%s: Error sending IBI ENEC for 0x%02x (%d)", dev->name,
749 target->dynamic_addr, ret);
750 return ret;
751 }
752
753 sir_map = sys_read32(config->base + SIR_MAP_DEV_REG(cdns_i3c_device_data->id - 1));
754 sir_map &= ~SIR_MAP_DEV_CONF_MASK(cdns_i3c_device_data->id - 1);
755 sir_map |= SIR_MAP_DEV_CONF(cdns_i3c_device_data->id - 1, sir_cfg);
756
757 sys_write32(sir_map, config->base + SIR_MAP_DEV_REG(cdns_i3c_device_data->id - 1));
758
759 return ret;
760 }
761
cdns_i3c_controller_ibi_disable(const struct device * dev,struct i3c_device_desc * target)762 static int cdns_i3c_controller_ibi_disable(const struct device *dev, struct i3c_device_desc *target)
763 {
764 uint32_t sir_map;
765 const struct cdns_i3c_config *config = dev->config;
766 struct cdns_i3c_i2c_dev_data *cdns_i3c_device_data = target->controller_priv;
767 struct i3c_ccc_events i3c_events;
768 int ret = 0;
769
770 if (!i3c_device_is_ibi_capable(target)) {
771 ret = -EINVAL;
772 return ret;
773 }
774
775 /* Tell target to disable IBI */
776 i3c_events.events = I3C_CCC_EVT_INTR;
777 ret = i3c_ccc_do_events_set(target, false, &i3c_events);
778 if (ret != 0) {
779 LOG_ERR("%s: Error sending IBI DISEC for 0x%02x (%d)", dev->name,
780 target->dynamic_addr, ret);
781 return ret;
782 }
783
784 sir_map = sys_read32(config->base + SIR_MAP_DEV_REG(cdns_i3c_device_data->id - 1));
785 sir_map &= ~SIR_MAP_DEV_CONF_MASK(cdns_i3c_device_data->id - 1);
786 sir_map |=
787 SIR_MAP_DEV_CONF(cdns_i3c_device_data->id - 1, SIR_MAP_DEV_DA(I3C_BROADCAST_ADDR));
788 sys_write32(sir_map, config->base + SIR_MAP_DEV_REG(cdns_i3c_device_data->id - 1));
789
790 return ret;
791 }
792
cdns_i3c_target_ibi_raise_hj(const struct device * dev)793 static int cdns_i3c_target_ibi_raise_hj(const struct device *dev)
794 {
795 const struct cdns_i3c_config *config = dev->config;
796 struct cdns_i3c_data *data = dev->data;
797 struct i3c_config_controller *ctrl_config = &data->common.ctrl_config;
798
799 /* HJ requests should not be done by primary controllers */
800 if (!ctrl_config->is_secondary) {
801 LOG_ERR("%s: controller is primary, HJ not available", dev->name);
802 return -ENOTSUP;
803 }
804 /* Check if target already has a DA assigned to it */
805 if (sys_read32(config->base + SLV_STATUS1) & SLV_STATUS1_HAS_DA) {
806 LOG_ERR("%s: HJ not available, DA already assigned", dev->name);
807 return -EACCES;
808 }
809 /* Check if HJ requests DISEC CCC with DISHJ field set has been received */
810 if (sys_read32(config->base + SLV_STATUS1) & SLV_STATUS1_HJ_DIS) {
811 LOG_ERR("%s: HJ requests are currently disabled by DISEC", dev->name);
812 return -EAGAIN;
813 }
814
815 sys_write32(CTRL_HJ_INIT | sys_read32(config->base + CTRL), config->base + CTRL);
816 k_sem_reset(&data->ibi_hj_complete);
817 if (k_sem_take(&data->ibi_hj_complete, K_MSEC(500)) != 0) {
818 LOG_ERR("%s: timeout waiting for DAA after HJ", dev->name);
819 return -ETIMEDOUT;
820 }
821 return 0;
822 }
823
cdns_i3c_target_ibi_raise(const struct device * dev,struct i3c_ibi * request)824 static int cdns_i3c_target_ibi_raise(const struct device *dev, struct i3c_ibi *request)
825 {
826 if (request == NULL) {
827 return -EINVAL;
828 }
829
830 switch (request->ibi_type) {
831 case I3C_IBI_TARGET_INTR:
832 return -ENOTSUP;
833 case I3C_IBI_CONTROLLER_ROLE_REQUEST:
834 /* TODO: Cadence I3C can support CR, but not implemented yet */
835 return -ENOTSUP;
836 case I3C_IBI_HOTJOIN:
837 return cdns_i3c_target_ibi_raise_hj(dev);
838 default:
839 return -EINVAL;
840 }
841 }
842 #endif
843
cdns_i3c_cancel_transfer(const struct device * dev)844 static void cdns_i3c_cancel_transfer(const struct device *dev)
845 {
846 struct cdns_i3c_data *data = dev->data;
847 const struct cdns_i3c_config *config = dev->config;
848 uint32_t val;
849 uint32_t retry_count;
850
851 /* Disable further interrupts */
852 sys_write32(MST_INT_CMDD_EMP, config->base + MST_IDR);
853
854 /* Ignore if no pending transfer */
855 if (data->xfer.num_cmds == 0) {
856 return;
857 }
858
859 data->xfer.num_cmds = 0;
860
861 /* Clear main enable bit to disable further transactions */
862 sys_write32(~CTRL_DEV_EN & sys_read32(config->base + CTRL), config->base + CTRL);
863
864 /**
865 * Spin waiting for device to go idle. It is unlikely that this will
866 * actually take any time since we only get here if a transaction didn't
867 * complete in a long time.
868 */
869 retry_count = I3C_MAX_IDLE_CANCEL_WAIT_RETRIES;
870 while (retry_count--) {
871 val = sys_read32(config->base + MST_STATUS0);
872 if (val & MST_STATUS0_IDLE) {
873 break;
874 }
875 k_msleep(10);
876 }
877 if (retry_count == 0) {
878 data->xfer.ret = -ETIMEDOUT;
879 }
880
881 /**
882 * Flush all queues.
883 */
884 sys_write32(FLUSH_RX_FIFO | FLUSH_TX_FIFO | FLUSH_CMD_FIFO | FLUSH_CMD_RESP,
885 config->base + FLUSH_CTRL);
886
887 /* Re-enable device */
888 sys_write32(CTRL_DEV_EN | sys_read32(config->base + CTRL), config->base + CTRL);
889 }
890
891 /**
892 * @brief Start a I3C/I2C Transfer
893 *
894 * This is to be called from a I3C/I2C transfer function. This will write
895 * all data to tx and cmd fifos
896 *
897 * @param dev Pointer to controller device driver instance.
898 */
cdns_i3c_start_transfer(const struct device * dev)899 static void cdns_i3c_start_transfer(const struct device *dev)
900 {
901 struct cdns_i3c_data *data = dev->data;
902 const struct cdns_i3c_config *config = dev->config;
903 struct cdns_i3c_xfer *xfer = &data->xfer;
904
905 /* Ensure no pending command response queue threshold interrupt */
906 sys_write32(MST_INT_CMDD_EMP, config->base + MST_ICR);
907
908 /* Make sure RX FIFO is empty. */
909 while (!cdns_i3c_rx_fifo_empty(config)) {
910 (void)sys_read32(config->base + RX_FIFO);
911 }
912 /* Make sure CMDR FIFO is empty too */
913 while (!cdns_i3c_cmd_rsp_fifo_empty(config)) {
914 (void)sys_read32(config->base + CMDR);
915 }
916
917 /* Write all tx data to fifo */
918 for (unsigned int i = 0; i < xfer->num_cmds; i++) {
919 if (!(xfer->cmds[i].cmd0 & CMD0_FIFO_RNW)) {
920 cdns_i3c_write_tx_fifo(config, xfer->cmds[i].buf, xfer->cmds[i].len);
921 }
922 }
923
924 /* Write all data to cmd fifos */
925 for (unsigned int i = 0; i < xfer->num_cmds; i++) {
926 /* The command ID is just the msg index. */
927 xfer->cmds[i].cmd1 |= CMD1_FIFO_CMDID(i);
928 sys_write32(xfer->cmds[i].cmd1, config->base + CMD1_FIFO);
929 sys_write32(xfer->cmds[i].cmd0, config->base + CMD0_FIFO);
930 }
931
932 /* kickoff transfer */
933 sys_write32(CTRL_MCS | sys_read32(config->base + CTRL), config->base + CTRL);
934 sys_write32(MST_INT_CMDD_EMP, config->base + MST_IER);
935 }
936
937 /**
938 * @brief Send Common Command Code (CCC).
939 *
940 * @see i3c_do_ccc
941 *
942 * @param dev Pointer to controller device driver instance.
943 * @param payload Pointer to CCC payload.
944 *
945 * @return @see i3c_do_ccc
946 */
cdns_i3c_do_ccc(const struct device * dev,struct i3c_ccc_payload * payload)947 static int cdns_i3c_do_ccc(const struct device *dev, struct i3c_ccc_payload *payload)
948 {
949 const struct cdns_i3c_config *config = dev->config;
950 struct cdns_i3c_data *data = dev->data;
951 struct cdns_i3c_cmd *dcmd = &data->xfer.cmds[0];
952 int ret = 0;
953 int num_cmds = 0;
954
955 /* make sure we are currently the active controller */
956 if (!(sys_read32(config->base + MST_STATUS0) & MST_STATUS0_MASTER_MODE)) {
957 return -EACCES;
958 }
959
960 if (payload == NULL) {
961 return -EINVAL;
962 }
963
964 /*
965 * Ensure data will fit within FIFOs.
966 *
967 * TODO: This limitation prevents burst transfers greater than the
968 * FIFO sizes and should be replaced with an implementation that
969 * utilizes the RX/TX data threshold interrupts.
970 */
971 uint32_t num_msgs =
972 1 + ((payload->ccc.data_len > 0) ? payload->targets.num_targets
973 : MAX(payload->targets.num_targets - 1, 0));
974 if (num_msgs > data->hw_cfg.cmd_mem_depth || num_msgs > data->hw_cfg.cmdr_mem_depth) {
975 LOG_ERR("%s: Too many messages", dev->name);
976 return -ENOMEM;
977 }
978
979 uint32_t rxsize = 0;
980 uint32_t txsize = ROUND_UP(payload->ccc.data_len, 4);
981
982 for (int i = 0; i < payload->targets.num_targets; i++) {
983 if (payload->targets.payloads[i].rnw) {
984 rxsize += ROUND_UP(payload->targets.payloads[i].data_len, 4);
985 } else {
986 txsize += ROUND_UP(payload->targets.payloads[i].data_len, 4);
987 }
988 }
989 if ((rxsize > data->hw_cfg.rx_mem_depth) || (txsize > data->hw_cfg.tx_mem_depth)) {
990 LOG_ERR("%s: Total RX and/or TX transfer larger than FIFO", dev->name);
991 return -ENOMEM;
992 }
993
994 LOG_DBG("%s: CCC[0x%02x]", dev->name, payload->ccc.id);
995
996 k_mutex_lock(&data->bus_lock, K_FOREVER);
997
998 /**
999 * Spin waiting for device to go idle. It is unlikely that this will
1000 * actually take any time unless if the last transaction came immediately
1001 * after an error condition.
1002 */
1003 uint32_t retry_count = I3C_MAX_IDLE_WAIT_RETRIES;
1004
1005 while (!(sys_read32(config->base + MST_STATUS0) & MST_STATUS0_IDLE) && (retry_count > 0)) {
1006 retry_count--;
1007 }
1008 if (retry_count == 0) {
1009 LOG_ERR("%s: Unable to start transfer, device not idle", dev->name);
1010 ret = -EAGAIN;
1011 goto error;
1012 }
1013
1014 dcmd->cmd1 = CMD1_FIFO_CCC(payload->ccc.id);
1015 dcmd->cmd0 = CMD0_FIFO_IS_CCC;
1016 dcmd->len = 0;
1017
1018 size_t idx = 0;
1019
1020 if (payload->ccc.data_len > 0) {
1021 /* Write additional data for CCC if needed */
1022 dcmd->buf = payload->ccc.data;
1023 dcmd->len = payload->ccc.data_len;
1024 dcmd->cmd0 |= CMD0_FIFO_PL_LEN(payload->ccc.data_len);
1025 } else if (payload->targets.num_targets > 0) {
1026 dcmd->buf = payload->targets.payloads[0].data;
1027 dcmd->len = payload->targets.payloads[0].data_len;
1028 dcmd->cmd0 |= CMD0_FIFO_DEV_ADDR(payload->targets.payloads[0].addr) |
1029 CMD0_FIFO_PL_LEN(payload->targets.payloads[0].data_len);
1030 if (payload->targets.payloads[0].rnw) {
1031 dcmd->cmd0 |= CMD0_FIFO_RNW;
1032 }
1033 idx++;
1034 }
1035 num_cmds++;
1036
1037 if (!i3c_ccc_is_payload_broadcast(payload)) {
1038 /*
1039 * If there are payload(s) for each target,
1040 * RESTART and then send payload for each target.
1041 */
1042 while (idx < payload->targets.num_targets) {
1043 num_cmds++;
1044 struct cdns_i3c_cmd *cmd = &data->xfer.cmds[idx + 1];
1045 struct i3c_ccc_target_payload *tgt_payload =
1046 &payload->targets.payloads[idx];
1047 /* Send repeated start on all transfers except the last */
1048 if (idx < (payload->targets.num_targets - 1)) {
1049 cmd->cmd0 |= CMD0_FIFO_RSBC;
1050 }
1051 cmd->cmd0 |= CMD0_FIFO_DEV_ADDR(tgt_payload->addr);
1052 if (tgt_payload->rnw) {
1053 cmd->cmd0 |= CMD0_FIFO_RNW;
1054 }
1055
1056 cmd->buf = tgt_payload->data;
1057 cmd->len = tgt_payload->data_len;
1058
1059 idx++;
1060 }
1061 }
1062
1063 data->xfer.ret = -ETIMEDOUT;
1064 data->xfer.num_cmds = num_cmds;
1065
1066 cdns_i3c_start_transfer(dev);
1067 if (k_sem_take(&data->xfer.complete, K_MSEC(1000)) != 0) {
1068 cdns_i3c_cancel_transfer(dev);
1069 }
1070
1071 if (data->xfer.ret < 0) {
1072 LOG_ERR("%s: CCC[0x%02x] error (%d)", dev->name, payload->ccc.id, data->xfer.ret);
1073 }
1074
1075 ret = data->xfer.ret;
1076 error:
1077 k_mutex_unlock(&data->bus_lock);
1078
1079 return ret;
1080 }
1081
1082 /**
1083 * @brief Perform Dynamic Address Assignment.
1084 *
1085 * @see i3c_do_daa
1086 *
1087 * @param dev Pointer to controller device driver instance.
1088 *
1089 * @return @see i3c_do_daa
1090 */
cdns_i3c_do_daa(const struct device * dev)1091 static int cdns_i3c_do_daa(const struct device *dev)
1092 {
1093 struct cdns_i3c_data *data = dev->data;
1094 const struct cdns_i3c_config *config = dev->config;
1095 struct i3c_config_controller *ctrl_config = &data->common.ctrl_config;
1096
1097 /* DAA should not be done by secondary controllers */
1098 if (ctrl_config->is_secondary) {
1099 return -ENOTSUP;
1100 }
1101
1102 /* read dev active reg */
1103 uint32_t olddevs = sys_read32(config->base + DEVS_CTRL) & DEVS_CTRL_DEVS_ACTIVE_MASK;
1104 /* ignore the controller register */
1105 olddevs |= BIT(0);
1106
1107 /* the Cadence I3C IP will assign an address for it from the RR */
1108 struct i3c_ccc_payload entdaa_ccc;
1109
1110 memset(&entdaa_ccc, 0, sizeof(entdaa_ccc));
1111 entdaa_ccc.ccc.id = I3C_CCC_ENTDAA;
1112
1113 int status = cdns_i3c_do_ccc(dev, &entdaa_ccc);
1114
1115 if (status != 0) {
1116 return status;
1117 }
1118
1119 /* read again dev active reg */
1120 uint32_t newdevs = sys_read32(config->base + DEVS_CTRL) & DEVS_CTRL_DEVS_ACTIVE_MASK;
1121 /* look for new bits that were set */
1122 newdevs &= ~olddevs;
1123
1124 if (newdevs) {
1125 /* loop through each set bit for new devices */
1126 for (uint8_t i = find_lsb_set(newdevs); i <= find_msb_set(newdevs); i++) {
1127 uint8_t rr_idx = i - 1;
1128
1129 if (newdevs & BIT(rr_idx)) {
1130 /* Read RRx registers */
1131 uint32_t dev_id_rr0 = sys_read32(config->base + DEV_ID_RR0(rr_idx));
1132 uint32_t dev_id_rr1 = sys_read32(config->base + DEV_ID_RR1(rr_idx));
1133 uint32_t dev_id_rr2 = sys_read32(config->base + DEV_ID_RR2(rr_idx));
1134
1135 uint64_t pid = ((uint64_t)dev_id_rr1 << 16) + (dev_id_rr2 >> 16);
1136 uint8_t dyn_addr = (dev_id_rr0 & 0xFE) >> 1;
1137 uint8_t bcr = dev_id_rr2 >> 8;
1138 uint8_t dcr = dev_id_rr2 & 0xFF;
1139
1140 const struct i3c_device_id i3c_id = I3C_DEVICE_ID(pid);
1141 struct i3c_device_desc *target = i3c_device_find(dev, &i3c_id);
1142
1143 if (target == NULL) {
1144 LOG_INF("%s: PID 0x%012llx is not in registered device "
1145 "list, given DA 0x%02x",
1146 dev->name, pid, dyn_addr);
1147 i3c_addr_slots_mark_i3c(
1148 &data->common.attached_dev.addr_slots, dyn_addr);
1149 } else {
1150 target->dynamic_addr = dyn_addr;
1151 target->bcr = bcr;
1152 target->dcr = dcr;
1153
1154 LOG_DBG("%s: PID 0x%012llx assigned dynamic address 0x%02x",
1155 dev->name, pid, dyn_addr);
1156 }
1157 }
1158 }
1159 } else {
1160 LOG_DBG("%s: ENTDAA: No devices found", dev->name);
1161 }
1162
1163 /* mark slot as not free, may already be set if already attached */
1164 data->free_rr_slots &= ~newdevs;
1165
1166 /* Unmask Hot-Join request interrupts. HJ will send DISEC HJ from the CTRL value */
1167 struct i3c_ccc_events i3c_events;
1168
1169 i3c_events.events = I3C_CCC_EVT_HJ;
1170 status = i3c_ccc_do_events_all_set(dev, true, &i3c_events);
1171 if (status != 0) {
1172 LOG_DBG("%s: Broadcast ENEC was NACK", dev->name);
1173 }
1174
1175 return 0;
1176 }
1177
1178 /**
1179 * @brief Configure I2C hardware.
1180 *
1181 * @param dev Pointer to controller device driver instance.
1182 * @param config Value of the configuration parameters.
1183 *
1184 * @retval 0 If successful.
1185 * @retval -EINVAL If invalid configure parameters.
1186 * @retval -EIO General Input/Output errors.
1187 * @retval -ENOSYS If not implemented.
1188 */
cdns_i3c_i2c_api_configure(const struct device * dev,uint32_t config)1189 static int cdns_i3c_i2c_api_configure(const struct device *dev, uint32_t config)
1190 {
1191 struct cdns_i3c_data *data = dev->data;
1192 struct i3c_config_controller *ctrl_config = &data->common.ctrl_config;
1193
1194 switch (I2C_SPEED_GET(config)) {
1195 case I2C_SPEED_STANDARD:
1196 ctrl_config->scl.i2c = 100000;
1197 break;
1198 case I2C_SPEED_FAST:
1199 ctrl_config->scl.i2c = 400000;
1200 break;
1201 case I2C_SPEED_FAST_PLUS:
1202 ctrl_config->scl.i2c = 1000000;
1203 break;
1204 case I2C_SPEED_HIGH:
1205 ctrl_config->scl.i2c = 3400000;
1206 break;
1207 case I2C_SPEED_ULTRA:
1208 ctrl_config->scl.i2c = 5000000;
1209 break;
1210 default:
1211 break;
1212 }
1213
1214 cdns_i3c_set_prescalers(dev);
1215
1216 return 0;
1217 }
1218
1219 /**
1220 * @brief Configure I3C hardware.
1221 *
1222 * @param dev Pointer to controller device driver instance.
1223 * @param type Type of configuration parameters being passed
1224 * in @p config.
1225 * @param config Pointer to the configuration parameters.
1226 *
1227 * @retval 0 If successful.
1228 * @retval -EINVAL If invalid configure parameters.
1229 * @retval -EIO General Input/Output errors.
1230 * @retval -ENOSYS If not implemented.
1231 */
cdns_i3c_configure(const struct device * dev,enum i3c_config_type type,void * config)1232 static int cdns_i3c_configure(const struct device *dev, enum i3c_config_type type, void *config)
1233 {
1234 struct cdns_i3c_data *data = dev->data;
1235 struct i3c_config_controller *ctrl_cfg = config;
1236
1237 if ((ctrl_cfg->scl.i2c == 0U) || (ctrl_cfg->scl.i3c == 0U)) {
1238 return -EINVAL;
1239 }
1240
1241 data->common.ctrl_config.scl.i3c = ctrl_cfg->scl.i3c;
1242 data->common.ctrl_config.scl.i2c = ctrl_cfg->scl.i2c;
1243 cdns_i3c_set_prescalers(dev);
1244
1245 return 0;
1246 }
1247
1248 /**
1249 * @brief Complete a I3C/I2C Transfer
1250 *
1251 * This is to be called from an ISR when the Command Response FIFO
1252 * is Empty. This will check each Command Response reading the RX
1253 * FIFO if message was a RnW and if any message had an error.
1254 *
1255 * @param dev Pointer to controller device driver instance.
1256 */
cdns_i3c_complete_transfer(const struct device * dev)1257 static void cdns_i3c_complete_transfer(const struct device *dev)
1258 {
1259 struct cdns_i3c_data *data = dev->data;
1260 const struct cdns_i3c_config *config = dev->config;
1261 uint32_t cmdr;
1262 uint32_t id = 0;
1263 uint32_t rx = 0;
1264 int ret = 0;
1265 struct cdns_i3c_cmd *cmd;
1266
1267 /* Disable further interrupts */
1268 sys_write32(MST_INT_CMDD_EMP, config->base + MST_IDR);
1269
1270 /* Ignore if no pending transfer */
1271 if (data->xfer.num_cmds == 0) {
1272 return;
1273 }
1274
1275 /* Process all results in fifo */
1276 for (uint32_t status0 = sys_read32(config->base + MST_STATUS0);
1277 !(status0 & MST_STATUS0_CMDR_EMP); status0 = sys_read32(config->base + MST_STATUS0)) {
1278 cmdr = sys_read32(config->base + CMDR);
1279 id = CMDR_CMDID(cmdr);
1280
1281 if (id == CMDR_CMDID_HJACK_DISEC || id == CMDR_CMDID_HJACK_ENTDAA ||
1282 id >= data->xfer.num_cmds) {
1283 continue;
1284 }
1285
1286 cmd = &data->xfer.cmds[id];
1287
1288 /* Read any rx data into buffer */
1289 if (cmd->cmd0 & CMD0_FIFO_RNW) {
1290 rx = MIN(CMDR_XFER_BYTES(cmdr), cmd->len);
1291 ret = cdns_i3c_read_rx_fifo(config, cmd->buf, rx);
1292 }
1293
1294 /* Record error */
1295 cmd->error = CMDR_ERROR(cmdr);
1296 }
1297
1298 for (int i = 0; i < data->xfer.num_cmds; i++) {
1299 switch (data->xfer.cmds[i].error) {
1300 case CMDR_NO_ERROR:
1301 break;
1302
1303 case CMDR_DDR_PREAMBLE_ERROR:
1304 case CMDR_DDR_PARITY_ERROR:
1305 case CMDR_M0_ERROR:
1306 case CMDR_M1_ERROR:
1307 case CMDR_M2_ERROR:
1308 case CMDR_MST_ABORT:
1309 case CMDR_NACK_RESP:
1310 case CMDR_DDR_DROPPED:
1311 ret = -EIO;
1312 break;
1313
1314 case CMDR_DDR_RX_FIFO_OVF:
1315 case CMDR_DDR_TX_FIFO_UNF:
1316 ret = -ENOSPC;
1317 break;
1318
1319 case CMDR_INVALID_DA:
1320 default:
1321 ret = -EINVAL;
1322 break;
1323 }
1324 }
1325
1326 data->xfer.ret = ret;
1327
1328 /* Indicate no transfer is pending */
1329 data->xfer.num_cmds = 0;
1330
1331 k_sem_give(&data->xfer.complete);
1332 }
1333
1334 /**
1335 * @brief Transfer messages in I2C mode.
1336 *
1337 * @param dev Pointer to device driver instance.
1338 * @param target Pointer to target device descriptor.
1339 * @param msgs Pointer to I2C messages.
1340 * @param num_msgs Number of messages to transfers.
1341 *
1342 * @retval 0 If successful.
1343 * @retval -EIO General input / output error.
1344 * @retval -EINVAL Address not registered
1345 */
cdns_i3c_i2c_transfer(const struct device * dev,struct i3c_i2c_device_desc * i2c_dev,struct i2c_msg * msgs,uint8_t num_msgs)1346 static int cdns_i3c_i2c_transfer(const struct device *dev, struct i3c_i2c_device_desc *i2c_dev,
1347 struct i2c_msg *msgs, uint8_t num_msgs)
1348 {
1349 const struct cdns_i3c_config *config = dev->config;
1350 struct cdns_i3c_data *data = dev->data;
1351 uint32_t txsize = 0;
1352 uint32_t rxsize = 0;
1353 int ret;
1354
1355 /* make sure we are currently the active controller */
1356 if (!(sys_read32(config->base + MST_STATUS0) & MST_STATUS0_MASTER_MODE)) {
1357 return -EACCES;
1358 }
1359
1360 if (num_msgs == 0) {
1361 return 0;
1362 }
1363
1364 if (num_msgs > data->hw_cfg.cmd_mem_depth || num_msgs > data->hw_cfg.cmdr_mem_depth) {
1365 LOG_ERR("%s: Too many messages", dev->name);
1366 return -ENOMEM;
1367 }
1368
1369 /*
1370 * Ensure data will fit within FIFOs
1371 */
1372 for (unsigned int i = 0; i < num_msgs; i++) {
1373 if ((msgs[i].flags & I2C_MSG_RW_MASK) == I2C_MSG_READ) {
1374 rxsize += ROUND_UP(msgs[i].len, 4);
1375 } else {
1376 txsize += ROUND_UP(msgs[i].len, 4);
1377 }
1378 }
1379 if ((rxsize > data->hw_cfg.rx_mem_depth) || (txsize > data->hw_cfg.tx_mem_depth)) {
1380 LOG_ERR("%s: Total RX and/or TX transfer larger than FIFO", dev->name);
1381 return -ENOMEM;
1382 }
1383
1384 k_mutex_lock(&data->bus_lock, K_FOREVER);
1385
1386 /**
1387 * Spin waiting for device to go idle. It is unlikely that this will
1388 * actually take any time unless if the last transaction came immediately
1389 * after an error condition.
1390 */
1391 uint32_t retry_count = I3C_MAX_IDLE_WAIT_RETRIES;
1392
1393 while (!(sys_read32(config->base + MST_STATUS0) & MST_STATUS0_IDLE) && (retry_count > 0)) {
1394 retry_count--;
1395 }
1396 if (retry_count == 0) {
1397 LOG_ERR("%s: Unable to start transfer, device not idle", dev->name);
1398 ret = -EAGAIN;
1399 goto error;
1400 }
1401
1402 for (unsigned int i = 0; i < num_msgs; i++) {
1403 struct cdns_i3c_cmd *cmd = &data->xfer.cmds[i];
1404
1405 cmd->len = msgs[i].len;
1406 cmd->buf = msgs[i].buf;
1407
1408 cmd->cmd0 = CMD0_FIFO_PRIV_XMIT_MODE(XMIT_BURST_WITHOUT_SUBADDR);
1409 cmd->cmd0 |= CMD0_FIFO_DEV_ADDR(i2c_dev->addr);
1410 cmd->cmd0 |= CMD0_FIFO_PL_LEN(msgs[i].len);
1411
1412 /* Send repeated start on all transfers except the last or those marked STOP. */
1413 if ((i < (num_msgs - 1)) && ((msgs[i].flags & I2C_MSG_STOP) == 0)) {
1414 cmd->cmd0 |= CMD0_FIFO_RSBC;
1415 }
1416
1417 if (msgs[i].flags & I2C_MSG_ADDR_10_BITS) {
1418 cmd->cmd0 |= CMD0_FIFO_IS_10B;
1419 }
1420
1421 if ((msgs[i].flags & I2C_MSG_RW_MASK) == I2C_MSG_READ) {
1422 cmd->cmd0 |= CMD0_FIFO_RNW;
1423 }
1424 }
1425
1426 data->xfer.ret = -ETIMEDOUT;
1427 data->xfer.num_cmds = num_msgs;
1428
1429 cdns_i3c_start_transfer(dev);
1430 if (k_sem_take(&data->xfer.complete, K_MSEC(1000)) != 0) {
1431 cdns_i3c_cancel_transfer(dev);
1432 }
1433
1434 ret = data->xfer.ret;
1435 error:
1436 k_mutex_unlock(&data->bus_lock);
1437
1438 return ret;
1439 }
1440
cdns_i3c_master_get_rr_slot(const struct device * dev,uint8_t dyn_addr)1441 static int cdns_i3c_master_get_rr_slot(const struct device *dev, uint8_t dyn_addr)
1442 {
1443 struct cdns_i3c_data *data = dev->data;
1444 const struct cdns_i3c_config *config = dev->config;
1445
1446 if (dyn_addr == 0) {
1447 if (!data->free_rr_slots) {
1448 return -ENOSPC;
1449 }
1450
1451 return find_lsb_set(data->free_rr_slots) - 1;
1452 }
1453
1454 uint32_t activedevs = sys_read32(config->base + DEVS_CTRL) & DEVS_CTRL_DEVS_ACTIVE_MASK;
1455
1456 activedevs &= ~BIT(0);
1457
1458 /* loop through each set bit for new devices */
1459 for (uint8_t i = find_lsb_set(activedevs); i <= find_msb_set(activedevs); i++) {
1460 if (activedevs & BIT(i)) {
1461 uint32_t rr = sys_read32(config->base + DEV_ID_RR0(i));
1462
1463 if (!(rr & DEV_ID_RR0_IS_I3C) || DEV_ID_RR0_GET_DEV_ADDR(rr) != dyn_addr) {
1464 continue;
1465 }
1466 return i;
1467 }
1468 }
1469
1470 return -EINVAL;
1471 }
1472
cdns_i3c_attach_device(const struct device * dev,struct i3c_device_desc * desc,uint8_t addr)1473 static int cdns_i3c_attach_device(const struct device *dev, struct i3c_device_desc *desc,
1474 uint8_t addr)
1475 {
1476 const struct cdns_i3c_config *config = dev->config;
1477 struct cdns_i3c_data *data = dev->data;
1478 int slot = cdns_i3c_master_get_rr_slot(dev, desc->dynamic_addr);
1479
1480 if (slot < 0) {
1481 LOG_ERR("%s: no space for i3c device: %s", dev->name, desc->dev->name);
1482 return slot;
1483 }
1484
1485 k_mutex_lock(&data->bus_lock, K_FOREVER);
1486
1487 data->cdns_i3c_i2c_priv_data[slot].id = slot;
1488 desc->controller_priv = &(data->cdns_i3c_i2c_priv_data[slot]);
1489 data->free_rr_slots &= ~BIT(slot);
1490
1491 uint32_t dev_id_rr0 = DEV_ID_RR0_IS_I3C | prepare_rr0_dev_address(addr);
1492 uint32_t dev_id_rr1 = DEV_ID_RR1_PID_MSB((desc->pid & 0xFFFFFFFF0000) >> 16);
1493 uint32_t dev_id_rr2 = DEV_ID_RR2_PID_LSB(desc->pid & 0xFFFF);
1494
1495 sys_write32(dev_id_rr0, config->base + DEV_ID_RR0(slot));
1496 sys_write32(dev_id_rr1, config->base + DEV_ID_RR1(slot));
1497 sys_write32(dev_id_rr2, config->base + DEV_ID_RR2(slot));
1498
1499 /** Mark Devices as active, devices that will be found and marked active during DAA,
1500 * it will be given the exact DA programmed in it's RR if the PID matches and marked
1501 * as active duing ENTDAA, otherwise they get set as active here. If dynamic address
1502 * is set, then it assumed that it was already initialized by the primary controller.
1503 */
1504 if ((desc->static_addr != 0) || (desc->dynamic_addr != 0)) {
1505 sys_write32(sys_read32(config->base + DEVS_CTRL) | DEVS_CTRL_DEV_ACTIVE(slot),
1506 config->base + DEVS_CTRL);
1507 }
1508
1509 k_mutex_unlock(&data->bus_lock);
1510
1511 return 0;
1512 }
1513
cdns_i3c_reattach_device(const struct device * dev,struct i3c_device_desc * desc,uint8_t old_dyn_addr)1514 static int cdns_i3c_reattach_device(const struct device *dev, struct i3c_device_desc *desc,
1515 uint8_t old_dyn_addr)
1516 {
1517 const struct cdns_i3c_config *config = dev->config;
1518 struct cdns_i3c_data *data = dev->data;
1519 struct cdns_i3c_i2c_dev_data *cdns_i3c_device_data = desc->controller_priv;
1520
1521 if (cdns_i3c_device_data == NULL) {
1522 LOG_ERR("%s: %s: device not attached", dev->name, desc->dev->name);
1523 return -EINVAL;
1524 }
1525
1526 k_mutex_lock(&data->bus_lock, K_FOREVER);
1527
1528 uint32_t dev_id_rr0 = DEV_ID_RR0_IS_I3C | prepare_rr0_dev_address(desc->dynamic_addr);
1529 uint32_t dev_id_rr1 = DEV_ID_RR1_PID_MSB((desc->pid & 0xFFFFFFFF0000) >> 16);
1530 uint32_t dev_id_rr2 = DEV_ID_RR2_PID_LSB(desc->pid & 0xFFFF) | DEV_ID_RR2_BCR(desc->bcr) |
1531 DEV_ID_RR2_DCR(desc->dcr);
1532
1533 sys_write32(dev_id_rr0, config->base + DEV_ID_RR0(cdns_i3c_device_data->id));
1534 sys_write32(dev_id_rr1, config->base + DEV_ID_RR1(cdns_i3c_device_data->id));
1535 sys_write32(dev_id_rr2, config->base + DEV_ID_RR2(cdns_i3c_device_data->id));
1536
1537 k_mutex_unlock(&data->bus_lock);
1538
1539 return 0;
1540 }
1541
cdns_i3c_detach_device(const struct device * dev,struct i3c_device_desc * desc)1542 static int cdns_i3c_detach_device(const struct device *dev, struct i3c_device_desc *desc)
1543 {
1544 const struct cdns_i3c_config *config = dev->config;
1545 struct cdns_i3c_data *data = dev->data;
1546 struct cdns_i3c_i2c_dev_data *cdns_i3c_device_data = desc->controller_priv;
1547
1548 if (cdns_i3c_device_data == NULL) {
1549 LOG_ERR("%s: %s: device not attached", dev->name, desc->dev->name);
1550 return -EINVAL;
1551 }
1552
1553 k_mutex_lock(&data->bus_lock, K_FOREVER);
1554
1555 sys_write32(sys_read32(config->base + DEVS_CTRL) |
1556 DEVS_CTRL_DEV_CLR(cdns_i3c_device_data->id),
1557 config->base + DEVS_CTRL);
1558 data->free_rr_slots |= BIT(cdns_i3c_device_data->id);
1559 desc->controller_priv = NULL;
1560
1561 k_mutex_unlock(&data->bus_lock);
1562
1563 return 0;
1564 }
1565
cdns_i3c_i2c_attach_device(const struct device * dev,struct i3c_i2c_device_desc * desc)1566 static int cdns_i3c_i2c_attach_device(const struct device *dev, struct i3c_i2c_device_desc *desc)
1567 {
1568 const struct cdns_i3c_config *config = dev->config;
1569 struct cdns_i3c_data *data = dev->data;
1570
1571 int slot = cdns_i3c_master_get_rr_slot(dev, 0);
1572
1573 if (slot < 0) {
1574 LOG_ERR("%s: no space for i2c device: addr 0x%02x", dev->name, desc->addr);
1575 return slot;
1576 }
1577
1578 k_mutex_lock(&data->bus_lock, K_FOREVER);
1579
1580 uint32_t dev_id_rr0 = prepare_rr0_dev_address(desc->addr);
1581 uint32_t dev_id_rr2 = DEV_ID_RR2_LVR(desc->lvr);
1582
1583 sys_write32(dev_id_rr0, config->base + DEV_ID_RR0(slot));
1584 sys_write32(0, config->base + DEV_ID_RR1(slot));
1585 sys_write32(dev_id_rr2, config->base + DEV_ID_RR2(slot));
1586
1587 data->cdns_i3c_i2c_priv_data[slot].id = slot;
1588 desc->controller_priv = &(data->cdns_i3c_i2c_priv_data[slot]);
1589 data->free_rr_slots &= ~BIT(slot);
1590
1591 sys_write32(sys_read32(config->base + DEVS_CTRL) | DEVS_CTRL_DEV_ACTIVE(slot),
1592 config->base + DEVS_CTRL);
1593
1594 k_mutex_unlock(&data->bus_lock);
1595
1596 return 0;
1597 }
1598
cdns_i3c_i2c_detach_device(const struct device * dev,struct i3c_i2c_device_desc * desc)1599 static int cdns_i3c_i2c_detach_device(const struct device *dev, struct i3c_i2c_device_desc *desc)
1600 {
1601 const struct cdns_i3c_config *config = dev->config;
1602 struct cdns_i3c_data *data = dev->data;
1603 struct cdns_i3c_i2c_dev_data *cdns_i2c_device_data = desc->controller_priv;
1604
1605 if (cdns_i2c_device_data == NULL) {
1606 LOG_ERR("%s: device not attached", dev->name);
1607 return -EINVAL;
1608 }
1609
1610 k_mutex_lock(&data->bus_lock, K_FOREVER);
1611
1612 sys_write32(sys_read32(config->base + DEVS_CTRL) |
1613 DEVS_CTRL_DEV_CLR(cdns_i2c_device_data->id),
1614 config->base + DEVS_CTRL);
1615 data->free_rr_slots |= BIT(cdns_i2c_device_data->id);
1616 desc->controller_priv = NULL;
1617
1618 k_mutex_unlock(&data->bus_lock);
1619
1620 return 0;
1621 }
1622
1623 /**
1624 * @brief Transfer messages in I3C mode.
1625 *
1626 * @see i3c_transfer
1627 *
1628 * @param dev Pointer to device driver instance.
1629 * @param target Pointer to target device descriptor.
1630 * @param msgs Pointer to I3C messages.
1631 * @param num_msgs Number of messages to transfers.
1632 *
1633 * @return @see i3c_transfer
1634 */
cdns_i3c_transfer(const struct device * dev,struct i3c_device_desc * target,struct i3c_msg * msgs,uint8_t num_msgs)1635 static int cdns_i3c_transfer(const struct device *dev, struct i3c_device_desc *target,
1636 struct i3c_msg *msgs, uint8_t num_msgs)
1637 {
1638 const struct cdns_i3c_config *config = dev->config;
1639 struct cdns_i3c_data *data = dev->data;
1640 int txsize = 0;
1641 int rxsize = 0;
1642 int ret;
1643
1644 /* make sure we are currently the active controller */
1645 if (!(sys_read32(config->base + MST_STATUS0) & MST_STATUS0_MASTER_MODE)) {
1646 return -EACCES;
1647 }
1648
1649 if (num_msgs == 0) {
1650 return 0;
1651 }
1652
1653 if (num_msgs > data->hw_cfg.cmd_mem_depth || num_msgs > data->hw_cfg.cmdr_mem_depth) {
1654 LOG_ERR("%s: Too many messages", dev->name);
1655 return -ENOMEM;
1656 }
1657
1658 /*
1659 * Ensure data will fit within FIFOs.
1660 *
1661 * TODO: This limitation prevents burst transfers greater than the
1662 * FIFO sizes and should be replaced with an implementation that
1663 * utilizes the RX/TX data interrupts.
1664 */
1665 for (int i = 0; i < num_msgs; i++) {
1666 if ((msgs[i].flags & I3C_MSG_RW_MASK) == I3C_MSG_READ) {
1667 rxsize += ROUND_UP(msgs[i].len, 4);
1668 } else {
1669 txsize += ROUND_UP(msgs[i].len, 4);
1670 }
1671 }
1672 if ((rxsize > data->hw_cfg.rx_mem_depth) || (txsize > data->hw_cfg.tx_mem_depth)) {
1673 LOG_ERR("%s: Total RX and/or TX transfer larger than FIFO", dev->name);
1674 return -ENOMEM;
1675 }
1676
1677 k_mutex_lock(&data->bus_lock, K_FOREVER);
1678
1679 /**
1680 * Spin waiting for device to go idle. It is unlikely that this will
1681 * actually take any time unless if the last transaction came immediately
1682 * after an error condition.
1683 */
1684 uint32_t retry_count = I3C_MAX_IDLE_WAIT_RETRIES;
1685
1686 while (!(sys_read32(config->base + MST_STATUS0) & MST_STATUS0_IDLE) && (retry_count > 0)) {
1687 retry_count--;
1688 }
1689 if (retry_count == 0) {
1690 LOG_ERR("%s: Unable to start transfer, device not idle", dev->name);
1691 ret = -EAGAIN;
1692 goto error;
1693 }
1694
1695 /*
1696 * Prepare transfer commands. Currently there is only a single transfer
1697 * in-flight but it would be possible to keep a queue of transfers. If so,
1698 * this preparation could be completed outside of the bus lock allowing
1699 * greater parallelism.
1700 */
1701 bool send_broadcast = true;
1702
1703 for (int i = 0; i < num_msgs; i++) {
1704 struct cdns_i3c_cmd *cmd = &data->xfer.cmds[i];
1705 uint32_t pl = msgs[i].len;
1706
1707 cmd->len = pl;
1708 cmd->buf = msgs[i].buf;
1709
1710 cmd->cmd0 = CMD0_FIFO_PRIV_XMIT_MODE(XMIT_BURST_WITHOUT_SUBADDR);
1711 cmd->cmd0 |= CMD0_FIFO_DEV_ADDR(target->dynamic_addr);
1712 if ((msgs[i].flags & I3C_MSG_RW_MASK) == I3C_MSG_READ) {
1713 cmd->cmd0 |= CMD0_FIFO_RNW;
1714 /*
1715 * For I3C_XMIT_MODE_NO_ADDR reads in SDN mode,
1716 * CMD0_FIFO_PL_LEN specifies the abort limit not bytes to read
1717 */
1718 cmd->cmd0 |= CMD0_FIFO_PL_LEN(pl + 1);
1719 } else {
1720 cmd->cmd0 |= CMD0_FIFO_PL_LEN(pl);
1721 }
1722
1723 /* Send broadcast header on first transfer or after a STOP. */
1724 if (!(msgs[i].flags & I3C_MSG_NBCH) && (send_broadcast)) {
1725 cmd->cmd0 |= CMD0_FIFO_BCH;
1726 send_broadcast = false;
1727 }
1728
1729 /* Send repeated start on all transfers except the last or those marked STOP. */
1730 if ((i < (num_msgs - 1)) && ((msgs[i].flags & I3C_MSG_STOP) == 0)) {
1731 cmd->cmd0 |= CMD0_FIFO_RSBC;
1732 } else {
1733 send_broadcast = true;
1734 }
1735 }
1736
1737 data->xfer.ret = -ETIMEDOUT;
1738 data->xfer.num_cmds = num_msgs;
1739
1740 cdns_i3c_start_transfer(dev);
1741 if (k_sem_take(&data->xfer.complete, K_MSEC(1000)) != 0) {
1742 LOG_ERR("%s: transfer timed out", dev->name);
1743 cdns_i3c_cancel_transfer(dev);
1744 }
1745
1746 ret = data->xfer.ret;
1747 error:
1748 k_mutex_unlock(&data->bus_lock);
1749
1750 return ret;
1751 }
1752
1753 #ifdef CONFIG_I3C_USE_IBI
cdns_i3c_read_ibi_fifo(const struct cdns_i3c_config * config,void * buf,uint32_t len)1754 static int cdns_i3c_read_ibi_fifo(const struct cdns_i3c_config *config, void *buf, uint32_t len)
1755 {
1756 uint32_t *ptr = buf;
1757 uint32_t remain, val;
1758
1759 for (remain = len; remain >= 4; remain -= 4) {
1760 if (cdns_i3c_ibi_fifo_empty(config)) {
1761 return -EIO;
1762 }
1763 val = sys_le32_to_cpu(sys_read32(config->base + IBI_DATA_FIFO));
1764 *ptr++ = val;
1765 }
1766
1767 if (remain > 0) {
1768 if (cdns_i3c_ibi_fifo_empty(config)) {
1769 return -EIO;
1770 }
1771 val = sys_le32_to_cpu(sys_read32(config->base + IBI_DATA_FIFO));
1772 memcpy(ptr, &val, remain);
1773 }
1774
1775 return 0;
1776 }
1777
cdns_i3c_handle_ibi(const struct device * dev,uint32_t ibir)1778 static void cdns_i3c_handle_ibi(const struct device *dev, uint32_t ibir)
1779 {
1780 const struct cdns_i3c_config *config = dev->config;
1781 struct cdns_i3c_data *data = dev->data;
1782
1783 uint8_t ibi_data[CONFIG_I3C_IBI_MAX_PAYLOAD_SIZE];
1784
1785 /* The slave ID returned here is the device ID in the SIR map NOT the device ID
1786 * in the RR map.
1787 */
1788 uint8_t slave_id = IBIR_SLVID(ibir);
1789
1790 if (slave_id == IBIR_SLVID_INV) {
1791 /* DA does not match any value among SIR map */
1792 return;
1793 }
1794
1795 uint32_t dev_id_rr0 = sys_read32(config->base + DEV_ID_RR0(slave_id + 1));
1796 uint8_t dyn_addr = DEV_ID_RR0_GET_DEV_ADDR(dev_id_rr0);
1797 struct i3c_device_desc *desc =
1798 i3c_dev_list_i3c_addr_find(&data->common.attached_dev, dyn_addr);
1799
1800 /*
1801 * Check for NAK or error conditions.
1802 *
1803 * Note: The logging is for debugging only so will be compiled out in most cases.
1804 * However, if the log level for this module is DEBUG and log mode is IMMEDIATE or MINIMAL,
1805 * this option is also set this may cause problems due to being inside an ISR.
1806 */
1807 if (!(IBIR_ACKED & ibir)) {
1808 LOG_DBG("%s: NAK for slave ID %u", dev->name, (unsigned int)slave_id);
1809 return;
1810 }
1811 if (ibir & IBIR_ERROR) {
1812 LOG_ERR("%s: Data overflow", dev->name);
1813 return;
1814 }
1815
1816 /* Read out any payload bytes */
1817 uint8_t ibi_len = IBIR_XFER_BYTES(ibir);
1818
1819 if (ibi_len > 0) {
1820 if (cdns_i3c_read_ibi_fifo(config, ibi_data, ibi_len) < 0) {
1821 LOG_ERR("%s: Failed to get payload", dev->name);
1822 }
1823 }
1824
1825 if (i3c_ibi_work_enqueue_target_irq(desc, ibi_data, ibi_len) != 0) {
1826 LOG_ERR("%s: Error enqueue IBI IRQ work", dev->name);
1827 }
1828 }
1829
cdns_i3c_handle_hj(const struct device * dev,uint32_t ibir)1830 static void cdns_i3c_handle_hj(const struct device *dev, uint32_t ibir)
1831 {
1832 if (!(IBIR_ACKED & ibir)) {
1833 LOG_DBG("%s: NAK for HJ", dev->name);
1834 return;
1835 }
1836
1837 if (i3c_ibi_work_enqueue_hotjoin(dev) != 0) {
1838 LOG_ERR("%s: Error enqueue IBI HJ work", dev->name);
1839 }
1840 }
1841
cnds_i3c_master_demux_ibis(const struct device * dev)1842 static void cnds_i3c_master_demux_ibis(const struct device *dev)
1843 {
1844 const struct cdns_i3c_config *config = dev->config;
1845
1846 for (uint32_t status0 = sys_read32(config->base + MST_STATUS0);
1847 !(status0 & MST_STATUS0_IBIR_EMP); status0 = sys_read32(config->base + MST_STATUS0)) {
1848 uint32_t ibir = sys_read32(config->base + IBIR);
1849
1850 switch (IBIR_TYPE(ibir)) {
1851 case IBIR_TYPE_IBI:
1852 cdns_i3c_handle_ibi(dev, ibir);
1853 break;
1854 case IBIR_TYPE_HJ:
1855 cdns_i3c_handle_hj(dev, ibir);
1856 break;
1857 case IBIR_TYPE_MR:
1858 /* not implemented */
1859 break;
1860 default:
1861 break;
1862 }
1863 }
1864 }
1865
cdns_i3c_target_ibi_hj_complete(const struct device * dev)1866 static void cdns_i3c_target_ibi_hj_complete(const struct device *dev)
1867 {
1868 struct cdns_i3c_data *data = dev->data;
1869
1870 k_sem_give(&data->ibi_hj_complete);
1871 }
1872 #endif
1873
cdns_i3c_irq_handler(const struct device * dev)1874 static void cdns_i3c_irq_handler(const struct device *dev)
1875 {
1876 const struct cdns_i3c_config *config = dev->config;
1877
1878 if (sys_read32(config->base + MST_STATUS0) & MST_STATUS0_MASTER_MODE) {
1879 uint32_t int_st = sys_read32(config->base + MST_ISR);
1880
1881 /* Command queue empty */
1882 if (int_st & MST_INT_HALTED) {
1883 LOG_WRN("Core Halted, 2 read aborts");
1884 sys_write32(MST_INT_HALTED, config->base + MST_ICR);
1885 }
1886
1887 /* Command queue empty */
1888 if (int_st & MST_INT_CMDD_EMP) {
1889 cdns_i3c_complete_transfer(dev);
1890 sys_write32(MST_INT_CMDD_EMP, config->base + MST_ICR);
1891 }
1892
1893 /* Command queue threshold */
1894 if (int_st & MST_INT_CMDD_THR) {
1895 sys_write32(MST_INT_CMDD_THR, config->base + MST_ICR);
1896 }
1897
1898 /* Command response threshold hit */
1899 if (int_st & MST_INT_CMDR_THR) {
1900 sys_write32(MST_INT_CMDR_THR, config->base + MST_ICR);
1901 }
1902
1903 /* RX data ready */
1904 if (int_st & MST_INT_RX_THR) {
1905 sys_write32(MST_INT_RX_THR, config->base + MST_ICR);
1906 }
1907
1908 /* In-band interrupt */
1909 if (int_st & MST_INT_IBIR_THR) {
1910 sys_write32(MST_INT_IBIR_THR, config->base + MST_ICR);
1911 #ifdef CONFIG_I3C_USE_IBI
1912 cnds_i3c_master_demux_ibis(dev);
1913 #else
1914 LOG_ERR("%s: IBI received - Kconfig for using IBIs is not enabled",
1915 dev->name);
1916 #endif
1917 }
1918
1919 /* In-band interrupt data */
1920 if (int_st & MST_INT_IBID_THR) {
1921 sys_write32(MST_INT_IBID_THR, config->base + MST_ICR);
1922 }
1923
1924 /* In-band interrupt data */
1925 if (int_st & MST_INT_TX_OVF) {
1926 sys_write32(MST_INT_TX_OVF, config->base + MST_ICR);
1927 LOG_ERR("%s: controller tx buffer overflow,", dev->name);
1928 }
1929
1930 /* In-band interrupt data */
1931 if (int_st & MST_INT_RX_UNF) {
1932 sys_write32(MST_INT_RX_UNF, config->base + MST_ICR);
1933 LOG_ERR("%s: controller rx buffer underflow,", dev->name);
1934 }
1935
1936 /* In-band interrupt data */
1937 if (int_st & MST_INT_IBID_THR) {
1938 sys_write32(MST_INT_IBID_THR, config->base + MST_ICR);
1939 }
1940 } else {
1941 uint32_t int_sl = sys_read32(config->base + SLV_ISR);
1942 struct cdns_i3c_data *data = dev->data;
1943 const struct i3c_target_callbacks *target_cb = data->target_config->callbacks;
1944
1945 /* SLV SDR rx fifo threshold */
1946 if (int_sl & SLV_INT_SDR_RX_THR) {
1947 /* while rx fifo is not empty */
1948 while (!(sys_read32(config->base + SLV_STATUS1) &
1949 SLV_STATUS1_SDR_RX_EMPTY)) {
1950 /* Target writes only write to the first byte of the 32 bit width
1951 * fifo
1952 */
1953 uint8_t rx_data = (uint8_t)sys_read32(config->base + RX_FIFO);
1954 /* call function pointer for write */
1955 if (target_cb != NULL && target_cb->write_received_cb != NULL) {
1956 target_cb->write_received_cb(data->target_config, rx_data);
1957 }
1958 }
1959 }
1960
1961 /* SLV SDR tx fifo threshold */
1962 if (int_sl & SLV_INT_SDR_TX_THR) {
1963 int status = 0;
1964
1965 if (target_cb != NULL && target_cb->read_processed_cb) {
1966 /* while tx fifo is not full and there is still data available */
1967 while ((!(sys_read32(config->base + SLV_STATUS1) &
1968 SLV_STATUS1_SDR_TX_FULL)) &&
1969 (status == 0)) {
1970 /* call function pointer for read */
1971 uint8_t byte;
1972 /* will return negative if no data left to transmit and 0 if
1973 * data available
1974 */
1975 status = target_cb->read_processed_cb(data->target_config,
1976 &byte);
1977 if (status == 0) {
1978 cdns_i3c_write_tx_fifo(config, &byte, sizeof(byte));
1979 }
1980 }
1981 }
1982 }
1983
1984 /* SLV SDR rx complete */
1985 if (int_sl & SLV_INT_SDR_RD_COMP) {
1986 /* a read needs to be done on slv_status 0 else a NACK will happen */
1987 (void)sys_read32(config->base + SLV_STATUS0);
1988 /* call stop function pointer */
1989 if (target_cb != NULL && target_cb->stop_cb) {
1990 target_cb->stop_cb(data->target_config);
1991 }
1992 }
1993
1994 /* SLV SDR tx complete */
1995 if (int_sl & SLV_INT_SDR_WR_COMP) {
1996 /* a read needs to be done on slv_status 0 else a NACK will happen */
1997 (void)sys_read32(config->base + SLV_STATUS0);
1998 /* call stop function pointer */
1999 if (target_cb != NULL && target_cb->stop_cb) {
2000 target_cb->stop_cb(data->target_config);
2001 }
2002 }
2003
2004 /* DA has been updated */
2005 if (int_sl & SLV_INT_DA_UPD) {
2006 LOG_INF("%s: DA updated to 0x%02lx", dev->name,
2007 SLV_STATUS1_DA(sys_read32(config->base + SLV_STATUS1)));
2008 /* HJ could send a DISEC which would trigger the SLV_INT_EVENT_UP bit,
2009 * but it's still expected to eventually send a DAA
2010 */
2011 #ifdef CONFIG_I3C_USE_IBI
2012 cdns_i3c_target_ibi_hj_complete(dev);
2013 #endif
2014 }
2015
2016 /* HJ complete and DA has been assigned */
2017 if (int_sl & SLV_INT_HJ_DONE) {
2018 }
2019
2020 /* Controllership has been been given */
2021 if (int_sl & SLV_INT_MR_DONE) {
2022 /* TODO: implement support for controllership handoff */
2023 }
2024
2025 /* EISC or DISEC has been received */
2026 if (int_sl & SLV_INT_EVENT_UP) {
2027 }
2028
2029 /* sdr transfer aborted by controller */
2030 if (int_sl & SLV_INT_M_RD_ABORT) {
2031 /* TODO: consider flushing tx buffer? */
2032 }
2033
2034 /* SLV SDR rx fifo underflow */
2035 if (int_sl & SLV_INT_SDR_RX_UNF) {
2036 LOG_ERR("%s: slave sdr rx buffer underflow", dev->name);
2037 }
2038
2039 /* SLV SDR tx fifo overflow */
2040 if (int_sl & SLV_INT_SDR_TX_OVF) {
2041 LOG_ERR("%s: slave sdr tx buffer overflow,", dev->name);
2042 }
2043
2044 sys_write32(int_sl, config->base + SLV_ICR);
2045 }
2046 }
2047
cdns_i3c_read_hw_cfg(const struct device * dev)2048 static void cdns_i3c_read_hw_cfg(const struct device *dev)
2049 {
2050 const struct cdns_i3c_config *config = dev->config;
2051 struct cdns_i3c_data *data = dev->data;
2052
2053 uint32_t devid = sys_read32(config->base + DEV_ID);
2054 uint32_t revid = sys_read32(config->base + REV_ID);
2055
2056 LOG_DBG("%s: Device info:\r\n"
2057 " vid: 0x%03lX, pid: 0x%03lX\r\n"
2058 " revision: major = %lu, minor = %lu\r\n"
2059 " device ID: 0x%04X",
2060 dev->name, REV_ID_VID(revid), REV_ID_PID(revid), REV_ID_REV_MAJOR(revid),
2061 REV_ID_REV_MINOR(revid), devid);
2062
2063 /*
2064 * Depths are specified as number of words (32bit), convert to bytes
2065 */
2066 uint32_t cfg0 = sys_read32(config->base + CONF_STATUS0);
2067 uint32_t cfg1 = sys_read32(config->base + CONF_STATUS1);
2068
2069 data->hw_cfg.cmdr_mem_depth = CONF_STATUS0_CMDR_DEPTH(cfg0) * 4;
2070 data->hw_cfg.cmd_mem_depth = CONF_STATUS1_CMD_DEPTH(cfg1) * 4;
2071 data->hw_cfg.rx_mem_depth = CONF_STATUS1_RX_DEPTH(cfg1) * 4;
2072 data->hw_cfg.tx_mem_depth = CONF_STATUS1_TX_DEPTH(cfg1) * 4;
2073 data->hw_cfg.ibir_mem_depth = CONF_STATUS0_IBIR_DEPTH(cfg0) * 4;
2074
2075 LOG_DBG("%s: FIFO info:\r\n"
2076 " cmd_mem_depth = %u\r\n"
2077 " cmdr_mem_depth = %u\r\n"
2078 " rx_mem_depth = %u\r\n"
2079 " tx_mem_depth = %u\r\n"
2080 " ibir_mem_depth = %u",
2081 dev->name, data->hw_cfg.cmd_mem_depth, data->hw_cfg.cmdr_mem_depth,
2082 data->hw_cfg.rx_mem_depth, data->hw_cfg.tx_mem_depth, data->hw_cfg.ibir_mem_depth);
2083
2084 /* Regardless of the cmd depth size we are limited by our cmd array length. */
2085 data->hw_cfg.cmd_mem_depth = MIN(data->hw_cfg.cmd_mem_depth, ARRAY_SIZE(data->xfer.cmds));
2086 }
2087
2088 /**
2089 * @brief Get configuration of the I3C hardware.
2090 *
2091 * This provides a way to get the current configuration of the I3C hardware.
2092 *
2093 * This can return cached config or probed hardware parameters, but it has to
2094 * be up to date with current configuration.
2095 *
2096 * @param[in] dev Pointer to controller device driver instance.
2097 * @param[in] type Type of configuration parameters being passed
2098 * in @p config.
2099 * @param[in,out] config Pointer to the configuration parameters.
2100 *
2101 * Note that if @p type is @c I3C_CONFIG_CUSTOM, @p config must contain
2102 * the ID of the parameter to be retrieved.
2103 *
2104 * @retval 0 If successful.
2105 * @retval -EIO General Input/Output errors.
2106 * @retval -ENOSYS If not implemented.
2107 */
cdns_i3c_config_get(const struct device * dev,enum i3c_config_type type,void * config)2108 static int cdns_i3c_config_get(const struct device *dev, enum i3c_config_type type, void *config)
2109 {
2110 struct cdns_i3c_data *data = dev->data;
2111 int ret = 0;
2112
2113 if (config == NULL) {
2114 ret = -EINVAL;
2115 goto out_configure;
2116 }
2117
2118 (void)memcpy(config, &data->common.ctrl_config, sizeof(data->common.ctrl_config));
2119
2120 out_configure:
2121 return ret;
2122 }
2123
2124 /**
2125 * @brief Writes to the Target's TX FIFO
2126 *
2127 * The Cadence I3C will then ACK read requests to it's TX FIFO from a
2128 * Controller
2129 *
2130 * @param dev Pointer to the device structure for an I3C controller
2131 * driver configured in target mode.
2132 * @param buf Pointer to the buffer
2133 * @param len Length of the buffer
2134 *
2135 * @retval Total number of bytes written
2136 * @retval -EACCES Not in Target Mode
2137 * @retval -ENOSPC No space in Tx FIFO
2138 */
cdns_i3c_target_tx_write(const struct device * dev,uint8_t * buf,uint16_t len)2139 static int cdns_i3c_target_tx_write(const struct device *dev, uint8_t *buf, uint16_t len)
2140 {
2141 const struct cdns_i3c_config *config = dev->config;
2142 struct cdns_i3c_data *data = dev->data;
2143
2144 /* check if we are currently a target */
2145 if (sys_read32(config->base + MST_STATUS0) & MST_STATUS0_MASTER_MODE) {
2146 return -EACCES;
2147 }
2148
2149 /* check if there is space available in the tx fifo */
2150 if (sys_read32(config->base + SLV_STATUS1) & SLV_STATUS1_SDR_TX_FULL) {
2151 return -ENOSPC;
2152 }
2153
2154 k_mutex_lock(&data->bus_lock, K_FOREVER);
2155
2156 /* write as much as you can to the fifo */
2157 uint16_t i;
2158
2159 for (i = 0;
2160 i < len && (!(sys_read32(config->base + SLV_STATUS1) & SLV_STATUS1_SDR_TX_FULL));
2161 i++) {
2162 sys_write32((uint32_t)buf[i], config->base + TX_FIFO);
2163 }
2164
2165 /* setup THR interrupt */
2166 uint32_t thr_ctrl = sys_read32(config->base + TX_RX_THR_CTRL);
2167
2168 /*
2169 * Interrupt at half of the data or FIFO depth to give it enough time to be
2170 * processed. The ISR will then callback to the function pointer
2171 * `read_processed_cb` to collect more data to transmit
2172 */
2173 thr_ctrl &= ~TX_THR_MASK;
2174 thr_ctrl |= TX_THR(MIN((data->hw_cfg.tx_mem_depth / 4) / 2, i / 2));
2175 sys_write32(thr_ctrl, config->base + TX_RX_THR_CTRL);
2176
2177 k_mutex_unlock(&data->bus_lock);
2178
2179 /* return total bytes written */
2180 return i;
2181 }
2182
2183 /**
2184 * @brief Instructs the I3C Target device to register itself to the I3C Controller
2185 *
2186 * This routine instructs the I3C Target device to register itself to the I3C
2187 * Controller via its parent controller's i3c_target_register() API.
2188 *
2189 * @param dev Pointer to target device driver instance.
2190 * @param cfg Config struct with functions and parameters used by the I3C driver
2191 * to send bus events
2192 *
2193 * @return @see i3c_device_find.
2194 */
cdns_i3c_target_register(const struct device * dev,struct i3c_target_config * cfg)2195 static int cdns_i3c_target_register(const struct device *dev, struct i3c_target_config *cfg)
2196 {
2197 struct cdns_i3c_data *data = dev->data;
2198
2199 data->target_config = cfg;
2200 return 0;
2201 }
2202
2203 /**
2204 * @brief Unregisters the provided config as Target device
2205 *
2206 * This routine disables I3C target mode for the 'dev' I3C bus driver using
2207 * the provided 'config' struct containing the functions and parameters
2208 * to send bus events.
2209 *
2210 * @param dev Pointer to target device driver instance.
2211 * @param cfg Config struct with functions and parameters used by the I3C driver
2212 * to send bus events
2213 *
2214 * @return @see i3c_device_find.
2215 */
cdns_i3c_target_unregister(const struct device * dev,struct i3c_target_config * cfg)2216 static int cdns_i3c_target_unregister(const struct device *dev, struct i3c_target_config *cfg)
2217 {
2218 /* no way to disable? maybe write DA to 0? */
2219 return 0;
2220 }
2221
2222 /**
2223 * @brief Find a registered I3C target device.
2224 *
2225 * This returns the I3C device descriptor of the I3C device
2226 * matching the incoming @p id.
2227 *
2228 * @param dev Pointer to controller device driver instance.
2229 * @param id Pointer to I3C device ID.
2230 *
2231 * @return @see i3c_device_find.
2232 */
cdns_i3c_device_find(const struct device * dev,const struct i3c_device_id * id)2233 static struct i3c_device_desc *cdns_i3c_device_find(const struct device *dev,
2234 const struct i3c_device_id *id)
2235 {
2236 const struct cdns_i3c_config *config = dev->config;
2237
2238 return i3c_dev_list_find(&config->common.dev_list, id);
2239 }
2240
2241 /**
2242 * Find a registered I2C target device.
2243 *
2244 * Controller only API.
2245 *
2246 * This returns the I2C device descriptor of the I2C device
2247 * matching the device address @p addr.
2248 *
2249 * @param dev Pointer to controller device driver instance.
2250 * @param id I2C target device address.
2251 *
2252 * @return @see i3c_i2c_device_find.
2253 */
cdns_i3c_i2c_device_find(const struct device * dev,uint16_t addr)2254 static struct i3c_i2c_device_desc *cdns_i3c_i2c_device_find(const struct device *dev, uint16_t addr)
2255 {
2256 struct cdns_i3c_data *data = dev->data;
2257
2258 return i3c_dev_list_i2c_addr_find(&data->common.attached_dev, addr);
2259 }
2260
2261 /**
2262 * @brief Transfer messages in I2C mode.
2263 *
2264 * @see i2c_transfer
2265 *
2266 * @param dev Pointer to device driver instance.
2267 * @param target Pointer to target device descriptor.
2268 * @param msgs Pointer to I2C messages.
2269 * @param num_msgs Number of messages to transfers.
2270 *
2271 * @return @see i2c_transfer
2272 */
cdns_i3c_i2c_api_transfer(const struct device * dev,struct i2c_msg * msgs,uint8_t num_msgs,uint16_t addr)2273 static int cdns_i3c_i2c_api_transfer(const struct device *dev, struct i2c_msg *msgs,
2274 uint8_t num_msgs, uint16_t addr)
2275 {
2276 struct i3c_i2c_device_desc *i2c_dev = cdns_i3c_i2c_device_find(dev, addr);
2277 int ret;
2278
2279 if (i2c_dev == NULL) {
2280 ret = -ENODEV;
2281 } else {
2282 ret = cdns_i3c_i2c_transfer(dev, i2c_dev, msgs, num_msgs);
2283 }
2284
2285 return ret;
2286 }
2287
2288 /**
2289 * Determine I3C bus mode from the i2c devices on the bus
2290 *
2291 * Reads the LVR of all I2C devices and returns the I3C bus
2292 * Mode
2293 *
2294 * @param dev_list Pointer to device list
2295 *
2296 * @return @see enum i3c_bus_mode.
2297 */
i3c_bus_mode(const struct i3c_dev_list * dev_list)2298 static enum i3c_bus_mode i3c_bus_mode(const struct i3c_dev_list *dev_list)
2299 {
2300 enum i3c_bus_mode mode = I3C_BUS_MODE_PURE;
2301
2302 for (int i = 0; i < dev_list->num_i2c; i++) {
2303 switch (I3C_DCR_I2C_DEV_IDX(dev_list->i2c[i].lvr)) {
2304 case I3C_DCR_I2C_DEV_IDX_0:
2305 if (mode < I3C_BUS_MODE_MIXED_FAST) {
2306 mode = I3C_BUS_MODE_MIXED_FAST;
2307 }
2308 break;
2309 case I3C_DCR_I2C_DEV_IDX_1:
2310 if (mode < I3C_BUS_MODE_MIXED_LIMITED) {
2311 mode = I3C_BUS_MODE_MIXED_LIMITED;
2312 }
2313 break;
2314 case I3C_DCR_I2C_DEV_IDX_2:
2315 if (mode < I3C_BUS_MODE_MIXED_SLOW) {
2316 mode = I3C_BUS_MODE_MIXED_SLOW;
2317 }
2318 break;
2319 default:
2320 mode = I3C_BUS_MODE_INVALID;
2321 break;
2322 }
2323 }
2324 return mode;
2325 }
2326
2327 /**
2328 * Determine THD_DEL value for CTRL register
2329 *
2330 * @param dev Pointer to device driver instance.
2331 *
2332 * @return Value to be written to THD_DEL
2333 */
cdns_i3c_clk_to_data_turnaround(const struct device * dev)2334 static uint8_t cdns_i3c_clk_to_data_turnaround(const struct device *dev)
2335 {
2336 const struct cdns_i3c_config *config = dev->config;
2337 uint32_t input_clock_frequency = config->input_frequency;
2338 uint8_t thd_delay =
2339 DIV_ROUND_UP(I3C_TSCO_DEFAULT_NS, (NSEC_PER_SEC / input_clock_frequency));
2340
2341 if (thd_delay > THD_DELAY_MAX) {
2342 thd_delay = THD_DELAY_MAX;
2343 }
2344
2345 return (THD_DELAY_MAX - thd_delay);
2346 }
2347
2348 /**
2349 * @brief Initialize the hardware.
2350 *
2351 * @param dev Pointer to controller device driver instance.
2352 */
cdns_i3c_bus_init(const struct device * dev)2353 static int cdns_i3c_bus_init(const struct device *dev)
2354 {
2355 struct cdns_i3c_data *data = dev->data;
2356 const struct cdns_i3c_config *config = dev->config;
2357 struct i3c_config_controller *ctrl_config = &data->common.ctrl_config;
2358
2359 /* Clear all retaining regs */
2360 sys_write32(DEVS_CTRL_DEV_CLR_ALL, config->base + DEVS_CTRL);
2361
2362 uint32_t conf0 = sys_read32(config->base + CONF_STATUS0);
2363
2364 data->max_devs = CONF_STATUS0_DEVS_NUM(conf0);
2365 data->free_rr_slots = GENMASK(data->max_devs, 1);
2366 ctrl_config->is_secondary = (conf0 & CONF_STATUS0_SEC_MASTER) ? true : false;
2367 ctrl_config->supported_hdr = (conf0 & CONF_STATUS0_SUPPORTS_DDR) ? I3C_MSG_HDR_DDR : 0;
2368
2369 k_mutex_init(&data->bus_lock);
2370 k_sem_init(&data->xfer.complete, 0, 1);
2371 k_sem_init(&data->ibi_hj_complete, 0, 1);
2372
2373 cdns_i3c_interrupts_disable(config);
2374 cdns_i3c_interrupts_clear(config);
2375
2376 config->irq_config_func(dev);
2377
2378 /* Ensure the bus is disabled. */
2379 sys_write32(~CTRL_DEV_EN & sys_read32(config->base + CTRL), config->base + CTRL);
2380
2381 cdns_i3c_read_hw_cfg(dev);
2382
2383 /* determine prescaler timings for i3c and i2c scl */
2384 cdns_i3c_set_prescalers(dev);
2385
2386 enum i3c_bus_mode mode = i3c_bus_mode(&config->common.dev_list);
2387
2388 LOG_DBG("%s: i3c bus mode %d", dev->name, mode);
2389 int cdns_mode;
2390
2391 switch (mode) {
2392 case I3C_BUS_MODE_PURE:
2393 cdns_mode = CTRL_PURE_BUS_MODE;
2394 break;
2395 case I3C_BUS_MODE_MIXED_FAST:
2396 cdns_mode = CTRL_MIXED_FAST_BUS_MODE;
2397 break;
2398 case I3C_BUS_MODE_MIXED_LIMITED:
2399 case I3C_BUS_MODE_MIXED_SLOW:
2400 cdns_mode = CTRL_MIXED_SLOW_BUS_MODE;
2401 break;
2402 default:
2403 return -EINVAL;
2404 }
2405
2406 /*
2407 * When a Hot-Join request happens, disable all events coming from this device.
2408 * We will issue ENTDAA afterwards from the threaded IRQ handler.
2409 * Set HJ ACK later after bus init to prevent targets from indirect DAA enforcement.
2410 *
2411 * Set the I3C Bus Mode based on the LVR of the I2C devices
2412 */
2413 uint32_t ctrl = CTRL_HJ_DISEC | CTRL_MCS_EN | (CTRL_BUS_MODE_MASK & cdns_mode) |
2414 CTRL_THD_DELAY(cdns_i3c_clk_to_data_turnaround(dev));
2415 /* Disable Controllership requests as it is not supported yet by the driver */
2416 ctrl &= ~CTRL_MST_ACK;
2417
2418 /*
2419 * Cadence I3C release r105v1p0 and above support I3C v1.1 timing change
2420 * for tCASHr_min = tCAS_min / 2, otherwise tCASr_min = tCAS_min (as
2421 * per MIPI spec v1.0)
2422 */
2423 uint32_t rev_id = sys_read32(config->base + REV_ID);
2424
2425 if (REV_ID_REV(rev_id) >= REV_ID_VERSION(1, 5)) {
2426 ctrl |= CTRL_I3C_11_SUPP;
2427 }
2428
2429 /* write ctrl register value */
2430 sys_write32(ctrl, config->base + CTRL);
2431
2432 /* enable Core */
2433 sys_write32(CTRL_DEV_EN | ctrl, config->base + CTRL);
2434
2435 /* Set fifo thresholds. */
2436 sys_write32(CMD_THR(I3C_CMDD_THR) | IBI_THR(I3C_IBID_THR) | CMDR_THR(I3C_CMDR_THR) |
2437 IBIR_THR(I3C_IBIR_THR),
2438 config->base + CMD_IBI_THR_CTRL);
2439
2440 /* Set TX/RX interrupt thresholds. */
2441 if (sys_read32(config->base + MST_STATUS0) & MST_STATUS0_MASTER_MODE) {
2442 sys_write32(TX_THR(I3C_TX_THR) | RX_THR(data->hw_cfg.rx_mem_depth),
2443 config->base + TX_RX_THR_CTRL);
2444 } else {
2445 sys_write32(TX_THR(1) | RX_THR(1), config->base + TX_RX_THR_CTRL);
2446 }
2447
2448 /* enable target interrupts */
2449 sys_write32(SLV_INT_DA_UPD | SLV_INT_SDR_RD_COMP | SLV_INT_SDR_WR_COMP |
2450 SLV_INT_SDR_RX_THR | SLV_INT_SDR_TX_THR | SLV_INT_SDR_RX_UNF |
2451 SLV_INT_SDR_TX_OVF | SLV_INT_HJ_DONE,
2452 config->base + SLV_IER);
2453
2454 /* Enable IBI interrupts. */
2455 sys_write32(MST_INT_IBIR_THR | MST_INT_RX_UNF | MST_INT_HALTED | MST_INT_TX_OVF,
2456 config->base + MST_IER);
2457
2458 int ret = i3c_addr_slots_init(dev);
2459
2460 if (ret != 0) {
2461 return ret;
2462 }
2463
2464 /* Program retaining regs. */
2465 cdns_i3c_program_controller_retaining_reg(dev);
2466
2467 /* only primary controllers are responsible for initializing the bus */
2468 if (!ctrl_config->is_secondary) {
2469 /* Perform bus initialization */
2470 ret = i3c_bus_init(dev, &config->common.dev_list);
2471 #ifdef CONFIG_I3C_USE_IBI
2472 /* Bus Initialization Complete, allow HJ ACKs */
2473 sys_write32(CTRL_HJ_ACK | sys_read32(config->base + CTRL), config->base + CTRL);
2474 #endif
2475 }
2476
2477 return 0;
2478 }
2479
2480 static struct i3c_driver_api api = {
2481 .i2c_api.configure = cdns_i3c_i2c_api_configure,
2482 .i2c_api.transfer = cdns_i3c_i2c_api_transfer,
2483
2484 .configure = cdns_i3c_configure,
2485 .config_get = cdns_i3c_config_get,
2486
2487 .attach_i3c_device = cdns_i3c_attach_device,
2488 .reattach_i3c_device = cdns_i3c_reattach_device,
2489 .detach_i3c_device = cdns_i3c_detach_device,
2490 .attach_i2c_device = cdns_i3c_i2c_attach_device,
2491 .detach_i2c_device = cdns_i3c_i2c_detach_device,
2492
2493 .do_daa = cdns_i3c_do_daa,
2494 .do_ccc = cdns_i3c_do_ccc,
2495
2496 .i3c_device_find = cdns_i3c_device_find,
2497
2498 .i3c_xfers = cdns_i3c_transfer,
2499
2500 .target_tx_write = cdns_i3c_target_tx_write,
2501 .target_register = cdns_i3c_target_register,
2502 .target_unregister = cdns_i3c_target_unregister,
2503
2504 #ifdef CONFIG_I3C_USE_IBI
2505 .ibi_enable = cdns_i3c_controller_ibi_enable,
2506 .ibi_disable = cdns_i3c_controller_ibi_disable,
2507 .ibi_raise = cdns_i3c_target_ibi_raise,
2508 #endif
2509 };
2510
2511 #define CADENCE_I3C_INSTANTIATE(n) \
2512 static void cdns_i3c_config_func_##n(const struct device *dev); \
2513 static struct i3c_device_desc cdns_i3c_device_array_##n[] = I3C_DEVICE_ARRAY_DT_INST(n); \
2514 static struct i3c_i2c_device_desc cdns_i3c_i2c_device_array_##n[] = \
2515 I3C_I2C_DEVICE_ARRAY_DT_INST(n); \
2516 static const struct cdns_i3c_config i3c_config_##n = { \
2517 .base = DT_INST_REG_ADDR(n), \
2518 .input_frequency = DT_INST_PROP(n, input_clock_frequency), \
2519 .irq_config_func = cdns_i3c_config_func_##n, \
2520 .common.dev_list.i3c = cdns_i3c_device_array_##n, \
2521 .common.dev_list.num_i3c = ARRAY_SIZE(cdns_i3c_device_array_##n), \
2522 .common.dev_list.i2c = cdns_i3c_i2c_device_array_##n, \
2523 .common.dev_list.num_i2c = ARRAY_SIZE(cdns_i3c_i2c_device_array_##n), \
2524 }; \
2525 static struct cdns_i3c_data i3c_data_##n = { \
2526 .common.ctrl_config.scl.i3c = DT_INST_PROP_OR(n, i3c_scl_hz, 0), \
2527 .common.ctrl_config.scl.i2c = DT_INST_PROP_OR(n, i2c_scl_hz, 0), \
2528 }; \
2529 DEVICE_DT_INST_DEFINE(n, cdns_i3c_bus_init, NULL, &i3c_data_##n, &i3c_config_##n, \
2530 POST_KERNEL, CONFIG_I3C_CONTROLLER_INIT_PRIORITY, &api); \
2531 static void cdns_i3c_config_func_##n(const struct device *dev) \
2532 { \
2533 IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), cdns_i3c_irq_handler, \
2534 DEVICE_DT_INST_GET(n), 0); \
2535 irq_enable(DT_INST_IRQN(n)); \
2536 };
2537
2538 #define DT_DRV_COMPAT cdns_i3c
2539 DT_INST_FOREACH_STATUS_OKAY(CADENCE_I3C_INSTANTIATE)
2540