1 /* 2 * Copyright (c) 2017 IpTronix S.r.l. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_DRIVERS_SENSOR_ADXL362_ADXL362_H_ 8 #define ZEPHYR_DRIVERS_SENSOR_ADXL362_ADXL362_H_ 9 10 #include <zephyr/types.h> 11 #include <zephyr/device.h> 12 #include <zephyr/drivers/gpio.h> 13 #include <zephyr/drivers/spi.h> 14 15 #define ADXL362_SLAVE_ID 1 16 17 /* ADXL362 communication commands */ 18 #define ADXL362_WRITE_REG 0x0A 19 #define ADXL362_READ_REG 0x0B 20 #define ADXL362_WRITE_FIFO 0x0D 21 22 /* Registers */ 23 #define ADXL362_REG_DEVID_AD 0x00 24 #define ADXL362_REG_DEVID_MST 0x01 25 #define ADXL362_REG_PARTID 0x02 26 #define ADXL362_REG_REVID 0x03 27 #define ADXL362_REG_XDATA 0x08 28 #define ADXL362_REG_YDATA 0x09 29 #define ADXL362_REG_ZDATA 0x0A 30 #define ADXL362_REG_STATUS 0x0B 31 #define ADXL362_REG_FIFO_L 0x0C 32 #define ADXL362_REG_FIFO_H 0x0D 33 #define ADXL362_REG_XDATA_L 0x0E 34 #define ADXL362_REG_XDATA_H 0x0F 35 #define ADXL362_REG_YDATA_L 0x10 36 #define ADXL362_REG_YDATA_H 0x11 37 #define ADXL362_REG_ZDATA_L 0x12 38 #define ADXL362_REG_ZDATA_H 0x13 39 #define ADXL362_REG_TEMP_L 0x14 40 #define ADXL362_REG_TEMP_H 0x15 41 #define ADXL362_REG_SOFT_RESET 0x1F 42 #define ADXL362_REG_THRESH_ACT_L 0x20 43 #define ADXL362_REG_THRESH_ACT_H 0x21 44 #define ADXL362_REG_TIME_ACT 0x22 45 #define ADXL362_REG_THRESH_INACT_L 0x23 46 #define ADXL362_REG_THRESH_INACT_H 0x24 47 #define ADXL362_REG_TIME_INACT_L 0x25 48 #define ADXL362_REG_TIME_INACT_H 0x26 49 #define ADXL362_REG_ACT_INACT_CTL 0x27 50 #define ADXL362_REG_FIFO_CTL 0x28 51 #define ADXL362_REG_FIFO_SAMPLES 0x29 52 #define ADXL362_REG_INTMAP1 0x2A 53 #define ADXL362_REG_INTMAP2 0x2B 54 #define ADXL362_REG_FILTER_CTL 0x2C 55 #define ADXL362_REG_POWER_CTL 0x2D 56 #define ADXL362_REG_SELF_TEST 0x2E 57 58 /* ADXL362_REG_STATUS definitions */ 59 #define ADXL362_STATUS_ERR_USER_REGS (1 << 7) 60 #define ADXL362_STATUS_AWAKE (1 << 6) 61 #define ADXL362_STATUS_INACT (1 << 5) 62 #define ADXL362_STATUS_ACT (1 << 4) 63 #define ADXL362_STATUS_FIFO_OVERRUN (1 << 3) 64 #define ADXL362_STATUS_FIFO_WATERMARK (1 << 2) 65 #define ADXL362_STATUS_FIFO_RDY (1 << 1) 66 #define ADXL362_STATUS_DATA_RDY (1 << 0) 67 68 /* ADXL362_REG_ACT_INACT_CTL definitions */ 69 #define ADXL362_ACT_INACT_CTL_LINKLOOP(x) (((x) & 0x3) << 4) 70 #define ADXL362_ACT_INACT_CTL_INACT_REF (1 << 3) 71 #define ADXL362_ACT_INACT_CTL_INACT_EN (1 << 2) 72 #define ADXL362_ACT_INACT_CTL_ACT_REF (1 << 1) 73 #define ADXL362_ACT_INACT_CTL_ACT_EN (1 << 0) 74 75 /* ADXL362_ACT_INACT_CTL_LINKLOOP(x) options */ 76 #define ADXL362_MODE_DEFAULT 0 77 #define ADXL362_MODE_LINK 1 78 #define ADXL362_MODE_LOOP 3 79 80 /* ADXL362_REG_FIFO_CTL */ 81 #define ADXL362_FIFO_CTL_AH (1 << 3) 82 #define ADXL362_FIFO_CTL_FIFO_TEMP (1 << 2) 83 #define ADXL362_FIFO_CTL_FIFO_MODE(x) (((x) & 0x3) << 0) 84 85 /* ADXL362_FIFO_CTL_FIFO_MODE(x) options */ 86 #define ADXL362_FIFO_DISABLE 0 87 #define ADXL362_FIFO_OLDEST_SAVED 1 88 #define ADXL362_FIFO_STREAM 2 89 #define ADXL362_FIFO_TRIGGERED 3 90 91 /* ADXL362_REG_INTMAP1 */ 92 #define ADXL362_INTMAP1_INT_LOW (1 << 7) 93 #define ADXL362_INTMAP1_AWAKE (1 << 6) 94 #define ADXL362_INTMAP1_INACT (1 << 5) 95 #define ADXL362_INTMAP1_ACT (1 << 4) 96 #define ADXL362_INTMAP1_FIFO_OVERRUN (1 << 3) 97 #define ADXL362_INTMAP1_FIFO_WATERMARK (1 << 2) 98 #define ADXL362_INTMAP1_FIFO_READY (1 << 1) 99 #define ADXL362_INTMAP1_DATA_READY (1 << 0) 100 101 /* ADXL362_REG_INTMAP2 definitions */ 102 #define ADXL362_INTMAP2_INT_LOW (1 << 7) 103 #define ADXL362_INTMAP2_AWAKE (1 << 6) 104 #define ADXL362_INTMAP2_INACT (1 << 5) 105 #define ADXL362_INTMAP2_ACT (1 << 4) 106 #define ADXL362_INTMAP2_FIFO_OVERRUN (1 << 3) 107 #define ADXL362_INTMAP2_FIFO_WATERMARK (1 << 2) 108 #define ADXL362_INTMAP2_FIFO_READY (1 << 1) 109 #define ADXL362_INTMAP2_DATA_READY (1 << 0) 110 111 /* ADXL362_REG_FILTER_CTL definitions */ 112 #define ADXL362_FILTER_CTL_RANGE(x) (((x) & 0x3) << 6) 113 #define ADXL362_FILTER_CTL_RES (1 << 5) 114 #define ADXL362_FILTER_CTL_HALF_BW (1 << 4) 115 #define ADXL362_FILTER_CTL_EXT_SAMPLE (1 << 3) 116 #define ADXL362_FILTER_CTL_ODR(x) (((x) & 0x7) << 0) 117 118 /* ADXL362_FILTER_CTL_RANGE(x) options */ 119 #define ADXL362_RANGE_2G 0 /* +/-2 g */ 120 #define ADXL362_RANGE_4G 1 /* +/-4 g */ 121 #define ADXL362_RANGE_8G 2 /* +/-8 g */ 122 123 /* ADXL362_FILTER_CTL_ODR(x) options */ 124 #define ADXL362_ODR_12_5_HZ 0 /* 12.5 Hz */ 125 #define ADXL362_ODR_25_HZ 1 /* 25 Hz */ 126 #define ADXL362_ODR_50_HZ 2 /* 50 Hz */ 127 #define ADXL362_ODR_100_HZ 3 /* 100 Hz */ 128 #define ADXL362_ODR_200_HZ 4 /* 200 Hz */ 129 #define ADXL362_ODR_400_HZ 5 /* 400 Hz */ 130 131 /* ADXL362_REG_POWER_CTL definitions */ 132 #define ADXL362_POWER_CTL_RES (1 << 7) 133 #define ADXL362_POWER_CTL_EXT_CLK (1 << 6) 134 #define ADXL362_POWER_CTL_LOW_NOISE(x) (((x) & 0x3) << 4) 135 #define ADXL362_POWER_CTL_WAKEUP (1 << 3) 136 #define ADXL362_POWER_CTL_AUTOSLEEP (1 << 2) 137 #define ADXL362_POWER_CTL_MEASURE(x) (((x) & 0x3) << 0) 138 139 /* ADXL362_POWER_CTL_LOW_NOISE(x) options */ 140 #define ADXL362_NOISE_MODE_NORMAL 0 141 #define ADXL362_NOISE_MODE_LOW 1 142 #define ADXL362_NOISE_MODE_ULTRALOW 2 143 144 /* ADXL362_POWER_CTL_MEASURE(x) options */ 145 #define ADXL362_MEASURE_STANDBY 0 146 #define ADXL362_MEASURE_ON 2 147 148 /* ADXL362_REG_SELF_TEST */ 149 #define ADXL362_SELF_TEST_ST (1 << 0) 150 151 /* ADXL362 device information */ 152 #define ADXL362_DEVICE_AD 0xAD 153 #define ADXL362_DEVICE_MST 0x1D 154 #define ADXL362_PART_ID 0xF2 155 156 /* ADXL362 Reset settings */ 157 #define ADXL362_RESET_KEY 0x52 158 159 /* ADXL362 Status check */ 160 #define ADXL362_STATUS_CHECK_DATA_READY(x) (((x) >> 0) & 0x1) 161 #define ADXL362_STATUS_CHECK_INACT(x) (((x) >> 5) & 0x1) 162 #define ADXL362_STATUS_CHECK_ACTIVITY(x) (((x) >> 4) & 0x1) 163 164 /* ADXL362 scale factors from specifications */ 165 #define ADXL362_ACCEL_2G_LSB_PER_G 1000 166 #define ADXL362_ACCEL_4G_LSB_PER_G 500 167 #define ADXL362_ACCEL_8G_LSB_PER_G 235 168 169 /* ADXL362 temperature sensor specifications */ 170 #define ADXL362_TEMP_MC_PER_LSB 65 171 #define ADXL362_TEMP_BIAS_LSB 350 172 173 struct adxl362_config { 174 struct spi_dt_spec bus; 175 #if defined(CONFIG_ADXL362_TRIGGER) 176 struct gpio_dt_spec interrupt; 177 uint8_t int1_config; 178 uint8_t int2_config; 179 #endif 180 uint8_t power_ctl; 181 }; 182 183 struct adxl362_data { 184 union { 185 int16_t acc_xyz[3]; 186 struct { 187 int16_t acc_x; 188 int16_t acc_y; 189 int16_t acc_z; 190 }; 191 } __packed; 192 int16_t temp; 193 uint8_t selected_range; 194 195 #if defined(CONFIG_ADXL362_TRIGGER) 196 const struct device *dev; 197 struct gpio_callback gpio_cb; 198 struct k_mutex trigger_mutex; 199 200 sensor_trigger_handler_t inact_handler; 201 const struct sensor_trigger *inact_trigger; 202 sensor_trigger_handler_t act_handler; 203 const struct sensor_trigger *act_trigger; 204 sensor_trigger_handler_t drdy_handler; 205 const struct sensor_trigger *drdy_trigger; 206 207 #if defined(CONFIG_ADXL362_TRIGGER_OWN_THREAD) 208 K_KERNEL_STACK_MEMBER(thread_stack, CONFIG_ADXL362_THREAD_STACK_SIZE); 209 struct k_sem gpio_sem; 210 struct k_thread thread; 211 #elif defined(CONFIG_ADXL362_TRIGGER_GLOBAL_THREAD) 212 struct k_work work; 213 #endif 214 #endif /* CONFIG_ADXL362_TRIGGER */ 215 }; 216 217 #if defined(CONFIG_ADXL362_ACCEL_RANGE_RUNTIME) ||\ 218 defined(CONFIG_ADXL362_ACCEL_RANGE_2G) 219 # define ADXL362_DEFAULT_RANGE_ACC ADXL362_RANGE_2G 220 #elif defined(CONFIG_ADXL362_ACCEL_RANGE_4G) 221 # define ADXL362_DEFAULT_RANGE_ACC ADXL362_RANGE_4G 222 #else 223 # define ADXL362_DEFAULT_RANGE_ACC ADXL362_RANGE_8G 224 #endif 225 226 #if defined(CONFIG_ADXL362_ACCEL_ODR_RUNTIME) ||\ 227 defined(CONFIG_ADXL362_ACCEL_ODR_12_5) 228 # define ADXL362_DEFAULT_ODR_ACC ADXL362_ODR_12_5_HZ 229 #elif defined(CONFIG_ADXL362_ACCEL_ODR_25) 230 # define ADXL362_DEFAULT_ODR_ACC ADXL362_ODR_25_HZ 231 #elif defined(CONFIG_ADXL362_ACCEL_ODR_50) 232 # define ADXL362_DEFAULT_ODR_ACC ADXL362_ODR_50_HZ 233 #elif defined(CONFIG_ADXL362_ACCEL_ODR_100) 234 # define ADXL362_DEFAULT_ODR_ACC ADXL362_ODR_100_HZ 235 #elif defined(CONFIG_ADXL362_ACCEL_ODR_200) 236 # define ADXL362_DEFAULT_ODR_ACC ADXL362_ODR_200_HZ 237 #else 238 # define ADXL362_DEFAULT_ODR_ACC ADXL362_ODR_400_HZ 239 #endif 240 241 #ifdef CONFIG_ADXL362_TRIGGER 242 int adxl362_reg_write_mask(const struct device *dev, 243 uint8_t reg_addr, uint8_t mask, uint8_t data); 244 245 int adxl362_get_status(const struct device *dev, uint8_t *status); 246 247 int adxl362_interrupt_activity_enable(const struct device *dev); 248 249 int adxl362_trigger_set(const struct device *dev, 250 const struct sensor_trigger *trig, 251 sensor_trigger_handler_t handler); 252 253 int adxl362_init_interrupt(const struct device *dev); 254 255 int adxl362_set_interrupt_mode(const struct device *dev, uint8_t mode); 256 257 int adxl362_clear_data_ready(const struct device *dev); 258 #endif /* CONFIG_ADT7420_TRIGGER */ 259 260 #endif /* ZEPHYR_DRIVERS_SENSOR_ADXL362_ADXL362_H_ */ 261
