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/Zephyr-Core-3.4.0/include/zephyr/dt-bindings/clock/
Dstm32h5_clock.h71 #define STM32_CLOCK(val, mask, shift, reg) \ argument
75 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
89 #define USART1_SEL(val) STM32_CLOCK(val, 7, 0, CCIPR1_REG) argument
90 #define USART2_SEL(val) STM32_CLOCK(val, 7, 3, CCIPR1_REG) argument
91 #define USART3_SEL(val) STM32_CLOCK(val, 7, 6, CCIPR1_REG) argument
92 #define USART4_SEL(val) STM32_CLOCK(val, 7, 9, CCIPR1_REG) argument
93 #define USART5_SEL(val) STM32_CLOCK(val, 7, 12, CCIPR1_REG) argument
94 #define USART6_SEL(val) STM32_CLOCK(val, 7, 15, CCIPR1_REG) argument
95 #define USART7_SEL(val) STM32_CLOCK(val, 7, 18, CCIPR1_REG) argument
96 #define USART8_SEL(val) STM32_CLOCK(val, 7, 21, CCIPR1_REG) argument
[all …]
Dstm32u5_clock.h71 #define STM32_CLOCK(val, mask, shift, reg) \ argument
75 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
87 #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR1_REG) argument
88 #define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR1_REG) argument
89 #define USART3_SEL(val) STM32_CLOCK(val, 3, 4, CCIPR1_REG) argument
90 #define USART4_SEL(val) STM32_CLOCK(val, 3, 6, CCIPR1_REG) argument
91 #define USART5_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR1_REG) argument
92 #define I2C1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR1_REG) argument
93 #define I2C2_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR1_REG) argument
94 #define I2C4_SEL(val) STM32_CLOCK(val, 3, 14, CCIPR1_REG) argument
[all …]
Dstm32h7_clock.h80 #define STM32_CLOCK(val, mask, shift, reg) \ argument
84 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
97 #define FMC_SEL(val) STM32_CLOCK(val, 3, 0, D1CCIPR_REG) argument
98 #define QSPI_SEL(val) STM32_CLOCK(val, 3, 4, D1CCIPR_REG) argument
99 #define DSI_SEL(val) STM32_CLOCK(val, 1, 8, D1CCIPR_REG) argument
100 #define SDMMC_SEL(val) STM32_CLOCK(val, 1, 16, D1CCIPR_REG) argument
101 #define CKPER_SEL(val) STM32_CLOCK(val, 3, 28, D1CCIPR_REG) argument
103 #define OSPI_SEL(val) STM32_CLOCK(val, 3, 4, D1CCIPR_REG) argument
105 #define SAI1_SEL(val) STM32_CLOCK(val, 7, 0, D2CCIP1R_REG) argument
106 #define SAI23_SEL(val) STM32_CLOCK(val, 7, 6, D2CCIP1R_REG) argument
[all …]
Dstm32l4_clock.h61 #define STM32_CLOCK(val, mask, shift, reg) \ argument
65 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
76 #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG) argument
77 #define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR_REG) argument
78 #define USART3_SEL(val) STM32_CLOCK(val, 3, 4, CCIPR_REG) argument
79 #define UART4_SEL(val) STM32_CLOCK(val, 3, 6, CCIPR_REG) argument
80 #define UART5_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR_REG) argument
81 #define LPUART1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR_REG) argument
82 #define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG) argument
83 #define I2C2_SEL(val) STM32_CLOCK(val, 3, 14, CCIPR_REG) argument
[all …]
Dstm32f7_clock.h61 #define STM32_CLOCK(val, mask, shift, reg) \ argument
65 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
75 #define I2S_SEL(val) STM32_CLOCK(val, 1, 23, CFGR_REG) argument
77 #define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BDCR_REG) argument
85 #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, DCKCFGR2_REG) argument
86 #define USART2_SEL(val) STM32_CLOCK(val, 3, 2, DCKCFGR2_REG) argument
87 #define USART3_SEL(val) STM32_CLOCK(val, 3, 4, DCKCFGR2_REG) argument
88 #define USART4_SEL(val) STM32_CLOCK(val, 3, 6, DCKCFGR2_REG) argument
89 #define USART5_SEL(val) STM32_CLOCK(val, 3, 8, DCKCFGR2_REG) argument
90 #define USART6_SEL(val) STM32_CLOCK(val, 3, 10, DCKCFGR2_REG) argument
[all …]
Dstm32f3_clock.h54 #define STM32_CLOCK(val, mask, shift, reg) \ argument
58 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
69 #define I2S_SEL(val) STM32_CLOCK(val, 1, 23, CFGR_REG) argument
71 #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CFGR3_REG) argument
72 #define I2C1_SEL(val) STM32_CLOCK(val, 1, 4, CFGR3_REG) argument
73 #define I2C2_SEL(val) STM32_CLOCK(val, 1, 5, CFGR3_REG) argument
74 #define I2C3_SEL(val) STM32_CLOCK(val, 1, 6, CFGR3_REG) argument
75 #define TIM1_SEL(val) STM32_CLOCK(val, 1, 8, CFGR3_REG) argument
76 #define TIM8_SEL(val) STM32_CLOCK(val, 1, 9, CFGR3_REG) argument
77 #define TIM15_SEL(val) STM32_CLOCK(val, 1, 10, CFGR3_REG) argument
[all …]
Dstm32g4_clock.h62 #define STM32_CLOCK(val, mask, shift, reg) \ argument
66 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
77 #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG) argument
78 #define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR_REG) argument
79 #define USART3_SEL(val) STM32_CLOCK(val, 3, 4, CCIPR_REG) argument
80 #define USART4_SEL(val) STM32_CLOCK(val, 3, 6, CCIPR_REG) argument
81 #define USART5_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR_REG) argument
82 #define LPUART1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR_REG) argument
83 #define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG) argument
84 #define I2C2_SEL(val) STM32_CLOCK(val, 3, 14, CCIPR_REG) argument
[all …]
Dstm32g0_clock.h59 #define STM32_CLOCK(val, mask, shift, reg) \ argument
63 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
74 #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG) argument
75 #define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR_REG) argument
76 #define USART3_SEL(val) STM32_CLOCK(val, 3, 4, CCIPR_REG) argument
77 #define CEC_SEL(val) STM32_CLOCK(val, 1, 6, CCIPR_REG) argument
78 #define LPUART2_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR_REG) argument
79 #define LPUART1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR_REG) argument
80 #define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG) argument
81 #define I2C2_I2S1_SEL(val) STM32_CLOCK(val, 3, 14, CCIPR_REG) argument
[all …]
Dstm32f410_clock.h15 #define CKDFSDM2A_SEL(val) STM32_CLOCK(val, 1, 14, DCKCFGR_REG) argument
16 #define CKDFSDM1A_SEL(val) STM32_CLOCK(val, 1, 15, DCKCFGR_REG) argument
17 #define SAI1A_SEL(val) STM32_CLOCK(val, 3, 20, DCKCFGR_REG) argument
18 #define SAI1B_SEL(val) STM32_CLOCK(val, 3, 22, DCKCFGR_REG) argument
19 #define I2S1_SEL(val) STM32_CLOCK(val, 3, 25, DCKCFGR_REG) argument
20 #define I2S2_SEL(val) STM32_CLOCK(val, 3, 27, DCKCFGR_REG) argument
21 #define CKDFSDM_SEL(val) STM32_CLOCK(val, 1, 31, DCKCFGR_REG) argument
24 #define I2CFMP1_SEL(val) STM32_CLOCK(val, 3, 22, DCKCFGR2_REG) argument
25 #define CK48M_SEL(val) STM32_CLOCK(val, 1, 27, DCKCFGR2_REG) argument
26 #define SDIO_SEL(val) STM32_CLOCK(val, 1, 28, DCKCFGR2_REG) argument
[all …]
Dstm32wl_clock.h60 #define STM32_CLOCK(val, mask, shift, reg) \ argument
64 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
74 #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG) argument
75 #define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR_REG) argument
76 #define SPI2_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR_REG) argument
77 #define LPUART1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR_REG) argument
78 #define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG) argument
79 #define I2C2_SEL(val) STM32_CLOCK(val, 3, 14, CCIPR_REG) argument
80 #define I2C3_SEL(val) STM32_CLOCK(val, 3, 16, CCIPR_REG) argument
81 #define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 18, CCIPR_REG) argument
[all …]
Dstm32wb_clock.h62 #define STM32_CLOCK(val, mask, shift, reg) \ argument
66 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
79 #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG) argument
80 #define LPUART1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR_REG) argument
81 #define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG) argument
82 #define I2C3_SEL(val) STM32_CLOCK(val, 3, 16, CCIPR_REG) argument
83 #define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 18, CCIPR_REG) argument
84 #define LPTIM2_SEL(val) STM32_CLOCK(val, 3, 20, CCIPR_REG) argument
85 #define SAI1_SEL(val) STM32_CLOCK(val, 3, 22, CCIPR_REG) argument
86 #define CLK48_SEL(val) STM32_CLOCK(val, 3, 26, CCIPR_REG) argument
[all …]
Dstm32f427_clock.h14 #define CKDFSDM2A_SEL(val) STM32_CLOCK(val, 1, 14, DCKCFGR_REG) argument
15 #define CKDFSDM1A_SEL(val) STM32_CLOCK(val, 1, 15, DCKCFGR_REG) argument
16 #define SAI1A_SEL(val) STM32_CLOCK(val, 3, 20, DCKCFGR_REG) argument
17 #define SAI1B_SEL(val) STM32_CLOCK(val, 3, 22, DCKCFGR_REG) argument
18 #define CLK48M_SEL(val) STM32_CLOCK(val, 1, 27, DCKCFGR_REG) argument
19 #define SDMMC_SEL(val) STM32_CLOCK(val, 1, 28, DCKCFGR_REG) argument
20 #define DSI_SEL(val) STM32_CLOCK(val, 1, 29, DCKCFGR_REG) argument
Dstm32f0_clock.h53 #define STM32_CLOCK(val, mask, shift, reg) \ argument
57 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
67 #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CFGR3_REG) argument
68 #define I2C1_SEL(val) STM32_CLOCK(val, 1, 4, CFGR3_REG) argument
69 #define CEC_SEL(val) STM32_CLOCK(val, 1, 6, CFGR3_REG) argument
70 #define USB_SEL(val) STM32_CLOCK(val, 1, 7, CFGR3_REG) argument
71 #define ADC_SEL(val) STM32_CLOCK(val, 1, 8, CFGR3_REG) argument
72 #define USART2_SEL(val) STM32_CLOCK(val, 3, 16, CFGR3_REG) argument
73 #define USART3_SEL(val) STM32_CLOCK(val, 3, 18, CFGR3_REG) argument
75 #define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BDCR_REG) argument
Dstm32l0_clock.h54 #define STM32_CLOCK(val, mask, shift, reg) \ argument
58 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
68 #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG) argument
69 #define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR_REG) argument
70 #define LPUART1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR_REG) argument
71 #define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG) argument
72 #define I2C3_SEL(val) STM32_CLOCK(val, 3, 16, CCIPR_REG) argument
73 #define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 18, CCIPR_REG) argument
74 #define HSI48_SEL(val) STM32_CLOCK(val, 1, 26, CCIPR_REG) argument
76 #define RTC_SEL(val) STM32_CLOCK(val, 3, 16, CSR_REG) argument
/Zephyr-Core-3.4.0/include/zephyr/sys/
Dbyteorder.h172 #define sys_le16_to_cpu(val) (val) argument
173 #define sys_cpu_to_le16(val) (val) argument
174 #define sys_le24_to_cpu(val) (val) argument
175 #define sys_cpu_to_le24(val) (val) argument
176 #define sys_le32_to_cpu(val) (val) argument
177 #define sys_cpu_to_le32(val) (val) argument
178 #define sys_le48_to_cpu(val) (val) argument
179 #define sys_cpu_to_le48(val) (val) argument
180 #define sys_le64_to_cpu(val) (val) argument
181 #define sys_cpu_to_le64(val) (val) argument
[all …]
/Zephyr-Core-3.4.0/subsys/net/
Dbuf_simple.c76 uint8_t *net_buf_simple_add_u8(struct net_buf_simple *buf, uint8_t val) in net_buf_simple_add_u8() argument
80 NET_BUF_SIMPLE_DBG("buf %p val 0x%02x", buf, val); in net_buf_simple_add_u8()
83 *u8 = val; in net_buf_simple_add_u8()
88 void net_buf_simple_add_le16(struct net_buf_simple *buf, uint16_t val) in net_buf_simple_add_le16() argument
90 NET_BUF_SIMPLE_DBG("buf %p val %u", buf, val); in net_buf_simple_add_le16()
92 sys_put_le16(val, net_buf_simple_add(buf, sizeof(val))); in net_buf_simple_add_le16()
95 void net_buf_simple_add_be16(struct net_buf_simple *buf, uint16_t val) in net_buf_simple_add_be16() argument
97 NET_BUF_SIMPLE_DBG("buf %p val %u", buf, val); in net_buf_simple_add_be16()
99 sys_put_be16(val, net_buf_simple_add(buf, sizeof(val))); in net_buf_simple_add_be16()
102 void net_buf_simple_add_le24(struct net_buf_simple *buf, uint32_t val) in net_buf_simple_add_le24() argument
[all …]
/Zephyr-Core-3.4.0/drivers/dai/intel/dmic/
Ddmic_nhlt.c28 uint32_t reg, uint32_t val) in dai_dmic_write() argument
30 sys_write32(val, dmic->reg_base + reg); in dai_dmic_write()
220 uint32_t val; in dai_dmic_set_config_nhlt() local
270 val = *(uint32_t *)p; in dai_dmic_set_config_nhlt()
271 out_control[n] = val; in dai_dmic_set_config_nhlt()
272 bf1 = OUTCONTROL0_TIE_GET(val); in dai_dmic_set_config_nhlt()
273 bf2 = OUTCONTROL0_SIP_GET(val); in dai_dmic_set_config_nhlt()
274 bf3 = OUTCONTROL0_FINIT_GET(val); in dai_dmic_set_config_nhlt()
275 bf4 = OUTCONTROL0_FCI_GET(val); in dai_dmic_set_config_nhlt()
276 bf5 = OUTCONTROL0_BFTH_GET(val); in dai_dmic_set_config_nhlt()
[all …]
/Zephyr-Core-3.4.0/subsys/bluetooth/mesh/
Dsar_cfg.c42 uint8_t val; in bt_mesh_sar_tx_decode() local
44 val = net_buf_simple_pull_u8(buf); in bt_mesh_sar_tx_decode()
45 tx->seg_int_step = (val & 0xf); in bt_mesh_sar_tx_decode()
46 tx->unicast_retrans_count = (val >> 4); in bt_mesh_sar_tx_decode()
47 val = net_buf_simple_pull_u8(buf); in bt_mesh_sar_tx_decode()
48 tx->unicast_retrans_without_prog_count = (val & 0xf); in bt_mesh_sar_tx_decode()
49 tx->unicast_retrans_int_step = (val >> 4); in bt_mesh_sar_tx_decode()
50 val = net_buf_simple_pull_u8(buf); in bt_mesh_sar_tx_decode()
51 tx->unicast_retrans_int_inc = (val & 0xf); in bt_mesh_sar_tx_decode()
52 tx->multicast_retrans_count = (val >> 4); in bt_mesh_sar_tx_decode()
[all …]
/Zephyr-Core-3.4.0/include/zephyr/dt-bindings/dma/
Dstm32_dma.h14 #define STM32_DMA_CH_CFG_MODE(val) ((val & 0x1) << 5) argument
19 #define STM32_DMA_CH_CFG_DIRECTION(val) ((val & 0x3) << 6) argument
26 #define STM32_DMA_CH_CFG_PERIPH_ADDR_INC(val) ((val & 0x1) << 9) argument
31 #define STM32_DMA_CH_CFG_MEM_ADDR_INC(val) ((val & 0x1) << 10) argument
36 #define STM32_DMA_CH_CFG_PERIPH_WIDTH(val) ((val & 0x3) << 11) argument
42 #define STM32_DMA_CH_CFG_MEM_WIDTH(val) ((val & 0x3) << 13) argument
48 #define STM32_DMA_CH_CFG_PERIPH_INC_FIXED(val) ((val & 0x1) << 15) argument
51 #define STM32_DMA_CH_CFG_PRIORITY(val) ((val & 0x3) << 16) argument
Dgd32_dma.h13 #define GD32_DMA_CH_CFG_DIRECTION(val) ((val & 0x3) << 6) argument
19 #define GD32_DMA_CH_CFG_PERIPH_ADDR_INC(val) ((val & 0x1) << 9) argument
24 #define GD32_DMA_CH_CFG_MEMORY_ADDR_INC(val) ((val & 0x1) << 10) argument
29 #define GD32_DMA_CH_CFG_PERIPH_WIDTH(val) ((val & 0x3) << 11) argument
35 #define GD32_DMA_CH_CFG_MEMORY_WIDTH(val) ((val & 0x3) << 13) argument
41 #define GD32_DMA_CH_CFG_PERIPH_INC_FIXED(val) ((val & 0x1) << 15) argument
44 #define GD32_DMA_CH_CFG_PRIORITY(val) ((val & 0x3) << 16) argument
/Zephyr-Core-3.4.0/drivers/fuel_gauge/sbs_gauge/
Dsbs_gauge.c21 static int sbs_cmd_reg_read(const struct device *dev, uint8_t reg_addr, uint16_t *val) in sbs_cmd_reg_read() argument
34 *val = sys_get_le16(i2c_data); in sbs_cmd_reg_read()
39 static int sbs_cmd_reg_write(const struct device *dev, uint8_t reg_addr, uint16_t val) in sbs_cmd_reg_write() argument
44 sys_put_le16(val, buf); in sbs_cmd_reg_write()
68 uint16_t val = 0; in sbs_gauge_get_prop() local
72 rc = sbs_cmd_reg_read(dev, SBS_GAUGE_CMD_AVG_CURRENT, &val); in sbs_gauge_get_prop()
73 prop->value.avg_current = val * 1000; in sbs_gauge_get_prop()
76 rc = sbs_cmd_reg_read(dev, SBS_GAUGE_CMD_CYCLE_COUNT, &val); in sbs_gauge_get_prop()
77 prop->value.cycle_count = val; in sbs_gauge_get_prop()
80 rc = sbs_cmd_reg_read(dev, SBS_GAUGE_CMD_CURRENT, &val); in sbs_gauge_get_prop()
[all …]
/Zephyr-Core-3.4.0/tests/drivers/sensor/generic/src/
Ddummy_sensor.c35 struct sensor_value *val) in dummy_sensor_channel_get() argument
41 val->val1 = data->val[0].val1; in dummy_sensor_channel_get()
42 val->val2 = data->val[0].val2; in dummy_sensor_channel_get()
45 val->val1 = data->val[1].val1; in dummy_sensor_channel_get()
46 val->val2 = data->val[1].val2; in dummy_sensor_channel_get()
49 val->val1 = data->val[2].val1; in dummy_sensor_channel_get()
50 val->val2 = data->val[2].val2; in dummy_sensor_channel_get()
53 val->val1 = data->val[3].val1; in dummy_sensor_channel_get()
54 val->val2 = data->val[3].val2; in dummy_sensor_channel_get()
57 val->val1 = data->val[4].val1; in dummy_sensor_channel_get()
[all …]
/Zephyr-Core-3.4.0/tests/kernel/common/src/
Dbyteorder.c79 uint64_t val = 0xf0e1d2c3b4a59687, tmp; in ZTEST() local
86 zassert_equal(tmp, val, "sys_get_be64() failed"); in ZTEST()
98 uint64_t val = 0xf0e1d2c3b4a59687; in ZTEST() local
104 sys_put_be64(val, tmp); in ZTEST()
118 uint64_t val = 0xf0e1d2c3b4a5, tmp; in ZTEST() local
125 zassert_equal(tmp, val, "sys_get_be64() failed"); in ZTEST()
137 uint64_t val = 0xf0e1d2c3b4a5; in ZTEST() local
143 sys_put_be48(val, tmp); in ZTEST()
156 uint32_t val = 0xf0e1d2c3, tmp; in ZTEST() local
163 zassert_equal(tmp, val, "sys_get_be32() failed"); in ZTEST()
[all …]
/Zephyr-Core-3.4.0/drivers/counter/
Dcounter_ace_v1x_art.c19 uint32_t val; in counter_ace_v1x_art_ionte_set() local
21 val = sys_read32(ACE_TSCTRL); in counter_ace_v1x_art_ionte_set()
22 val &= ~ACE_TSCTRL_IONTE_MASK; in counter_ace_v1x_art_ionte_set()
23 val |= FIELD_PREP(ACE_TSCTRL_IONTE_MASK, new_timestamp_enable); in counter_ace_v1x_art_ionte_set()
24 sys_write32(val, ACE_TSCTRL); in counter_ace_v1x_art_ionte_set()
29 uint32_t val; in counter_ace_v1x_art_cdmas_set() local
31 val = sys_read32(ACE_TSCTRL); in counter_ace_v1x_art_cdmas_set()
32 val &= ~ACE_TSCTRL_CDMAS_MASK; in counter_ace_v1x_art_cdmas_set()
33 val |= FIELD_PREP(ACE_TSCTRL_CDMAS_MASK, cdmas); in counter_ace_v1x_art_cdmas_set()
34 sys_write32(val, ACE_TSCTRL); in counter_ace_v1x_art_cdmas_set()
[all …]
/Zephyr-Core-3.4.0/subsys/bluetooth/host/
Duuid.c27 .val = { BT_UUID_128_ENCODE(
36 sys_put_le16(BT_UUID_16(src)->val, in uuid_to_uuid128()
37 &dst->val[UUID_16_BASE_OFFSET]); in uuid_to_uuid128()
41 sys_put_le32(BT_UUID_32(src)->val, in uuid_to_uuid128()
42 &dst->val[UUID_16_BASE_OFFSET]); in uuid_to_uuid128()
57 return memcmp(uuid1.val, uuid2.val, 16); in uuid128_cmp()
69 return (int)BT_UUID_16(u1)->val - (int)BT_UUID_16(u2)->val; in bt_uuid_cmp()
71 return (int)BT_UUID_32(u1)->val - (int)BT_UUID_32(u2)->val; in bt_uuid_cmp()
73 return memcmp(BT_UUID_128(u1)->val, BT_UUID_128(u2)->val, 16); in bt_uuid_cmp()
85 BT_UUID_16(uuid)->val = sys_get_le16(data); in bt_uuid_create()
[all …]

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