1 /* 2 * Copyright (c) 2019, MADMACHINE LIMITED 3 * 4 * refer to hal_nxp board file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 */ 8 9 #ifndef __FLEXSPI_NOR_CONFIG__ 10 #define __FLEXSPI_NOR_CONFIG__ 11 12 #include <zephyr/types.h> 13 #include "fsl_common.h" 14 15 #define FLEXSPI_CFG_BLK_TAG (0x42464346UL) 16 #define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) 17 #define FLEXSPI_CFG_BLK_SIZE (512) 18 19 #define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 20 21 #define CMD_INDEX_READ 0 22 #define CMD_INDEX_READSTATUS 1 23 #define CMD_INDEX_WRITEENABLE 2 24 #define CMD_INDEX_WRITE 4 25 26 #define CMD_LUT_SEQ_IDX_READ 0 27 #define CMD_LUT_SEQ_IDX_READSTATUS 1 28 #define CMD_LUT_SEQ_IDX_WRITEENABLE 3 29 #define CMD_LUT_SEQ_IDX_WRITE 9 30 31 #define CMD_SDR 0x01 32 #define CMD_DDR 0x21 33 #define RADDR_SDR 0x02 34 #define RADDR_DDR 0x22 35 #define CADDR_SDR 0x03 36 #define CADDR_DDR 0x23 37 #define MODE1_SDR 0x04 38 #define MODE1_DDR 0x24 39 #define MODE2_SDR 0x05 40 #define MODE2_DDR 0x25 41 #define MODE4_SDR 0x06 42 #define MODE4_DDR 0x26 43 #define MODE8_SDR 0x07 44 #define MODE8_DDR 0x27 45 #define WRITE_SDR 0x08 46 #define WRITE_DDR 0x28 47 #define READ_SDR 0x09 48 #define READ_DDR 0x29 49 #define LEARN_SDR 0x0A 50 #define LEARN_DDR 0x2A 51 #define DATSZ_SDR 0x0B 52 #define DATSZ_DDR 0x2B 53 #define DUMMY_SDR 0x0C 54 #define DUMMY_DDR 0x2C 55 #define DUMMY_RWDS_SDR 0x0D 56 #define DUMMY_RWDS_DDR 0x2D 57 #define JMP_ON_CS 0x1F 58 #define STOP 0 59 60 #define FLEXSPI_1PAD 0 61 #define FLEXSPI_2PAD 1 62 #define FLEXSPI_4PAD 2 63 #define FLEXSPI_8PAD 3 64 65 #define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ 66 (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | \ 67 FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ 68 FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) 69 70 /* For flexspi_mem_config.serialClkFreq */ 71 #if defined(CONFIG_SOC_MIMXRT1011) 72 enum { 73 kFlexSpiSerialClk_30MHz = 1, 74 kFlexSpiSerialClk_50MHz = 2, 75 kFlexSpiSerialClk_60MHz = 3, 76 kFlexSpiSerialClk_75MHz = 4, 77 kFlexSpiSerialClk_80MHz = 5, 78 kFlexSpiSerialClk_100MHz = 6, 79 kFlexSpiSerialClk_120MHz = 7, 80 kFlexSpiSerialClk_133MHz = 8, 81 }; 82 #elif defined(CONFIG_SOC_MIMXRT1015) || defined(CONFIG_SOC_MIMXRT1021) || \ 83 defined(CONFIG_SOC_MIMXRT1024) 84 enum { 85 kFlexSpiSerialClk_30MHz = 1, 86 kFlexSpiSerialClk_50MHz = 2, 87 kFlexSpiSerialClk_60MHz = 3, 88 kFlexSpiSerialClk_75MHz = 4, 89 kFlexSpiSerialClk_80MHz = 5, 90 kFlexSpiSerialClk_100MHz = 6, 91 kFlexSpiSerialClk_133MHz = 7, 92 }; 93 #elif defined(CONFIG_SOC_MIMXRT1051) || defined(CONFIG_SOC_MIMXRT1052) 94 enum { 95 kFlexSpiSerialClk_30MHz = 1, 96 kFlexSpiSerialClk_50MHz = 2, 97 kFlexSpiSerialClk_60MHz = 3, 98 kFlexSpiSerialClk_75MHz = 4, 99 kFlexSpiSerialClk_80MHz = 5, 100 kFlexSpiSerialClk_100MHz = 6, 101 kFlexSpiSerialClk_133MHz = 7, 102 kFlexSpiSerialClk_166MHz = 8, 103 kFlexSpiSerialClk_200MHz = 9, 104 }; 105 #elif defined(CONFIG_SOC_MIMXRT1061) || defined(CONFIG_SOC_MIMXRT1062) || \ 106 defined(CONFIG_SOC_MIMXRT1062) || defined(CONFIG_SOC_MIMXRT1064) 107 enum { 108 kFlexSpiSerialClk_30MHz = 1, 109 kFlexSpiSerialClk_50MHz = 2, 110 kFlexSpiSerialClk_60MHz = 3, 111 kFlexSpiSerialClk_75MHz = 4, 112 kFlexSpiSerialClk_80MHz = 5, 113 kFlexSpiSerialClk_100MHz = 6, 114 kFlexSpiSerialClk_120MHz = 7, 115 kFlexSpiSerialClk_133MHz = 8, 116 kFlexSpiSerialClk_166MHz = 9, 117 }; 118 #else 119 #error "kFlexSpiSerialClk is not defined for this SoC" 120 #endif 121 122 /* For flexspi_mem_config.controllerMiscOption */ 123 enum { 124 kFlexSpiClk_SDR, 125 kFlexSpiClk_DDR, 126 }; 127 128 /* For flexspi_mem_config.readSampleClkSrc */ 129 enum { 130 kFlexSPIReadSampleClk_LoopbackInternally = 0, 131 kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, 132 kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, 133 kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, 134 }; 135 136 /* For flexspi_mem_config.controllerMiscOption */ 137 enum { 138 /* !< Bit for Differential clock enable */ 139 kFlexSpiMiscOffset_DiffClkEnable = 0, 140 /* !< Bit for CK2 enable */ 141 kFlexSpiMiscOffset_Ck2Enable = 1, 142 /* !< Bit for Parallel mode enable */ 143 kFlexSpiMiscOffset_ParallelEnable = 2, 144 /* !< Bit for Word Addressable enable */ 145 kFlexSpiMiscOffset_WordAddressableEnable = 3, 146 /* !< Bit for Safe Configuration Frequency enable */ 147 kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, 148 /* !< Bit for Pad setting override enable */ 149 kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, 150 /* !< Bit for DDR clock configuration indication. */ 151 kFlexSpiMiscOffset_DdrModeEnable = 6, 152 }; 153 154 /* For flexspi_mem_config.deviceType */ 155 enum { 156 /* !< Flash devices are Serial NOR */ 157 kFlexSpiDeviceType_SerialNOR = 1, 158 /* !< Flash devices are Serial NAND */ 159 kFlexSpiDeviceType_SerialNAND = 2, 160 /* !< Flash devices are Serial RAM/HyperFLASH */ 161 kFlexSpiDeviceType_SerialRAM = 3, 162 /* !< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND */ 163 kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, 164 /* !< Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs */ 165 kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, 166 }; 167 168 /* For flexspi_mem_config.sflashPadType */ 169 enum { 170 kSerialFlash_1Pad = 1, 171 kSerialFlash_2Pads = 2, 172 kSerialFlash_4Pads = 4, 173 kSerialFlash_8Pads = 8, 174 }; 175 176 enum { 177 /* !< Generic command, for example: configure dummy cycles, drive strength, etc */ 178 kDeviceConfigCmdType_Generic, 179 /* !< Quad Enable command */ 180 kDeviceConfigCmdType_QuadEnable, 181 /* !< Switch from SPI to DPI/QPI/OPI mode */ 182 kDeviceConfigCmdType_Spi2Xpi, 183 /* !< Switch from DPI/QPI/OPI to SPI mode */ 184 kDeviceConfigCmdType_Xpi2Spi, 185 /* !< Switch to 0-4-4/0-8-8 mode */ 186 kDeviceConfigCmdType_Spi2NoCmd, 187 /* !< Reset device command */ 188 kDeviceConfigCmdType_Reset, 189 }; 190 191 struct flexspi_lut_seq_t { 192 uint8_t seqNum; 193 uint8_t seqId; 194 uint16_t reserved; 195 }; 196 197 struct flexspi_mem_config_t { 198 /* !< [0x000-0x003] Tag, fixed value 0x42464346UL */ 199 uint32_t tag; 200 /* !< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix */ 201 uint32_t version; 202 /* !< [0x008-0x00b] Reserved for future use */ 203 uint32_t reserved0; 204 /* !< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 */ 205 uint8_t readSampleClkSrc; 206 /* !< [0x00d-0x00d] CS hold time, default value: 3 */ 207 uint8_t csHoldTime; 208 /* !< [0x00e-0x00e] CS setup time, default value: 3 */ 209 uint8_t csSetupTime; 210 /* !< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For */ 211 uint8_t columnAddressWidth; 212 /* ! Serial NAND, need to refer to datasheet */ 213 /* !< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable */ 214 uint8_t deviceModeCfgEnable; 215 /* !< [0x011-0x011] Specify the configuration command 216 * type:Quad Enable, DPI/QPI/OPI switch, 217 */ 218 uint8_t deviceModeType; 219 /* ! Generic configuration, etc. */ 220 /* !< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for */ 221 uint16_t waitTimeCfgCommands; 222 /* ! DPI/QPI/OPI switch or reset command */ 223 /* !< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt */ 224 struct flexspi_lut_seq_t deviceModeSeq; 225 /* ! sequence number, [31:16] Reserved */ 226 /* !< [0x018-0x01b] Argument/Parameter for device configuration */ 227 uint32_t deviceModeArg; 228 /* !< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable */ 229 uint8_t configCmdEnable; 230 /* !< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe */ 231 uint8_t configModeType[3]; 232 /* !< [0x020-0x02b] Sequence info for Device Configuration command, similar as 233 * deviceModeSeq 234 */ 235 struct flexspi_lut_seq_t configCmdSeqs[3]; 236 /* !< [0x02c-0x02f] Reserved for future use */ 237 uint32_t reserved1; 238 /* !< [0x030-0x03b] Arguments/Parameters for device Configuration commands */ 239 uint32_t configCmdArgs[3]; 240 /* !< [0x03c-0x03f] Reserved for future use */ 241 uint32_t reserved2; 242 /* !< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more */ 243 uint32_t controllerMiscOption; 244 /* ! details */ 245 /* !< [0x044-0x044] Device Type: See Flash Type Definition for more details */ 246 uint8_t deviceType; 247 /* !< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal */ 248 uint8_t sflashPadType; 249 /* !< [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot */ 250 uint8_t serialClkFreq; 251 /* ! Chapter for more details */ 252 /* !< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot */ 253 uint8_t lutCustomSeqEnable; 254 /* ! be done using 1 LUT sequence, currently, only applicable to HyperFLASH */ 255 /* !< [0x048-0x04f] Reserved for future use */ 256 uint32_t reserved3[2]; 257 /* !< [0x050-0x053] Size of Flash connected to A1 */ 258 uint32_t sflashA1Size; 259 /* !< [0x054-0x057] Size of Flash connected to A2 */ 260 uint32_t sflashA2Size; 261 /* !< [0x058-0x05b] Size of Flash connected to B1 */ 262 uint32_t sflashB1Size; 263 /* !< [0x05c-0x05f] Size of Flash connected to B2 */ 264 uint32_t sflashB2Size; 265 /* !< [0x060-0x063] CS pad setting override value */ 266 uint32_t csPadSettingOverride; 267 /* !< [0x064-0x067] SCK pad setting override value */ 268 uint32_t sclkPadSettingOverride; 269 /* !< [0x068-0x06b] data pad setting override value */ 270 uint32_t dataPadSettingOverride; 271 /* !< [0x06c-0x06f] DQS pad setting override value */ 272 uint32_t dqsPadSettingOverride; 273 /* !< [0x070-0x073] Timeout threshold for read status command */ 274 uint32_t timeoutInMs; 275 /* !< [0x074-0x077] CS deselect interval between two commands */ 276 uint32_t commandInterval; 277 /* !< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns */ 278 uint16_t dataValidTime[2]; 279 /* !< [0x07c-0x07d] Busy offset, valid value: 0-31 */ 280 uint16_t busyOffset; 281 /* !< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - */ 282 uint16_t busyBitPolarity; 283 /* ! busy flag is 0 when flash device is busy */ 284 /* !< [0x080-0x17f] Lookup table holds Flash command sequences */ 285 uint32_t lookupTable[64]; 286 /* !< [0x180-0x1af] Customizable LUT Sequences */ 287 struct flexspi_lut_seq_t lutCustomSeq[12]; 288 /* !< [0x1b0-0x1bf] Reserved for future use */ 289 uint32_t reserved4[4]; 290 }; 291 292 #define NOR_CMD_INDEX_READ CMD_INDEX_READ 293 #define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS 294 #define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE 295 #define NOR_CMD_INDEX_ERASESECTOR 3 296 #define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE 297 #define NOR_CMD_INDEX_CHIPERASE 5 298 #define NOR_CMD_INDEX_DUMMY 6 299 #define NOR_CMD_INDEX_ERASEBLOCK 7 300 301 #define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ 302 #define NOR_CMD_LUT_SEQ_IDX_READSTATUS CMD_LUT_SEQ_IDX_READSTATUS 303 #define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI 2 304 #define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE CMD_LUT_SEQ_IDX_WRITEENABLE 305 #define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI 4 306 #define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 307 #define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 308 #define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM CMD_LUT_SEQ_IDX_WRITE 309 #define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 310 #define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 311 #define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD 14 312 #define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD 15 313 314 struct flexspi_nor_config_t { 315 /* !< Common memory configuration info via FlexSPI */ 316 struct flexspi_mem_config_t memConfig; 317 /* !< Page size of Serial NOR */ 318 uint32_t pageSize; 319 /* !< Sector size of Serial NOR */ 320 uint32_t sectorSize; 321 /* !< Clock frequency for IP command */ 322 uint8_t ipcmdSerialClkFreq; 323 /* !< Sector/Block size is the same */ 324 uint8_t isUniformBlockSize; 325 /* !< Reserved for future use */ 326 uint8_t reserved0[2]; 327 /* !< Serial NOR Flash type: 0/1/2/3 */ 328 uint8_t serialNorType; 329 /* !< Need to exit NoCmd mode before other IP command */ 330 uint8_t needExitNoCmdMode; 331 /* !< Half the Serial Clock for non-read command: true/false */ 332 uint8_t halfClkForNonReadCmd; 333 /* !< Need to Restore NoCmd mode after IP command execution */ 334 uint8_t needRestoreNoCmdMode; 335 /* !< Block size */ 336 uint32_t blockSize; 337 /* !< Reserved for future use */ 338 uint32_t reserve2[11]; 339 }; 340 341 #ifdef __cplusplus 342 extern "C" { 343 #endif 344 345 #ifdef __cplusplus 346 } 347 #endif 348 #endif 349
