1 /* 2 * Copyright (c) 2020 ITE Corporation. All Rights Reserved. 3 * SPDX-License-Identifier: Apache-2.0 4 */ 5 6 #ifndef CHIP_CHIPREGS_H 7 #define CHIP_CHIPREGS_H 8 9 #include <zephyr/sys/util.h> 10 11 #define EC_REG_BASE_ADDR 0x00f00000 12 13 #ifdef _ASMLANGUAGE 14 #define ECREG(x) x 15 #else 16 17 /* 18 * Macros for hardware registers access. 19 */ 20 #define ECREG(x) (*((volatile unsigned char *)(x))) 21 #define ECREG_u16(x) (*((volatile unsigned short *)(x))) 22 #define ECREG_u32(x) (*((volatile unsigned long *)(x))) 23 24 /* 25 * MASK operation macros 26 */ 27 #define SET_MASK(reg, bit_mask) ((reg) |= (bit_mask)) 28 #define CLEAR_MASK(reg, bit_mask) ((reg) &= (~(bit_mask))) 29 #define IS_MASK_SET(reg, bit_mask) (((reg) & (bit_mask)) != 0) 30 #endif /* _ASMLANGUAGE */ 31 32 #ifndef REG_BASE_ADDR 33 #define REG_BASE_ADDR EC_REG_BASE_ADDR 34 #endif 35 36 /* Common definition */ 37 /* 38 * EC clock frequency (PWM and tachometer driver need it to reply 39 * to api or calculate RPM) 40 */ 41 #define EC_FREQ MHZ(8) 42 43 44 /* --- General Control (GCTRL) --- */ 45 #define IT8XXX2_GCTRL_BASE 0x00F02000 46 #define IT8XXX2_GCTRL_EIDSR ECREG(IT8XXX2_GCTRL_BASE + 0x31) 47 48 /** 49 * 50 * (11xxh) Interrupt controller (INTC) 51 * 52 */ 53 #define ISR0 ECREG(EC_REG_BASE_ADDR + 0x3F00) 54 #define ISR1 ECREG(EC_REG_BASE_ADDR + 0x3F01) 55 #define ISR2 ECREG(EC_REG_BASE_ADDR + 0x3F02) 56 #define ISR3 ECREG(EC_REG_BASE_ADDR + 0x3F03) 57 #define ISR4 ECREG(EC_REG_BASE_ADDR + 0x3F14) 58 #define ISR5 ECREG(EC_REG_BASE_ADDR + 0x3F18) 59 #define ISR6 ECREG(EC_REG_BASE_ADDR + 0x3F1C) 60 #define ISR7 ECREG(EC_REG_BASE_ADDR + 0x3F20) 61 #define ISR8 ECREG(EC_REG_BASE_ADDR + 0x3F24) 62 #define ISR9 ECREG(EC_REG_BASE_ADDR + 0x3F28) 63 #define ISR10 ECREG(EC_REG_BASE_ADDR + 0x3F2C) 64 #define ISR11 ECREG(EC_REG_BASE_ADDR + 0x3F30) 65 #define ISR12 ECREG(EC_REG_BASE_ADDR + 0x3F34) 66 #define ISR13 ECREG(EC_REG_BASE_ADDR + 0x3F38) 67 #define ISR14 ECREG(EC_REG_BASE_ADDR + 0x3F3C) 68 #define ISR15 ECREG(EC_REG_BASE_ADDR + 0x3F40) 69 #define ISR16 ECREG(EC_REG_BASE_ADDR + 0x3F44) 70 #define ISR17 ECREG(EC_REG_BASE_ADDR + 0x3F48) 71 #define ISR18 ECREG(EC_REG_BASE_ADDR + 0x3F4C) 72 #define ISR19 ECREG(EC_REG_BASE_ADDR + 0x3F50) 73 #define ISR20 ECREG(EC_REG_BASE_ADDR + 0x3F54) 74 #define ISR21 ECREG(EC_REG_BASE_ADDR + 0x3F58) 75 #define ISR22 ECREG(EC_REG_BASE_ADDR + 0x3F5C) 76 #define ISR23 ECREG(EC_REG_BASE_ADDR + 0x3F90) 77 78 #define IER0 ECREG(EC_REG_BASE_ADDR + 0x3F04) 79 #define IER1 ECREG(EC_REG_BASE_ADDR + 0x3F05) 80 #define IER2 ECREG(EC_REG_BASE_ADDR + 0x3F06) 81 #define IER3 ECREG(EC_REG_BASE_ADDR + 0x3F07) 82 #define IER4 ECREG(EC_REG_BASE_ADDR + 0x3F15) 83 #define IER5 ECREG(EC_REG_BASE_ADDR + 0x3F19) 84 #define IER6 ECREG(EC_REG_BASE_ADDR + 0x3F1D) 85 #define IER7 ECREG(EC_REG_BASE_ADDR + 0x3F21) 86 #define IER8 ECREG(EC_REG_BASE_ADDR + 0x3F25) 87 #define IER9 ECREG(EC_REG_BASE_ADDR + 0x3F29) 88 #define IER10 ECREG(EC_REG_BASE_ADDR + 0x3F2D) 89 #define IER11 ECREG(EC_REG_BASE_ADDR + 0x3F31) 90 #define IER12 ECREG(EC_REG_BASE_ADDR + 0x3F35) 91 #define IER13 ECREG(EC_REG_BASE_ADDR + 0x3F39) 92 #define IER14 ECREG(EC_REG_BASE_ADDR + 0x3F3D) 93 #define IER15 ECREG(EC_REG_BASE_ADDR + 0x3F41) 94 #define IER16 ECREG(EC_REG_BASE_ADDR + 0x3F45) 95 #define IER17 ECREG(EC_REG_BASE_ADDR + 0x3F49) 96 #define IER18 ECREG(EC_REG_BASE_ADDR + 0x3F4D) 97 #define IER19 ECREG(EC_REG_BASE_ADDR + 0x3F51) 98 #define IER20 ECREG(EC_REG_BASE_ADDR + 0x3F55) 99 #define IER21 ECREG(EC_REG_BASE_ADDR + 0x3F59) 100 #define IER22 ECREG(EC_REG_BASE_ADDR + 0x3F5D) 101 #define IER23 ECREG(EC_REG_BASE_ADDR + 0x3F91) 102 103 #define IELMR0 ECREG(EC_REG_BASE_ADDR + 0x3F08) 104 #define IELMR1 ECREG(EC_REG_BASE_ADDR + 0x3F09) 105 #define IELMR2 ECREG(EC_REG_BASE_ADDR + 0x3F0A) 106 #define IELMR3 ECREG(EC_REG_BASE_ADDR + 0x3F0B) 107 #define IELMR4 ECREG(EC_REG_BASE_ADDR + 0x3F16) 108 #define IELMR5 ECREG(EC_REG_BASE_ADDR + 0x3F1A) 109 #define IELMR6 ECREG(EC_REG_BASE_ADDR + 0x3F1E) 110 #define IELMR7 ECREG(EC_REG_BASE_ADDR + 0x3F22) 111 #define IELMR8 ECREG(EC_REG_BASE_ADDR + 0x3F26) 112 #define IELMR9 ECREG(EC_REG_BASE_ADDR + 0x3F2A) 113 #define IELMR10 ECREG(EC_REG_BASE_ADDR + 0x3F2E) 114 #define IELMR11 ECREG(EC_REG_BASE_ADDR + 0x3F32) 115 #define IELMR12 ECREG(EC_REG_BASE_ADDR + 0x3F36) 116 #define IELMR13 ECREG(EC_REG_BASE_ADDR + 0x3F3A) 117 #define IELMR14 ECREG(EC_REG_BASE_ADDR + 0x3F3E) 118 #define IELMR15 ECREG(EC_REG_BASE_ADDR + 0x3F42) 119 #define IELMR16 ECREG(EC_REG_BASE_ADDR + 0x3F46) 120 #define IELMR17 ECREG(EC_REG_BASE_ADDR + 0x3F4A) 121 #define IELMR18 ECREG(EC_REG_BASE_ADDR + 0x3F4E) 122 #define IELMR19 ECREG(EC_REG_BASE_ADDR + 0x3F52) 123 #define IELMR20 ECREG(EC_REG_BASE_ADDR + 0x3F56) 124 #define IELMR21 ECREG(EC_REG_BASE_ADDR + 0x3F5A) 125 #define IELMR22 ECREG(EC_REG_BASE_ADDR + 0x3F5E) 126 #define IELMR23 ECREG(EC_REG_BASE_ADDR + 0x3F92) 127 128 #define IPOLR0 ECREG(EC_REG_BASE_ADDR + 0x3F0C) 129 #define IPOLR1 ECREG(EC_REG_BASE_ADDR + 0x3F0D) 130 #define IPOLR2 ECREG(EC_REG_BASE_ADDR + 0x3F0E) 131 #define IPOLR3 ECREG(EC_REG_BASE_ADDR + 0x3F0F) 132 #define IPOLR4 ECREG(EC_REG_BASE_ADDR + 0x3F17) 133 #define IPOLR5 ECREG(EC_REG_BASE_ADDR + 0x3F1B) 134 #define IPOLR6 ECREG(EC_REG_BASE_ADDR + 0x3F1F) 135 #define IPOLR7 ECREG(EC_REG_BASE_ADDR + 0x3F23) 136 #define IPOLR8 ECREG(EC_REG_BASE_ADDR + 0x3F27) 137 #define IPOLR9 ECREG(EC_REG_BASE_ADDR + 0x3F2B) 138 #define IPOLR10 ECREG(EC_REG_BASE_ADDR + 0x3F2F) 139 #define IPOLR11 ECREG(EC_REG_BASE_ADDR + 0x3F33) 140 #define IPOLR12 ECREG(EC_REG_BASE_ADDR + 0x3F37) 141 #define IPOLR13 ECREG(EC_REG_BASE_ADDR + 0x3F3B) 142 #define IPOLR14 ECREG(EC_REG_BASE_ADDR + 0x3F3F) 143 #define IPOLR15 ECREG(EC_REG_BASE_ADDR + 0x3F43) 144 #define IPOLR16 ECREG(EC_REG_BASE_ADDR + 0x3F47) 145 #define IPOLR17 ECREG(EC_REG_BASE_ADDR + 0x3F4B) 146 #define IPOLR18 ECREG(EC_REG_BASE_ADDR + 0x3F4F) 147 #define IPOLR19 ECREG(EC_REG_BASE_ADDR + 0x3F53) 148 #define IPOLR20 ECREG(EC_REG_BASE_ADDR + 0x3F57) 149 #define IPOLR21 ECREG(EC_REG_BASE_ADDR + 0x3F5B) 150 #define IPOLR22 ECREG(EC_REG_BASE_ADDR + 0x3F5F) 151 #define IPOLR23 ECREG(EC_REG_BASE_ADDR + 0x3F93) 152 153 #define IVECT ECREG(EC_REG_BASE_ADDR + 0x3F10) 154 155 156 /* 157 * TODO: use pinctrl node instead of following register declarations 158 * to fix in tcpm\it83xx_pd.h. 159 */ 160 /* GPIO control register */ 161 #define GPCRF4 ECREG(EC_REG_BASE_ADDR + 0x163C) 162 #define GPCRF5 ECREG(EC_REG_BASE_ADDR + 0x163D) 163 #define GPCRH1 ECREG(EC_REG_BASE_ADDR + 0x1649) 164 #define GPCRH2 ECREG(EC_REG_BASE_ADDR + 0x164A) 165 166 /* 167 * IT8XXX2 register structure size/offset checking macro function to mitigate 168 * the risk of unexpected compiling results. 169 */ 170 #define IT8XXX2_REG_SIZE_CHECK(reg_def, size) \ 171 BUILD_ASSERT(sizeof(struct reg_def) == size, \ 172 "Failed in size check of register structure!") 173 #define IT8XXX2_REG_OFFSET_CHECK(reg_def, member, offset) \ 174 BUILD_ASSERT(offsetof(struct reg_def, member) == offset, \ 175 "Failed in offset check of register structure member!") 176 177 /** 178 * 179 * (18xxh) PWM & SmartAuto Fan Control (PWM) 180 * 181 */ 182 #ifndef __ASSEMBLER__ 183 struct pwm_it8xxx2_regs { 184 /* 0x000: Channel0 Clock Prescaler */ 185 volatile uint8_t C0CPRS; 186 /* 0x001: Cycle Time0 */ 187 volatile uint8_t CTR; 188 /* 0x002~0x00A: Reserved1 */ 189 volatile uint8_t Reserved1[9]; 190 /* 0x00B: Prescaler Clock Frequency Select */ 191 volatile uint8_t PCFSR; 192 /* 0x00C~0x00F: Reserved2 */ 193 volatile uint8_t Reserved2[4]; 194 /* 0x010: Cycle Time1 MSB */ 195 volatile uint8_t CTR1M; 196 /* 0x011~0x022: Reserved3 */ 197 volatile uint8_t Reserved3[18]; 198 /* 0x023: PWM Clock Control */ 199 volatile uint8_t ZTIER; 200 /* 0x024~0x026: Reserved4 */ 201 volatile uint8_t Reserved4[3]; 202 /* 0x027: Channel4 Clock Prescaler */ 203 volatile uint8_t C4CPRS; 204 /* 0x028: Channel4 Clock Prescaler MSB */ 205 volatile uint8_t C4MCPRS; 206 /* 0x029~0x02A: Reserved5 */ 207 volatile uint8_t Reserved5[2]; 208 /* 0x02B: Channel6 Clock Prescaler */ 209 volatile uint8_t C6CPRS; 210 /* 0x02C: Channel6 Clock Prescaler MSB */ 211 volatile uint8_t C6MCPRS; 212 /* 0x02D: Channel7 Clock Prescaler */ 213 volatile uint8_t C7CPRS; 214 /* 0x02E: Channel7 Clock Prescaler MSB */ 215 volatile uint8_t C7MCPRS; 216 /* 0x02F~0x040: Reserved6 */ 217 volatile uint8_t reserved6[18]; 218 /* 0x041: Cycle Time1 */ 219 volatile uint8_t CTR1; 220 /* 0x042: Cycle Time2 */ 221 volatile uint8_t CTR2; 222 /* 0x043: Cycle Time3 */ 223 volatile uint8_t CTR3; 224 }; 225 #endif /* !__ASSEMBLER__ */ 226 227 /* PWM register fields */ 228 /* 0x023: PWM Clock Control */ 229 #define IT8XXX2_PWM_PCCE BIT(1) 230 /* 0x048: Tachometer Switch Control */ 231 #define IT8XXX2_PWM_T0DVS BIT(3) 232 #define IT8XXX2_PWM_T0CHSEL BIT(2) 233 #define IT8XXX2_PWM_T1DVS BIT(1) 234 #define IT8XXX2_PWM_T1CHSEL BIT(0) 235 236 237 /* --- Wake-Up Control (WUC) --- */ 238 #define IT8XXX2_WUC_BASE 0x00F01B00 239 240 /* TODO: should a defined interface for configuring wake-up interrupts */ 241 #define IT8XXX2_WUC_WUEMR1 (IT8XXX2_WUC_BASE + 0x00) 242 #define IT8XXX2_WUC_WUEMR5 (IT8XXX2_WUC_BASE + 0x0c) 243 #define IT8XXX2_WUC_WUESR1 (IT8XXX2_WUC_BASE + 0x04) 244 #define IT8XXX2_WUC_WUESR5 (IT8XXX2_WUC_BASE + 0x0d) 245 #define IT8XXX2_WUC_WUBEMR1 (IT8XXX2_WUC_BASE + 0x3c) 246 #define IT8XXX2_WUC_WUBEMR5 (IT8XXX2_WUC_BASE + 0x0f) 247 248 /** 249 * 250 * (1Dxxh) Keyboard Matrix Scan control (KSCAN) 251 * 252 */ 253 #ifndef __ASSEMBLER__ 254 struct kscan_it8xxx2_regs { 255 /* 0x000: Keyboard Scan Out */ 256 volatile uint8_t KBS_KSOL; 257 /* 0x001: Keyboard Scan Out */ 258 volatile uint8_t KBS_KSOH1; 259 /* 0x002: Keyboard Scan Out Control */ 260 volatile uint8_t KBS_KSOCTRL; 261 /* 0x003: Keyboard Scan Out */ 262 volatile uint8_t KBS_KSOH2; 263 /* 0x004: Keyboard Scan In */ 264 volatile uint8_t KBS_KSI; 265 /* 0x005: Keyboard Scan In Control */ 266 volatile uint8_t KBS_KSICTRL; 267 /* 0x006: Keyboard Scan In [7:0] GPIO Control */ 268 volatile uint8_t KBS_KSIGCTRL; 269 /* 0x007: Keyboard Scan In [7:0] GPIO Output Enable */ 270 volatile uint8_t KBS_KSIGOEN; 271 /* 0x008: Keyboard Scan In [7:0] GPIO Data */ 272 volatile uint8_t KBS_KSIGDAT; 273 /* 0x009: Keyboard Scan In [7:0] GPIO Data Mirror */ 274 volatile uint8_t KBS_KSIGDMRR; 275 /* 0x00A: Keyboard Scan Out [15:8] GPIO Control */ 276 volatile uint8_t KBS_KSOHGCTRL; 277 /* 0x00B: Keyboard Scan Out [15:8] GPIO Output Enable */ 278 volatile uint8_t KBS_KSOHGOEN; 279 /* 0x00C: Keyboard Scan Out [15:8] GPIO Data Mirror */ 280 volatile uint8_t KBS_KSOHGDMRR; 281 /* 0x00D: Keyboard Scan Out [7:0] GPIO Control */ 282 volatile uint8_t KBS_KSOLGCTRL; 283 /* 0x00E: Keyboard Scan Out [7:0] GPIO Output Enable */ 284 volatile uint8_t KBS_KSOLGOEN; 285 }; 286 #endif /* !__ASSEMBLER__ */ 287 288 /* KBS register fields */ 289 /* 0x002: Keyboard Scan Out Control */ 290 #define IT8XXX2_KBS_KSOPU BIT(2) 291 #define IT8XXX2_KBS_KSOOD BIT(0) 292 /* 0x005: Keyboard Scan In Control */ 293 #define IT8XXX2_KBS_KSIPU BIT(2) 294 /* 0x00D: Keyboard Scan Out [7:0] GPIO Control */ 295 #define IT8XXX2_KBS_KSO2GCTRL BIT(2) 296 /* 0x00E: Keyboard Scan Out [7:0] GPIO Output Enable */ 297 #define IT8XXX2_KBS_KSO2GOEN BIT(2) 298 299 300 /** 301 * 302 * (1Fxxh) External Timer & External Watchdog (ETWD) 303 * 304 */ 305 #ifndef __ASSEMBLER__ 306 struct wdt_it8xxx2_regs { 307 /* 0x000: Reserved1 */ 308 volatile uint8_t reserved1; 309 /* 0x001: External Timer1/WDT Configuration */ 310 volatile uint8_t ETWCFG; 311 /* 0x002: External Timer1 Prescaler */ 312 volatile uint8_t ET1PSR; 313 /* 0x003: External Timer1 Counter High Byte */ 314 volatile uint8_t ET1CNTLHR; 315 /* 0x004: External Timer1 Counter Low Byte */ 316 volatile uint8_t ET1CNTLLR; 317 /* 0x005: External Timer1/WDT Control */ 318 volatile uint8_t ETWCTRL; 319 /* 0x006: External WDT Counter Low Byte */ 320 volatile uint8_t EWDCNTLR; 321 /* 0x007: External WDT Key */ 322 volatile uint8_t EWDKEYR; 323 /* 0x008: Reserved2 */ 324 volatile uint8_t reserved2; 325 /* 0x009: External WDT Counter High Byte */ 326 volatile uint8_t EWDCNTHR; 327 /* 0x00A: External Timer2 Prescaler */ 328 volatile uint8_t ET2PSR; 329 /* 0x00B: External Timer2 Counter High Byte */ 330 volatile uint8_t ET2CNTLHR; 331 /* 0x00C: External Timer2 Counter Low Byte */ 332 volatile uint8_t ET2CNTLLR; 333 /* 0x00D: Reserved3 */ 334 volatile uint8_t reserved3; 335 /* 0x00E: External Timer2 Counter High Byte2 */ 336 volatile uint8_t ET2CNTLH2R; 337 }; 338 #endif /* !__ASSEMBLER__ */ 339 340 /* WDT register fields */ 341 /* 0x001: External Timer1/WDT Configuration */ 342 #define IT8XXX2_WDT_EWDKEYEN BIT(5) 343 #define IT8XXX2_WDT_EWDSRC BIT(4) 344 #define IT8XXX2_WDT_LEWDCNTL BIT(3) 345 #define IT8XXX2_WDT_LET1CNTL BIT(2) 346 #define IT8XXX2_WDT_LET1PS BIT(1) 347 #define IT8XXX2_WDT_LETWCFG BIT(0) 348 /* 0x002: External Timer1 Prescaler */ 349 #define IT8XXX2_WDT_ETPS_32P768_KHZ 0x00 350 #define IT8XXX2_WDT_ETPS_1P024_KHZ 0x01 351 #define IT8XXX2_WDT_ETPS_32_HZ 0x02 352 /* 0x005: External Timer1/WDT Control */ 353 #define IT8XXX2_WDT_EWDSCEN BIT(5) 354 #define IT8XXX2_WDT_EWDSCMS BIT(4) 355 #define IT8XXX2_WDT_ET2TC BIT(3) 356 #define IT8XXX2_WDT_ET2RST BIT(2) 357 #define IT8XXX2_WDT_ET1TC BIT(1) 358 #define IT8XXX2_WDT_ET1RST BIT(0) 359 360 /* External Timer register fields */ 361 /* External Timer 3~8 control */ 362 #define IT8XXX2_EXT_ETX_COMB_RST_EN (IT8XXX2_EXT_ETXCOMB | \ 363 IT8XXX2_EXT_ETXRST | \ 364 IT8XXX2_EXT_ETXEN) 365 #define IT8XXX2_EXT_ETXCOMB BIT(3) 366 #define IT8XXX2_EXT_ETXRST BIT(1) 367 #define IT8XXX2_EXT_ETXEN BIT(0) 368 369 /* Control external timer3~8 */ 370 #define IT8XXX2_EXT_TIMER_BASE DT_REG_ADDR(DT_NODELABEL(timer)) /*0x00F01F10*/ 371 #define IT8XXX2_EXT_CTRLX(n) ECREG(IT8XXX2_EXT_TIMER_BASE + (n << 3)) 372 #define IT8XXX2_EXT_PSRX(n) ECREG(IT8XXX2_EXT_TIMER_BASE + 0x01 + (n << 3)) 373 #define IT8XXX2_EXT_CNTX(n) ECREG_u32(IT8XXX2_EXT_TIMER_BASE + 0x04 + \ 374 (n << 3)) 375 #define IT8XXX2_EXT_CNTOX(n) ECREG_u32(IT8XXX2_EXT_TIMER_BASE + 0x38 + \ 376 (n << 2)) 377 378 /* Free run timer configurations */ 379 #define FREE_RUN_TIMER EXT_TIMER_4 380 #define FREE_RUN_TIMER_IRQ DT_IRQ_BY_IDX(DT_NODELABEL(timer), 1, irq) 381 /* Free run timer configurations */ 382 #define FREE_RUN_TIMER_FLAG DT_IRQ_BY_IDX(DT_NODELABEL(timer), 1, flags) 383 /* Free run timer max count is 36.4 hr (base on clock source 32768Hz) */ 384 #define FREE_RUN_TIMER_MAX_CNT 0xFFFFFFFFUL 385 386 #ifndef __ASSEMBLER__ 387 enum ext_clk_src_sel { 388 EXT_PSR_32P768K = 0, 389 EXT_PSR_1P024K, 390 EXT_PSR_32, 391 EXT_PSR_8M, 392 }; 393 /* 394 * 24-bit timers: external timer 3, 5, and 7 395 * 32-bit timers: external timer 4, 6, and 8 396 */ 397 enum ext_timer_idx { 398 EXT_TIMER_3 = 0, /* Event timer */ 399 EXT_TIMER_4, /* Free run timer */ 400 EXT_TIMER_5, /* Busy wait low timer */ 401 EXT_TIMER_6, /* Busy wait high timer */ 402 EXT_TIMER_7, 403 EXT_TIMER_8, 404 }; 405 #endif 406 407 408 /* 409 * 410 * (2Cxxh) Platform Environment Control Interface (PECI) 411 * 412 */ 413 #ifndef __ASSEMBLER__ 414 struct peci_it8xxx2_regs { 415 /* 0x00: Host Status */ 416 volatile uint8_t HOSTAR; 417 /* 0x01: Host Control */ 418 volatile uint8_t HOCTLR; 419 /* 0x02: Host Command */ 420 volatile uint8_t HOCMDR; 421 /* 0x03: Host Target Address */ 422 volatile uint8_t HOTRADDR; 423 /* 0x04: Host Write Length */ 424 volatile uint8_t HOWRLR; 425 /* 0x05: Host Read Length */ 426 volatile uint8_t HORDLR; 427 /* 0x06: Host Write Data */ 428 volatile uint8_t HOWRDR; 429 /* 0x07: Host Read Data */ 430 volatile uint8_t HORDDR; 431 /* 0x08: Host Control 2 */ 432 volatile uint8_t HOCTL2R; 433 /* 0x09: Received Write FCS value */ 434 volatile uint8_t RWFCSV; 435 /* 0x0A: Received Read FCS value */ 436 volatile uint8_t RRFCSV; 437 /* 0x0B: Write FCS Value */ 438 volatile uint8_t WFCSV; 439 /* 0x0C: Read FCS Value */ 440 volatile uint8_t RFCSV; 441 /* 0x0D: Assured Write FCS Value */ 442 volatile uint8_t AWFCSV; 443 /* 0x0E: Pad Control */ 444 volatile uint8_t PADCTLR; 445 }; 446 #endif /* !__ASSEMBLER__ */ 447 448 /** 449 * 450 * (2Fxxh) USB Device Controller (USBDC) Registers 451 * 452 */ 453 #define EP_EXT_REGS_9X 1 454 #define EP_EXT_REGS_BX 2 455 #define EP_EXT_REGS_DX 3 456 457 #ifndef __ASSEMBLER__ 458 459 /* EP0 to EP15 Enumeration */ 460 enum usb_dc_endpoints { 461 EP0, 462 EP1, 463 EP2, 464 EP3, 465 EP4, 466 EP5, 467 EP6, 468 EP7, 469 EP8, 470 EP9, 471 EP10, 472 EP11, 473 EP12, 474 EP13, 475 EP14, 476 EP15 477 }; 478 479 struct it82xx2_usb_ep_regs { 480 volatile uint8_t ep_ctrl; 481 volatile uint8_t ep_status; 482 volatile uint8_t ep_transtype_sts; 483 volatile uint8_t ep_nak_transtype_sts; 484 }; 485 486 /* Reserved EP Extended Registers */ 487 struct ep_ext_regs_7x { 488 /* 0x75 Reserved */ 489 volatile uint8_t ep_ext_ctrl_75; 490 /* 0x76 Reserved */ 491 volatile uint8_t ep_ext_ctrl_76; 492 /* 0x77 Reserved */ 493 volatile uint8_t ep_ext_ctrl_77; 494 /* 0x78 Reserved */ 495 volatile uint8_t ep_ext_ctrl_78; 496 /* 0x79 Reserved */ 497 volatile uint8_t ep_ext_ctrl_79; 498 /* 0x7A Reserved */ 499 volatile uint8_t ep_ext_ctrl_7a; 500 /* 0x7B Reserved */ 501 volatile uint8_t ep_ext_ctrl_7b; 502 /* 0x7C Reserved */ 503 volatile uint8_t ep_ext_ctrl_7c; 504 /* 0x7D Reserved */ 505 volatile uint8_t ep_ext_ctrl_7d; 506 /* 0x7E Reserved */ 507 volatile uint8_t ep_ext_ctrl_7e; 508 /* 0x7F Reserved */ 509 volatile uint8_t ep_ext_ctrl_7f; 510 }; 511 512 /* From 98h to 9Dh, the EP45/67/89/1011/1213/1415 Extended Control Registers 513 * are defined, and their bits definitions are as follows: 514 * 515 * Bit Description 516 * 7 Reserved 517 * 6 EPPOINT5_ISO_ENABLE 518 * 5 EPPOINT5_SEND_STALL 519 * 4 EPPOINT5_OUT_DATA_SEQUENCE 520 * 3 Reserved 521 * 2 EPPOINT4_ISO_ENABLE 522 * 1 EPPOINT4_SEND_STALL 523 * 0 EPPOINT4_OUT_DATA_SEQUENCE 524 * 525 * Apparently, we can tell that the EP4 and EP5 share the same register, and 526 * the EP6 and EP7 share the same one, and the rest EPs are defined in the 527 * same way. 528 */ 529 struct ep_ext_regs_9x { 530 /* 0x95 Reserved */ 531 volatile uint8_t ep_ext_ctrl_95; 532 /* 0x96 Reserved */ 533 volatile uint8_t ep_ext_ctrl_96; 534 /* 0x97 Reserved */ 535 volatile uint8_t ep_ext_ctrl_97; 536 /* 0x98 ~ 0x9D EP45/67/89/1011/1213/1415 Extended Control Registers */ 537 volatile uint8_t epn0n1_ext_ctrl[6]; 538 /* 0x9E Reserved */ 539 volatile uint8_t ep_ext_ctrl_9e; 540 /* 0x9F Reserved */ 541 volatile uint8_t ep_ext_ctrl_9f; 542 }; 543 544 /* From BXh to BDh are EP FIFO 1-3 Control 0/1 Registers, and their 545 * definitions as as follows: 546 * B8h: EP_FIFO1_CONTROL0_REG 547 * B9h: EP_FIFO1_CONTROL1_REG 548 * BAh: EP_FIFO2_CONTROL0_REG 549 * BBh: EP_FIFO2_CONTROL1_REG 550 * BCh: EP_FIFO3_CONTROL0_REG 551 * BDh: EP_FIFO3_CONTROL1_REG 552 * 553 * For each one, its bits definitions are as follows: 554 * (take EP_FIFO1_CONTROL1_REG as example, which controls from EP8 to EP15) 555 * 556 * Bit Description 557 * 558 * 7 EP15 select FIFO1 as data buffer 559 * 6 EP14 select FIFO1 as data buffer 560 * 5 EP13 select FIFO1 as data buffer 561 * 4 EP12 select FIFO1 as data buffer 562 * 3 EP11 select FIFO1 as data buffer 563 * 2 EP10 select FIFO1 as data buffer 564 * 1 EP9 select FIFO1 as data buffer 565 * 0 EP8 select FIFO1 as data buffer 566 * 567 * 1: Select 568 * 0: Not select 569 */ 570 struct ep_ext_regs_bx { 571 /* 0xB5 Reserved */ 572 volatile uint8_t ep_ext_ctrl_b5; 573 /* 0xB6 Reserved */ 574 volatile uint8_t ep_ext_ctrl_b6; 575 /* 0xB7 Reserved */ 576 volatile uint8_t ep_ext_ctrl_b7; 577 /* 0xB8 ~ 0xBD EP FIFO 1-3 Control 0/1 Registers */ 578 volatile uint8_t ep_fifo_ctrl[6]; 579 /* 0xBE Reserved */ 580 volatile uint8_t ep_ext_ctrl_be; 581 /* 0xBF Reserved */ 582 volatile uint8_t ep_ext_ctrl_bf; 583 }; 584 585 586 /* From D6h to DDh are EP Extended Control Registers, and their 587 * definitions as as follows: 588 * D6h: EP0_EXT_CTRL1 589 * D7h: EP0_EXT_CTRL2 590 * D8h: EP1_EXT_CTRL1 591 * D9h: EP1_EXT_CTRL2 592 * DAh: EP2_EXT_CTRL1 593 * DBh: EP2_EXT_CTRL2 594 * DCh: EP3_EXT_CTRL1 595 * DDh: EP3_EXT_CTRL2 596 * 597 * We classify them into 4 groups which each of them contains Control 1 and 2 598 * according to the EP number as follows: 599 */ 600 struct epn_ext_ctrl_regs { 601 /* 0xD6/0xD8/0xDA/0xDC EPN Extended Control1 Register */ 602 volatile uint8_t epn_ext_ctrl1; 603 /* 0xD7/0xD9/0xDB/0xDD EPB Extended Control2 Register */ 604 volatile uint8_t epn_ext_ctrl2; 605 }; 606 607 struct ep_ext_regs_dx { 608 /* 0xD5 Reserved */ 609 volatile uint8_t ep_ext_ctrl_d5; 610 /* 0xD6 ~ 0xDD EPN Extended Control 1/2 Registers */ 611 struct epn_ext_ctrl_regs epn_ext_ctrl[4]; 612 /* 0xDE Reserved */ 613 volatile uint8_t ep_ext_ctrl_de; 614 /* 0xDF Reserved */ 615 volatile uint8_t ep_ext_ctrl_df; 616 }; 617 618 619 /* The USB EPx FIFO Registers Definitions 620 * EP0: 60h ~ 74h 621 * EP1: 80h ~ 94h 622 * EP2: A0h ~ B4h 623 * EP3: C0h ~ D4h (D6h to DDh will be defined as marcos for usage) 624 */ 625 struct it82xx2_usb_ep_fifo_regs { 626 /* 0x60 + ep * 0x20 : EP RX FIFO Data Register */ 627 volatile uint8_t ep_rx_fifo_data; 628 /* 0x61 + ep * 0x20 : EP RX FIFO DMA Count Register */ 629 volatile uint8_t ep_rx_fifo_dma_count; 630 /* 0x62 + ep * 0x20 : EP RX FIFO Data Count MSB */ 631 volatile uint8_t ep_rx_fifo_dcnt_msb; 632 /* 0x63 + ep * 0x20 : EP RX FIFO Data Count LSB */ 633 volatile uint8_t ep_rx_fifo_dcnt_lsb; 634 /* 0x64 + ep * 0x20 : EP RX FIFO Control Register */ 635 volatile uint8_t ep_rx_fifo_ctrl; 636 /* (0x65 ~ 0x6F) + ep * 0x20 */ 637 volatile uint8_t reserved_65_6f_add_20[11]; 638 /* 0x70 + ep * 0x20 : EP TX FIFO Data Register */ 639 volatile uint8_t ep_tx_fifo_data; 640 /* (0x71 ~ 0x73) + ep * 0x20 */ 641 volatile uint8_t reserved_71_73_add_20[3]; 642 /* 0x74 + ep * 0x20 : EP TX FIFO Control Register */ 643 volatile uint8_t ep_tx_fifo_ctrl; 644 /* (0x75 ~ 0x7F) + ep * 0x20 */ 645 union { 646 struct ep_ext_regs_7x ep_res; 647 struct ep_ext_regs_9x ext_4_15; 648 struct ep_ext_regs_bx fifo_ctrl; 649 struct ep_ext_regs_dx ext_0_3; 650 }; 651 652 }; 653 654 struct usb_it82xx2_regs { 655 /* 0x00: Host TX Contrl Register */ 656 volatile uint8_t host_tx_ctrl; 657 /* 0x01: Host TX Transaction Type Register */ 658 volatile uint8_t host_tx_trans_type; 659 /* 0x02: Host TX Line Control Register */ 660 volatile uint8_t host_tx_line_ctrl; 661 /* 0x03: Host TX SOF Enable Register */ 662 volatile uint8_t host_tx_sof_enable; 663 /* 0x04: Host TX Address Register */ 664 volatile uint8_t host_tx_addr; 665 /* 0x05: Host TX EP Number Register */ 666 volatile uint8_t host_tx_endp; 667 /* 0x06: Host Frame Number MSP Register */ 668 volatile uint8_t host_frame_num_msp; 669 /* 0x07: Host Frame Number LSP Register */ 670 volatile uint8_t host_frame_num_lsp; 671 /* 0x08: Host Interrupt Status Register */ 672 volatile uint8_t host_interrupt_status; 673 /* 0x09: Host Interrupt Mask Register */ 674 volatile uint8_t host_interrupt_mask; 675 /* 0x0A: Host RX Status Register */ 676 volatile uint8_t host_rx_status; 677 /* 0x0B: Host RX PID Register */ 678 volatile uint8_t host_rx_pid; 679 /* 0x0C: MISC Control Register */ 680 volatile uint8_t misc_control; 681 /* 0x0D: MISC Status Register */ 682 volatile uint8_t misc_status; 683 /* 0x0E: Host RX Connect State Register */ 684 volatile uint8_t host_rx_connect_state; 685 /* 0x0F: Host SOF Timer MSB Register */ 686 volatile uint8_t host_sof_timer_msb; 687 /* 0x10 ~ 0x1F: Reserved Registers 10h - 1Fh */ 688 volatile uint8_t reserved_10_1f[16]; 689 /* 0x20: Host RX FIFO Data Port Register */ 690 volatile uint8_t host_rx_fifo_data; 691 /* 0x21: Host RX FIFO DMA Input Data Count Register */ 692 volatile uint8_t host_rx_fifo_dma_data_count; 693 /* 0x22: Host TX FIFO Data Count MSB Register */ 694 volatile uint8_t host_rx_fifo_data_count_msb; 695 /* 0x23: Host TX FIFO Data Count LSB Register */ 696 volatile uint8_t host_rx_fifo_data_count_lsb; 697 /* 0x24: Host RX FIFO Data Port Register */ 698 volatile uint8_t host_rx_fifo_control; 699 /* 0x25 ~ 0x2F: Reserved Registers 25h - 2Fh */ 700 volatile uint8_t reserved_25_2f[11]; 701 /* 0x30: Host TX FIFO Data Port Register */ 702 volatile uint8_t host_tx_fifo_data; 703 /* 0x31 ~ 0x3F: Reserved Registers 31h - 3Fh */ 704 volatile uint8_t reserved_31_3f[15]; 705 /* 0x40 ~ 0x4F: Endpoint Registers 40h - 4Fh */ 706 struct it82xx2_usb_ep_regs usb_ep_regs[4]; 707 /* 0x50: Device Controller Control Register */ 708 volatile uint8_t dc_control; 709 /* 0x51: Device Controller LINE Status Register */ 710 volatile uint8_t dc_line_status; 711 /* 0x52: Device Controller Interrupt Status Register */ 712 volatile uint8_t dc_interrupt_status; 713 /* 0x53: Device Controller Interrupt Mask Register */ 714 volatile uint8_t dc_interrupt_mask; 715 /* 0x54: Device Controller Address Register */ 716 volatile uint8_t dc_address; 717 /* 0x55: Device Controller Frame Number MSP Register */ 718 volatile uint8_t dc_frame_num_msp; 719 /* 0x56: Device Controller Frame Number LSP Register */ 720 volatile uint8_t dc_frame_num_lsp; 721 /* 0x57 ~ 0x5F: Reserved Registers 57h - 5Fh */ 722 volatile uint8_t reserved_57_5f[9]; 723 /* 0x60 ~ 0xDF: EP FIFO Registers 60h - DFh */ 724 struct it82xx2_usb_ep_fifo_regs fifo_regs[4]; 725 /* 0xE0: Host/Device Control Register */ 726 volatile uint8_t host_device_control; 727 /* 0xE1 ~ 0xE3: Reserved Registers E1h - E3h */ 728 volatile uint8_t reserved_e1_e3[3]; 729 /* 0xE4: Port0 MISC Control Register */ 730 volatile uint8_t port0_misc_control; 731 /* 0xE5 ~ 0xE7: Reserved Registers E5h - E7h */ 732 volatile uint8_t reserved_e5_e7[3]; 733 /* 0xE8: Port1 MISC Control Register */ 734 volatile uint8_t port1_misc_control; 735 }; 736 #endif /* #ifndef __ASSEMBLER__ */ 737 738 /** 739 * 740 * (37xxh, 38xxh) USBPD Controller 741 * 742 */ 743 #ifndef __ASSEMBLER__ 744 struct usbpd_it8xxx2_regs { 745 /* 0x000~0x003: Reserved1 */ 746 volatile uint8_t Reserved1[4]; 747 /* 0x004: CC General Configuration */ 748 volatile uint8_t CCGCR; 749 /* 0x005: CC Channel Setting */ 750 volatile uint8_t CCCSR; 751 /* 0x006: CC Pad Setting */ 752 volatile uint8_t CCPSR; 753 }; 754 #endif /* !__ASSEMBLER__ */ 755 756 /* USBPD controller register fields */ 757 /* 0x004: CC General Configuration */ 758 #define IT8XXX2_USBPD_DISABLE_CC BIT(7) 759 #define IT8XXX2_USBPD_DISABLE_CC_VOL_DETECTOR BIT(6) 760 #define IT8XXX2_USBPD_CC_SELECT_RP_RESERVED (BIT(3) | BIT(2) | BIT(1)) 761 #define IT8XXX2_USBPD_CC_SELECT_RP_DEF (BIT(3) | BIT(2)) 762 #define IT8XXX2_USBPD_CC_SELECT_RP_1A5 BIT(3) 763 #define IT8XXX2_USBPD_CC_SELECT_RP_3A0 BIT(2) 764 #define IT8XXX2_USBPD_CC1_CC2_SELECTION BIT(0) 765 /* 0x005: CC Channel Setting */ 766 #define IT8XXX2_USBPD_CC2_DISCONNECT BIT(7) 767 #define IT8XXX2_USBPD_CC2_DISCONNECT_5_1K_TO_GND BIT(6) 768 #define IT8XXX2_USBPD_CC1_DISCONNECT BIT(3) 769 #define IT8XXX2_USBPD_CC1_DISCONNECT_5_1K_TO_GND BIT(2) 770 #define IT8XXX2_USBPD_CC1_CC2_RP_RD_SELECT (BIT(1) | BIT(5)) 771 /* 0x006: CC Pad Setting */ 772 #define IT8XXX2_USBPD_DISCONNECT_5_1K_CC2_DB BIT(6) 773 #define IT8XXX2_USBPD_DISCONNECT_POWER_CC2 BIT(5) 774 #define IT8XXX2_USBPD_DISCONNECT_5_1K_CC1_DB BIT(2) 775 #define IT8XXX2_USBPD_DISCONNECT_POWER_CC1 BIT(1) 776 777 778 /** 779 * 780 * (10xxh) Shared Memory Flash Interface Bridge (SMFI) registers 781 * 782 */ 783 #ifndef __ASSEMBLER__ 784 struct smfi_it8xxx2_regs { 785 volatile uint8_t reserved1[59]; 786 /* 0x3B: EC-Indirect memory address 0 */ 787 volatile uint8_t SMFI_ECINDAR0; 788 /* 0x3C: EC-Indirect memory address 1 */ 789 volatile uint8_t SMFI_ECINDAR1; 790 /* 0x3D: EC-Indirect memory address 2 */ 791 volatile uint8_t SMFI_ECINDAR2; 792 /* 0x3E: EC-Indirect memory address 3 */ 793 volatile uint8_t SMFI_ECINDAR3; 794 /* 0x3F: EC-Indirect memory data */ 795 volatile uint8_t SMFI_ECINDDR; 796 /* 0x40: Scratch SRAM 0 address low byte */ 797 volatile uint8_t SMFI_SCAR0L; 798 /* 0x41: Scratch SRAM 0 address middle byte */ 799 volatile uint8_t SMFI_SCAR0M; 800 /* 0x42: Scratch SRAM 0 address high byte */ 801 volatile uint8_t SMFI_SCAR0H; 802 volatile uint8_t reserved1_1[23]; 803 /* 0x5A: Host RAM Window Control */ 804 volatile uint8_t SMFI_HRAMWC; 805 /* 0x5B: Host RAM Window 0 Base Address [11:4] */ 806 volatile uint8_t SMFI_HRAMW0BA; 807 /* 0x5C: Host RAM Window 1 Base Address [11:4] */ 808 volatile uint8_t SMFI_HRAMW1BA; 809 /* 0x5D: Host RAM Window 0 Access Allow Size */ 810 volatile uint8_t SMFI_HRAMW0AAS; 811 /* 0x5E: Host RAM Window 1 Access Allow Size */ 812 volatile uint8_t SMFI_HRAMW1AAS; 813 volatile uint8_t reserved2[67]; 814 /* 0xA2: Flash control 6 */ 815 volatile uint8_t SMFI_FLHCTRL6R; 816 volatile uint8_t reserved3[46]; 817 }; 818 #endif /* !__ASSEMBLER__ */ 819 820 /* SMFI register fields */ 821 /* EC-Indirect read internal flash */ 822 #define EC_INDIRECT_READ_INTERNAL_FLASH BIT(6) 823 /* Enable EC-indirect page program command */ 824 #define IT8XXX2_SMFI_MASK_ECINDPP BIT(3) 825 /* Scratch SRAM 0 address(BIT(19)) */ 826 #define IT8XXX2_SMFI_SC0A19 BIT(7) 827 /* Scratch SRAM enable */ 828 #define IT8XXX2_SMFI_SCAR0H_ENABLE BIT(3) 829 830 /* H2RAM Path Select. 1b: H2RAM through LPC IO cycle. */ 831 #define SMFI_H2RAMPS BIT(4) 832 /* H2RAM Window 1 Enable */ 833 #define SMFI_H2RAMW1E BIT(1) 834 /* H2RAM Window 0 Enable */ 835 #define SMFI_H2RAMW0E BIT(0) 836 837 /* Host RAM Window x Write Protect Enable (All protected) */ 838 #define SMFI_HRAMWXWPE_ALL (BIT(5) | BIT(4)) 839 840 841 /** 842 * 843 * (16xxh) General Purpose I/O Port (GPIO) registers 844 * 845 */ 846 #define GPIO_IT8XXX2_REG_BASE \ 847 ((struct gpio_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(gpiogcr))) 848 849 #ifndef __ASSEMBLER__ 850 #ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1 851 struct gpio_it8xxx2_regs { 852 /* 0x00: General Control */ 853 volatile uint8_t GPIO_GCR; 854 /* 0x01-D0: Reserved1 */ 855 volatile uint8_t reserved1[208]; 856 /* 0xD1: General Control 25 */ 857 volatile uint8_t GPIO_GCR25; 858 /* 0xD2: General Control 26 */ 859 volatile uint8_t GPIO_GCR26; 860 /* 0xD3: General Control 27 */ 861 volatile uint8_t GPIO_GCR27; 862 /* 0xD4: General Control 28 */ 863 volatile uint8_t GPIO_GCR28; 864 /* 0xD5: General Control 31 */ 865 volatile uint8_t GPIO_GCR31; 866 /* 0xD6: General Control 32 */ 867 volatile uint8_t GPIO_GCR32; 868 /* 0xD7: General Control 33 */ 869 volatile uint8_t GPIO_GCR33; 870 /* 0xD8-0xDF: Reserved2 */ 871 volatile uint8_t reserved2[8]; 872 /* 0xE0: General Control 16 */ 873 volatile uint8_t GPIO_GCR16; 874 /* 0xE1: General Control 17 */ 875 volatile uint8_t GPIO_GCR17; 876 /* 0xE2: General Control 18 */ 877 volatile uint8_t GPIO_GCR18; 878 /* 0xE3: Reserved3 */ 879 volatile uint8_t reserved3; 880 /* 0xE4: General Control 19 */ 881 volatile uint8_t GPIO_GCR19; 882 /* 0xE5: General Control 20 */ 883 volatile uint8_t GPIO_GCR20; 884 /* 0xE6: General Control 21 */ 885 volatile uint8_t GPIO_GCR21; 886 /* 0xE7: General Control 22 */ 887 volatile uint8_t GPIO_GCR22; 888 /* 0xE8: General Control 23 */ 889 volatile uint8_t GPIO_GCR23; 890 /* 0xE9: General Control 24 */ 891 volatile uint8_t GPIO_GCR24; 892 /* 0xEA-0xEC: Reserved4 */ 893 volatile uint8_t reserved4[3]; 894 /* 0xED: General Control 30 */ 895 volatile uint8_t GPIO_GCR30; 896 /* 0xEE: General Control 29 */ 897 volatile uint8_t GPIO_GCR29; 898 /* 0xEF: Reserved5 */ 899 volatile uint8_t reserved5; 900 /* 0xF0: General Control 1 */ 901 volatile uint8_t GPIO_GCR1; 902 /* 0xF1: General Control 2 */ 903 volatile uint8_t GPIO_GCR2; 904 /* 0xF2: General Control 3 */ 905 volatile uint8_t GPIO_GCR3; 906 /* 0xF3: General Control 4 */ 907 volatile uint8_t GPIO_GCR4; 908 /* 0xF4: General Control 5 */ 909 volatile uint8_t GPIO_GCR5; 910 /* 0xF5: General Control 6 */ 911 volatile uint8_t GPIO_GCR6; 912 /* 0xF6: General Control 7 */ 913 volatile uint8_t GPIO_GCR7; 914 /* 0xF7: General Control 8 */ 915 volatile uint8_t GPIO_GCR8; 916 /* 0xF8: General Control 9 */ 917 volatile uint8_t GPIO_GCR9; 918 /* 0xF9: General Control 10 */ 919 volatile uint8_t GPIO_GCR10; 920 /* 0xFA: General Control 11 */ 921 volatile uint8_t GPIO_GCR11; 922 /* 0xFB: General Control 12 */ 923 volatile uint8_t GPIO_GCR12; 924 /* 0xFC: General Control 13 */ 925 volatile uint8_t GPIO_GCR13; 926 /* 0xFD: General Control 14 */ 927 volatile uint8_t GPIO_GCR14; 928 /* 0xFE: General Control 15 */ 929 volatile uint8_t GPIO_GCR15; 930 /* 0xFF: Power Good Watch Control */ 931 volatile uint8_t GPIO_PGWCR; 932 }; 933 #elif CONFIG_SOC_IT8XXX2_REG_SET_V2 934 struct gpio_it8xxx2_regs { 935 /* 0x00: General Control */ 936 volatile uint8_t GPIO_GCR; 937 /* 0x01-0x0F: Reserved1 */ 938 volatile uint8_t reserved1[15]; 939 /* 0x10: General Control 1 */ 940 volatile uint8_t GPIO_GCR1; 941 /* 0x11: General Control 2 */ 942 volatile uint8_t GPIO_GCR2; 943 /* 0x12: General Control 3 */ 944 volatile uint8_t GPIO_GCR3; 945 /* 0x13: General Control 4 */ 946 volatile uint8_t GPIO_GCR4; 947 /* 0x14: General Control 5 */ 948 volatile uint8_t GPIO_GCR5; 949 /* 0x15: General Control 6 */ 950 volatile uint8_t GPIO_GCR6; 951 /* 0x16: General Control 7 */ 952 volatile uint8_t GPIO_GCR7; 953 /* 0x17: General Control 8 */ 954 volatile uint8_t GPIO_GCR8; 955 /* 0x18: General Control 9 */ 956 volatile uint8_t GPIO_GCR9; 957 /* 0x19: General Control 10 */ 958 volatile uint8_t GPIO_GCR10; 959 /* 0x1A: General Control 11 */ 960 volatile uint8_t GPIO_GCR11; 961 /* 0x1B: General Control 12 */ 962 volatile uint8_t GPIO_GCR12; 963 /* 0x1C: General Control 13 */ 964 volatile uint8_t GPIO_GCR13; 965 /* 0x1D: General Control 14 */ 966 volatile uint8_t GPIO_GCR14; 967 /* 0x1E: General Control 15 */ 968 volatile uint8_t GPIO_GCR15; 969 /* 0x1F: Power Good Watch Control */ 970 volatile uint8_t GPIO_PGWCR; 971 /* 0x20: General Control 16 */ 972 volatile uint8_t GPIO_GCR16; 973 /* 0x21: General Control 17 */ 974 volatile uint8_t GPIO_GCR17; 975 /* 0x22: General Control 18 */ 976 volatile uint8_t GPIO_GCR18; 977 /* 0x23: Reserved2 */ 978 volatile uint8_t reserved2; 979 /* 0x24: General Control 19 */ 980 volatile uint8_t GPIO_GCR19; 981 /* 0x25: Reserved3 */ 982 volatile uint8_t reserved3; 983 /* 0x26: General Control 21 */ 984 volatile uint8_t GPIO_GCR21; 985 /* 0x27-0x28: Reserved4 */ 986 volatile uint8_t reserved4[2]; 987 /* 0x29: General Control 24 */ 988 volatile uint8_t GPIO_GCR24; 989 /* 0x2A-0x2C: Reserved5 */ 990 volatile uint8_t reserved5[3]; 991 /* 0x2D: General Control 30 */ 992 volatile uint8_t GPIO_GCR30; 993 /* 0x2E: General Control 29 */ 994 volatile uint8_t GPIO_GCR29; 995 }; 996 997 /* GPIO register fields */ 998 /* 0x16: General Control 7 */ 999 #define IT8XXX2_GPIO_SMB2PS BIT(7) 1000 #define IT8XXX2_GPIO_SMB3PS BIT(6) 1001 #define IT8XXX2_GPIO_SMB5PS BIT(5) 1002 1003 #endif 1004 #endif /* !__ASSEMBLER__ */ 1005 1006 /* GPIO register fields */ 1007 /* 0x00: General Control */ 1008 #define IT8XXX2_GPIO_LPCRSTEN (BIT(2) | BIT(1)) 1009 #define IT8XXX2_GPIO_GCR_ESPI_RST_D2 0x2 1010 #define IT8XXX2_GPIO_GCR_ESPI_RST_POS 1 1011 #define IT8XXX2_GPIO_GCR_ESPI_RST_EN_MASK (0x3 << IT8XXX2_GPIO_GCR_ESPI_RST_POS) 1012 /* 0xF0: General Control 1 */ 1013 #define IT8XXX2_GPIO_U2CTRL_SIN1_SOUT1_EN BIT(2) 1014 #define IT8XXX2_GPIO_U1CTRL_SIN0_SOUT0_EN BIT(0) 1015 /* 0xE6: General Control 21 */ 1016 #define IT8XXX2_GPIO_GPH1VS BIT(1) 1017 #define IT8XXX2_GPIO_GPH2VS BIT(0) 1018 1019 #define GPCR_PORT_PIN_MODE_INPUT BIT(7) 1020 #define GPCR_PORT_PIN_MODE_OUTPUT BIT(6) 1021 #define GPCR_PORT_PIN_MODE_PULLUP BIT(2) 1022 #define GPCR_PORT_PIN_MODE_PULLDOWN BIT(1) 1023 1024 /* 1025 * If both PULLUP and PULLDOWN are set to 1b, the corresponding port would be 1026 * configured as tri-state. 1027 */ 1028 #define GPCR_PORT_PIN_MODE_TRISTATE (GPCR_PORT_PIN_MODE_INPUT | \ 1029 GPCR_PORT_PIN_MODE_PULLUP | \ 1030 GPCR_PORT_PIN_MODE_PULLDOWN) 1031 1032 /* --- GPIO --- */ 1033 #define IT8XXX2_GPIO_BASE 0x00F01600 1034 #define IT8XXX2_GPIO2_BASE 0x00F03E00 1035 1036 #define IT8XXX2_GPIO_GCRX(offset) ECREG(IT8XXX2_GPIO_BASE + (offset)) 1037 #define IT8XXX2_GPIO_GCR25_OFFSET 0xd1 1038 #define IT8XXX2_GPIO_GCR26_OFFSET 0xd2 1039 #define IT8XXX2_GPIO_GCR27_OFFSET 0xd3 1040 #define IT8XXX2_GPIO_GCR28_OFFSET 0xd4 1041 #define IT8XXX2_GPIO_GCR31_OFFSET 0xd5 1042 #define IT8XXX2_GPIO_GCR32_OFFSET 0xd6 1043 #define IT8XXX2_GPIO_GCR33_OFFSET 0xd7 1044 #define IT8XXX2_GPIO_GCR19_OFFSET 0xe4 1045 #define IT8XXX2_GPIO_GCR20_OFFSET 0xe5 1046 #define IT8XXX2_GPIO_GCR21_OFFSET 0xe6 1047 #define IT8XXX2_GPIO_GCR22_OFFSET 0xe7 1048 #define IT8XXX2_GPIO_GCR23_OFFSET 0xe8 1049 #define IT8XXX2_GPIO_GCR24_OFFSET 0xe9 1050 #define IT8XXX2_GPIO_GCR30_OFFSET 0xed 1051 #define IT8XXX2_GPIO_GCR29_OFFSET 0xee 1052 1053 /* 1054 * TODO: use pinctrl node instead of following register declarations 1055 * to fix in tcpm\it83xx_pd.h. 1056 */ 1057 #define IT8XXX2_GPIO_GPCRP0 ECREG(IT8XXX2_GPIO2_BASE + 0x18) 1058 #define IT8XXX2_GPIO_GPCRP1 ECREG(IT8XXX2_GPIO2_BASE + 0x19) 1059 1060 1061 /** 1062 * 1063 * (19xxh) Analog to Digital Converter (ADC) registers 1064 * 1065 */ 1066 #ifndef __ASSEMBLER__ 1067 1068 /* Data structure to define ADC channel 13-16 control registers. */ 1069 struct adc_vchs_ctrl_t { 1070 /* 0x60: Voltage Channel Control */ 1071 volatile uint8_t VCHCTL; 1072 /* 0x61: Voltage Channel Data Buffer MSB */ 1073 volatile uint8_t VCHDATM; 1074 /* 0x62: Voltage Channel Data Buffer LSB */ 1075 volatile uint8_t VCHDATL; 1076 }; 1077 1078 struct adc_it8xxx2_regs { 1079 /* 0x00: ADC Status */ 1080 volatile uint8_t ADCSTS; 1081 /* 0x01: ADC Configuration */ 1082 volatile uint8_t ADCCFG; 1083 /* 0x02: ADC Clock Control */ 1084 volatile uint8_t ADCCTL; 1085 /* 0x03: General Control */ 1086 volatile uint8_t ADCGCR; 1087 /* 0x04: Voltage Channel 0 Control */ 1088 volatile uint8_t VCH0CTL; 1089 /* 0x05: Calibration Data Control */ 1090 volatile uint8_t KDCTL; 1091 /* 0x06-0x17: Reserved1 */ 1092 volatile uint8_t reserved1[18]; 1093 /* 0x18: Voltage Channel 0 Data Buffer LSB */ 1094 volatile uint8_t VCH0DATL; 1095 /* 0x19: Voltage Channel 0 Data Buffer MSB */ 1096 volatile uint8_t VCH0DATM; 1097 /* 0x1a-0x43: Reserved2 */ 1098 volatile uint8_t reserved2[42]; 1099 /* 0x44: ADC Data Valid Status */ 1100 volatile uint8_t ADCDVSTS; 1101 /* 0x45-0x54: Reserved2-1 */ 1102 volatile uint8_t reserved2_1[16]; 1103 /* 0x55: ADC Input Voltage Mapping Full-Scale Code Selection 1 */ 1104 volatile uint8_t ADCIVMFSCS1; 1105 /* 0x56: ADC Input Voltage Mapping Full-Scale Code Selection 2 */ 1106 volatile uint8_t ADCIVMFSCS2; 1107 /* 0x57: ADC Input Voltage Mapping Full-Scale Code Selection 3 */ 1108 volatile uint8_t ADCIVMFSCS3; 1109 /* 0x58-0x5f: Reserved3 */ 1110 volatile uint8_t reserved3[8]; 1111 /* 0x60-0x6b: ADC channel 13~16 controller */ 1112 struct adc_vchs_ctrl_t adc_vchs_ctrl[4]; 1113 /* 0x6c: ADC Data Valid Status 2 */ 1114 volatile uint8_t ADCDVSTS2; 1115 }; 1116 #endif /* !__ASSEMBLER__ */ 1117 1118 /* ADC conversion time select 1 */ 1119 #define IT8XXX2_ADC_ADCCTS1 BIT(7) 1120 /* Analog accuracy initialization */ 1121 #define IT8XXX2_ADC_AINITB BIT(3) 1122 /* ADC conversion time select 0 */ 1123 #define IT8XXX2_ADC_ADCCTS0 BIT(5) 1124 /* ADC module enable */ 1125 #define IT8XXX2_ADC_ADCEN BIT(0) 1126 /* ADC data buffer keep enable */ 1127 #define IT8XXX2_ADC_DBKEN BIT(7) 1128 /* W/C data valid flag */ 1129 #define IT8XXX2_ADC_DATVAL BIT(7) 1130 /* Data valid interrupt of adc */ 1131 #define IT8XXX2_ADC_INTDVEN BIT(5) 1132 /* Voltage channel enable (Channel 4~7 and 13~16) */ 1133 #define IT8XXX2_ADC_VCHEN BIT(4) 1134 /* Automatic hardware calibration enable */ 1135 #define IT8XXX2_ADC_AHCE BIT(7) 1136 /* 0x046, 0x049, 0x04c, 0x06e, 0x071, 0x074: Voltage comparator x control */ 1137 #define IT8XXX2_VCMP_CMPEN BIT(7) 1138 #define IT8XXX2_VCMP_CMPINTEN BIT(6) 1139 #define IT8XXX2_VCMP_GREATER_THRESHOLD BIT(5) 1140 #define IT8XXX2_VCMP_EDGE_TRIGGER BIT(4) 1141 #define IT8XXX2_VCMP_GPIO_ACTIVE_LOW BIT(3) 1142 /* 0x077~0x07c: Voltage comparator x channel select MSB */ 1143 #define IT8XXX2_VCMP_VCMPXCSELM BIT(0) 1144 1145 /** 1146 * 1147 * (1Exxh) Clock and Power Management (ECPM) registers 1148 * 1149 */ 1150 #define IT8XXX2_ECPM_BASE 0x00F01E00 1151 1152 #ifndef __ASSEMBLER__ 1153 enum chip_pll_mode { 1154 CHIP_PLL_DOZE = 0, 1155 CHIP_PLL_SLEEP = 1, 1156 CHIP_PLL_DEEP_DOZE = 3, 1157 }; 1158 #endif 1159 /* 1160 * TODO: use ecpm_it8xxx2_regs instead of following register declarations 1161 * to fix in soc.c. 1162 */ 1163 #define IT8XXX2_ECPM_PLLCTRL ECREG(IT8XXX2_ECPM_BASE + 0x03) 1164 #define IT8XXX2_ECPM_AUTOCG ECREG(IT8XXX2_ECPM_BASE + 0x04) 1165 #define IT8XXX2_ECPM_CGCTRL3R ECREG(IT8XXX2_ECPM_BASE + 0x05) 1166 #define IT8XXX2_ECPM_PLLFREQR ECREG(IT8XXX2_ECPM_BASE + 0x06) 1167 #define IT8XXX2_ECPM_PLLCSS ECREG(IT8XXX2_ECPM_BASE + 0x08) 1168 #define IT8XXX2_ECPM_SCDCR0 ECREG(IT8XXX2_ECPM_BASE + 0x0c) 1169 #define IT8XXX2_ECPM_SCDCR1 ECREG(IT8XXX2_ECPM_BASE + 0x0d) 1170 #define IT8XXX2_ECPM_SCDCR2 ECREG(IT8XXX2_ECPM_BASE + 0x0e) 1171 #define IT8XXX2_ECPM_SCDCR3 ECREG(IT8XXX2_ECPM_BASE + 0x0f) 1172 #define IT8XXX2_ECPM_SCDCR4 ECREG(IT8XXX2_ECPM_BASE + 0x10) 1173 1174 /* 1175 * The count number of the counter for 25 ms register. 1176 * The 25 ms register is calculated by (count number *1.024 kHz). 1177 */ 1178 1179 #define I2C_CLK_LOW_TIMEOUT 255 /* ~=249 ms */ 1180 1181 /** 1182 * 1183 * (1Cxxh) SMBus Interface (SMB) registers 1184 * 1185 */ 1186 #define IT8XXX2_SMB_BASE 0x00F01C00 1187 #ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1 1188 #define IT8XXX2_SMB_4P7USL ECREG(IT8XXX2_SMB_BASE + 0x00) 1189 #define IT8XXX2_SMB_4P0USL ECREG(IT8XXX2_SMB_BASE + 0x01) 1190 #define IT8XXX2_SMB_300NS ECREG(IT8XXX2_SMB_BASE + 0x02) 1191 #define IT8XXX2_SMB_250NS ECREG(IT8XXX2_SMB_BASE + 0x03) 1192 #define IT8XXX2_SMB_25MS ECREG(IT8XXX2_SMB_BASE + 0x04) 1193 #define IT8XXX2_SMB_45P3USL ECREG(IT8XXX2_SMB_BASE + 0x05) 1194 #define IT8XXX2_SMB_45P3USH ECREG(IT8XXX2_SMB_BASE + 0x06) 1195 #define IT8XXX2_SMB_4P7A4P0H ECREG(IT8XXX2_SMB_BASE + 0x07) 1196 #define IT8XXX2_SMB_SLVISELR ECREG(IT8XXX2_SMB_BASE + 0x08) 1197 #define IT8XXX2_SMB_SCLKTS(ch) ECREG(IT8XXX2_SMB_BASE + 0x09 + ch) 1198 #define IT8XXX2_SMB_MSTFCTRL1 ECREG(IT8XXX2_SMB_BASE + 0x0D) 1199 #define IT8XXX2_SMB_MSTFSTS1 ECREG(IT8XXX2_SMB_BASE + 0x0E) 1200 #define IT8XXX2_SMB_MSTFCTRL2 ECREG(IT8XXX2_SMB_BASE + 0x0F) 1201 #define IT8XXX2_SMB_MSTFSTS2 ECREG(IT8XXX2_SMB_BASE + 0x10) 1202 #define IT8XXX2_SMB_CHSEF ECREG(IT8XXX2_SMB_BASE + 0x11) 1203 #define IT8XXX2_SMB_I2CW2RF ECREG(IT8XXX2_SMB_BASE + 0x12) 1204 #define IT8XXX2_SMB_IWRFISTA ECREG(IT8XXX2_SMB_BASE + 0x13) 1205 #define IT8XXX2_SMB_CHSAB ECREG(IT8XXX2_SMB_BASE + 0x20) 1206 #define IT8XXX2_SMB_CHSCD ECREG(IT8XXX2_SMB_BASE + 0x21) 1207 #define IT8XXX2_SMB_SFFCTL ECREG(IT8XXX2_SMB_BASE + 0x55) 1208 #define IT8XXX2_SMB_HOSTA(base) ECREG(base + 0x00) 1209 #define IT8XXX2_SMB_HOCTL(base) ECREG(base + 0x01) 1210 #define IT8XXX2_SMB_HOCMD(base) ECREG(base + 0x02) 1211 #define IT8XXX2_SMB_TRASLA(base) ECREG(base + 0x03) 1212 #define IT8XXX2_SMB_D0REG(base) ECREG(base + 0x04) 1213 #define IT8XXX2_SMB_D1REG(base) ECREG(base + 0x05) 1214 #define IT8XXX2_SMB_HOBDB(base) ECREG(base + 0x06) 1215 #define IT8XXX2_SMB_PECERC(base) ECREG(base + 0x07) 1216 #define IT8XXX2_SMB_SMBPCTL(base) ECREG(base + 0x0A) 1217 #define IT8XXX2_SMB_HOCTL2(base) ECREG(base + 0x10) 1218 #elif CONFIG_SOC_IT8XXX2_REG_SET_V2 1219 #define IT8XXX2_SMB_SLVISEL ECREG(IT8XXX2_SMB_BASE + 0x08) 1220 #define IT8XXX2_SMB_SMB01CHS ECREG(IT8XXX2_SMB_BASE + 0x09) 1221 #define IT8XXX2_SMB_SMB23CHS ECREG(IT8XXX2_SMB_BASE + 0x0A) 1222 #define IT8XXX2_SMB_SMB4CHS ECREG(IT8XXX2_SMB_BASE + 0x0B) 1223 #define IT8XXX2_SMB_SCLKTS_BRGS ECREG(IT8XXX2_SMB_BASE + 0x80) 1224 #define IT8XXX2_SMB_SCLKTS_BRGM ECREG(IT8XXX2_SMB_BASE + 0x81) 1225 #define IT8XXX2_SMB_CHSBRG ECREG(IT8XXX2_SMB_BASE + 0x82) 1226 #define IT8XXX2_SMB_CHSMOT ECREG(IT8XXX2_SMB_BASE + 0x83) 1227 1228 /* SMBus register fields */ 1229 /* 0x80: SMCLK Timing Setting Register Bridge Slave */ 1230 #define IT8XXX2_SMB_PREDEN BIT(7) 1231 #endif 1232 1233 /** 1234 * Enhanced SMBus/I2C Interface 1235 * Ch_D: 0x00F03680, Ch_E: 0x00F03500, Ch_F: 0x00F03580 1236 * Ch_D: ch = 0x03, Ch_E: ch = 0x00, Ch_F: ch = 0x01 1237 */ 1238 #define IT8XXX2_I2C_DRR(base) ECREG(base + 0x00) 1239 #define IT8XXX2_I2C_PSR(base) ECREG(base + 0x01) 1240 #define IT8XXX2_I2C_HSPR(base) ECREG(base + 0x02) 1241 #define IT8XXX2_I2C_STR(base) ECREG(base + 0x03) 1242 #define IT8XXX2_I2C_DHTR(base) ECREG(base + 0x04) 1243 #define IT8XXX2_I2C_TOR(base) ECREG(base + 0x05) 1244 #define IT8XXX2_I2C_DTR(base) ECREG(base + 0x08) 1245 #define IT8XXX2_I2C_CTR(base) ECREG(base + 0x09) 1246 #define IT8XXX2_I2C_CTR1(base) ECREG(base + 0x0A) 1247 #define IT8XXX2_I2C_BYTE_CNT_L(base) ECREG(base + 0x0C) 1248 #define IT8XXX2_I2C_IRQ_ST(base) ECREG(base + 0x0D) 1249 #define IT8XXX2_I2C_IDR(base) ECREG(base + 0x06) 1250 #define IT8XXX2_I2C_TOS(base) ECREG(base + 0x07) 1251 #define IT8XXX2_I2C_STR2(base) ECREG(base + 0x12) 1252 #define IT8XXX2_I2C_NST(base) ECREG(base + 0x13) 1253 #define IT8XXX2_I2C_TO_ARB_ST(base) ECREG(base + 0x18) 1254 #define IT8XXX2_I2C_ERR_ST(base) ECREG(base + 0x19) 1255 #define IT8XXX2_I2C_FST(base) ECREG(base + 0x1B) 1256 #define IT8XXX2_I2C_EM(base) ECREG(base + 0x1C) 1257 #define IT8XXX2_I2C_MODE_SEL(base) ECREG(base + 0x1D) 1258 #define IT8XXX2_I2C_IDR2(base) ECREG(base + 0x1F) 1259 #define IT8XXX2_I2C_CTR2(base) ECREG(base + 0x20) 1260 #define IT8XXX2_I2C_RAMHA(base) ECREG(base + 0x23) 1261 #define IT8XXX2_I2C_RAMLA(base) ECREG(base + 0x24) 1262 #define IT8XXX2_I2C_RAMHA2(base) ECREG(base + 0x2B) 1263 #define IT8XXX2_I2C_RAMLA2(base) ECREG(base + 0x2C) 1264 #define IT8XXX2_I2C_CMD_ADDH(base) ECREG(base + 0x25) 1265 #define IT8XXX2_I2C_CMD_ADDL(base) ECREG(base + 0x26) 1266 #define IT8XXX2_I2C_RAMH2A(base) ECREG(base + 0x50) 1267 #define IT8XXX2_I2C_CMD_ADDH2(base) ECREG(base + 0x52) 1268 1269 /* SMBus/I2C register fields */ 1270 /* 0x09-0xB: SMCLK Timing Setting */ 1271 #define IT8XXX2_SMB_SMCLKS_1M 4 1272 #define IT8XXX2_SMB_SMCLKS_400K 3 1273 #define IT8XXX2_SMB_SMCLKS_100K 2 1274 #define IT8XXX2_SMB_SMCLKS_50K 1 1275 1276 /* 0x0E: SMBus FIFO Status 1 */ 1277 #define IT8XXX2_SMB_FIFO1_EMPTY BIT(7) 1278 #define IT8XXX2_SMB_FIFO1_FULL BIT(6) 1279 /* 0x0D: SMBus FIFO Control 1 */ 1280 /* 0x0F: SMBus FIFO Control 2 */ 1281 #define IT8XXX2_SMB_BLKDS BIT(4) 1282 #define IT8XXX2_SMB_FFEN BIT(3) 1283 #define IT8XXX2_SMB_FFCHSEL2_B 0 1284 #define IT8XXX2_SMB_FFCHSEL2_C BIT(0) 1285 /* 0x10: SMBus FIFO Status 2 */ 1286 #define IT8XXX2_SMB_FIFO2_EMPTY BIT(7) 1287 #define IT8XXX2_SMB_FIFO2_FULL BIT(6) 1288 /* 0x12: I2C Wr To Rd FIFO */ 1289 #define IT8XXX2_SMB_MAIF BIT(7) 1290 #define IT8XXX2_SMB_MBCIF BIT(6) 1291 #define IT8XXX2_SMB_MCIFI BIT(2) 1292 #define IT8XXX2_SMB_MBIFI BIT(1) 1293 #define IT8XXX2_SMB_MAIFI BIT(0) 1294 /* 0x13: I2C Wr To Rd FIFO Interrupt Status */ 1295 #define IT8XXX2_SMB_MCIFID BIT(2) 1296 #define IT8XXX2_SMB_MAIFID BIT(0) 1297 /* 0x41 0x81 0xC1: Host Control */ 1298 #define IT8XXX2_SMB_SRT BIT(6) 1299 #define IT8XXX2_SMB_LABY BIT(5) 1300 #define IT8XXX2_SMB_SMCD_EXTND BIT(4) | BIT(3) | BIT(2) 1301 #define IT8XXX2_SMB_KILL BIT(1) 1302 #define IT8XXX2_SMB_INTREN BIT(0) 1303 /* 0x43 0x83 0xC3: Transmit Slave Address */ 1304 #define IT8XXX2_SMB_DIR BIT(0) 1305 /* 0x4A 0x8A 0xCA: SMBus Pin Control */ 1306 #define IT8XXX2_SMB_SMBDCS BIT(1) 1307 #define IT8XXX2_SMB_SMBCS BIT(0) 1308 /* 0x50 0x90 0xD0: Host Control 2 */ 1309 #define IT8XXX2_SMB_SMD_TO_EN BIT(4) 1310 #define IT8XXX2_SMB_I2C_SW_EN BIT(3) 1311 #define IT8XXX2_SMB_I2C_SW_WAIT BIT(2) 1312 #define IT8XXX2_SMB_I2C_EN BIT(1) 1313 #define IT8XXX2_SMB_SMHEN BIT(0) 1314 /* 0x55: Slave A FIFO Control */ 1315 #define IT8XXX2_SMB_HSAPE BIT(1) 1316 /* 0x04: Data Hold Time */ 1317 #define IT8XXX2_I2C_SOFT_RST BIT(7) 1318 /* 0x07: Time Out Status */ 1319 #define IT8XXX2_I2C_SCL_IN BIT(2) 1320 #define IT8XXX2_I2C_SDA_IN BIT(0) 1321 /* 0x0A: Control 1 */ 1322 #define IT8XXX2_I2C_COMQ_EN BIT(7) 1323 #define IT8XXX2_I2C_MDL_EN BIT(1) 1324 /* 0x13: Nack Status */ 1325 #define IT8XXX2_I2C_NST_CNS BIT(7) 1326 #define IT8XXX2_I2C_NST_ID_NACK BIT(3) 1327 /* 0x19: Error Status */ 1328 #define IT8XXX2_I2C_ERR_ST_DEV1_EIRQ BIT(0) 1329 /* 0x1B: Finish Status */ 1330 #define IT8XXX2_I2C_FST_DEV1_IRQ BIT(4) 1331 /* 0x1C: Error Mask */ 1332 #define IT8XXX2_I2C_EM_DEV1_IRQ BIT(4) 1333 1334 /* 1335 * TODO: use gctrl_it8xxx2_regs instead of following register declarations 1336 * to fix in cros_flash_it8xxx2.c, cros_shi_it8xxx2.c and tcpm\it8xxx2.c. 1337 */ 1338 /* --- General Control (GCTRL) --- */ 1339 #define IT83XX_GCTRL_BASE 0x00F02000 1340 1341 #define IT83XX_GCTRL_CHIPID1 ECREG(IT83XX_GCTRL_BASE + 0x85) 1342 #define IT83XX_GCTRL_CHIPID2 ECREG(IT83XX_GCTRL_BASE + 0x86) 1343 #define IT83XX_GCTRL_CHIPVER ECREG(IT83XX_GCTRL_BASE + 0x02) 1344 #define IT83XX_GCTRL_MCCR3 ECREG(IT83XX_GCTRL_BASE + 0x20) 1345 #define IT83XX_GCTRL_SPISLVPFE BIT(6) 1346 #define IT83XX_GCTRL_EWPR0PFH(i) ECREG(IT83XX_GCTRL_BASE + 0x60 + i) 1347 #define IT83XX_GCTRL_EWPR0PFD(i) ECREG(IT83XX_GCTRL_BASE + 0xA0 + i) 1348 #define IT83XX_GCTRL_EWPR0PFEC(i) ECREG(IT83XX_GCTRL_BASE + 0xC0 + i) 1349 1350 /* 1351 * TODO: use spisc_it8xxx2_regs instead of following register declarations 1352 * to fix in cros_shi_it8xxx2.c. 1353 */ 1354 /* Serial Peripheral Interface (SPI) */ 1355 #define IT83XX_SPI_BASE 0x00F03A00 1356 1357 #define IT83XX_SPI_SPISGCR ECREG(IT83XX_SPI_BASE + 0x00) 1358 #define IT83XX_SPI_SPISCEN BIT(0) 1359 #define IT83XX_SPI_TXRXFAR ECREG(IT83XX_SPI_BASE + 0x01) 1360 #define IT83XX_SPI_CPURXF2A BIT(4) 1361 #define IT83XX_SPI_CPURXF1A BIT(3) 1362 #define IT83XX_SPI_CPUTFA BIT(1) 1363 #define IT83XX_SPI_TXFCR ECREG(IT83XX_SPI_BASE + 0x02) 1364 #define IT83XX_SPI_TXFCMR BIT(2) 1365 #define IT83XX_SPI_TXFR BIT(1) 1366 #define IT83XX_SPI_TXFS BIT(0) 1367 #define IT83XX_SPI_GCR2 ECREG(IT83XX_SPI_BASE + 0x03) 1368 #define IT83XX_SPI_RXF2OC BIT(4) 1369 #define IT83XX_SPI_RXF1OC BIT(3) 1370 #define IT83XX_SPI_RXFAR BIT(0) 1371 #define IT83XX_SPI_IMR ECREG(IT83XX_SPI_BASE + 0x04) 1372 #define IT83XX_SPI_RX_FIFO_FULL BIT(7) 1373 #define IT83XX_SPI_RX_REACH BIT(5) 1374 #define IT83XX_SPI_EDIM BIT(2) 1375 #define IT83XX_SPI_ISR ECREG(IT83XX_SPI_BASE + 0x05) 1376 #define IT83XX_SPI_TXFSR ECREG(IT83XX_SPI_BASE + 0x06) 1377 #define IT83XX_SPI_ENDDETECTINT BIT(2) 1378 #define IT83XX_SPI_RXFSR ECREG(IT83XX_SPI_BASE + 0x07) 1379 #define IT83XX_SPI_RXFFSM (BIT(4) | BIT(3)) 1380 #define IT83XX_SPI_RXF2FS BIT(2) 1381 #define IT83XX_SPI_RXF1FS BIT(1) 1382 #ifdef CHIP_VARIANT_IT83202BX 1383 #define IT83XX_SPI_SPISRDR ECREG(IT83XX_SPI_BASE + 0x08) 1384 #else 1385 #define IT83XX_SPI_SPISRDR ECREG(IT83XX_SPI_BASE + 0x0b) 1386 #endif 1387 #define IT83XX_SPI_CPUWTFDB0 ECREG_u32(IT83XX_SPI_BASE + 0x08) 1388 #define IT83XX_SPI_FCR ECREG(IT83XX_SPI_BASE + 0x09) 1389 #define IT83XX_SPI_SPISRTXF BIT(2) 1390 #define IT83XX_SPI_RXFR BIT(1) 1391 #define IT83XX_SPI_RXFCMR BIT(0) 1392 #define IT83XX_SPI_RXFRDRB0 ECREG_u32(IT83XX_SPI_BASE + 0x0C) 1393 #define IT83XX_SPI_FTCB0R ECREG(IT83XX_SPI_BASE + 0x18) 1394 #define IT83XX_SPI_FTCB1R ECREG(IT83XX_SPI_BASE + 0x19) 1395 #define IT83XX_SPI_TCCB0 ECREG(IT83XX_SPI_BASE + 0x1A) 1396 #define IT83XX_SPI_TCCB1 ECREG(IT83XX_SPI_BASE + 0x1B) 1397 #define IT83XX_SPI_HPR2 ECREG(IT83XX_SPI_BASE + 0x1E) 1398 #define IT83XX_SPI_EMMCBMR ECREG(IT83XX_SPI_BASE + 0x21) 1399 #define IT83XX_SPI_EMMCABM BIT(1) /* eMMC Alternative Boot Mode */ 1400 #define IT83XX_SPI_RX_VLISMR ECREG(IT83XX_SPI_BASE + 0x26) 1401 #define IT83XX_SPI_RVLIM BIT(0) 1402 #define IT83XX_SPI_RX_VLISR ECREG(IT83XX_SPI_BASE + 0x27) 1403 #define IT83XX_SPI_RVLI BIT(0) 1404 1405 /** 1406 * 1407 * (20xxh) General Control (GCTRL) registers 1408 * 1409 */ 1410 #define GCTRL_IT8XXX2_REGS_BASE \ 1411 ((struct gctrl_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(gctrl))) 1412 1413 #ifndef __ASSEMBLER__ 1414 struct gctrl_it8xxx2_regs { 1415 /* 0x00-0x01: Reserved_00_01 */ 1416 volatile uint8_t reserved_00_01[2]; 1417 /* 0x02: Chip Version */ 1418 volatile uint8_t GCTRL_ECHIPVER; 1419 /* 0x03-0x05: Reserved_03_05 */ 1420 volatile uint8_t reserved_03_05[3]; 1421 /* 0x06: Reset Status */ 1422 volatile uint8_t GCTRL_RSTS; 1423 /* 0x07-0x09: Reserved_07_09 */ 1424 volatile uint8_t reserved_07_09[3]; 1425 /* 0x0A: Base Address Select */ 1426 volatile uint8_t GCTRL_BADRSEL; 1427 /* 0x0B: Wait Next Clock Rising */ 1428 volatile uint8_t GCTRL_WNCKR; 1429 /* 0x0C: reserved_0c */ 1430 volatile uint8_t reserved_0c; 1431 /* 0x0D: Special Control 1 */ 1432 volatile uint8_t GCTRL_SPCTRL1; 1433 /* 0x0E-0x0F: reserved_0e_0f */ 1434 volatile uint8_t reserved_0e_0f[2]; 1435 /* 0x10: Reset Control DMM */ 1436 volatile uint8_t GCTRL_RSTDMMC; 1437 /* 0x11: Reset Control 4 */ 1438 volatile uint8_t GCTRL_RSTC4; 1439 /* 0x12-0x1B: reserved_12_1b */ 1440 volatile uint8_t reserved_12_1b[10]; 1441 /* 0x1C: Special Control 4 */ 1442 volatile uint8_t GCTRL_SPCTRL4; 1443 /* 0x1D-0x1F: reserved_1d_1f */ 1444 volatile uint8_t reserved_1d_1f[3]; 1445 /* 0x20: Memory Controller Configuration 3 */ 1446 volatile uint8_t GCTRL_MCCR3; 1447 /* 0x21: Reset Control 5 */ 1448 volatile uint8_t GCTRL_RSTC5; 1449 /* 0x22-0x2F: reserved_22_2f */ 1450 volatile uint8_t reserved_22_2f[14]; 1451 /* 0x30: Memory Controller Configuration */ 1452 volatile uint8_t GCTRL_MCCR; 1453 /* 0x31: Externel ILM/DLM Size */ 1454 volatile uint8_t GCTRL_EIDSR; 1455 /* 0x32: Reserved_32 */ 1456 volatile uint8_t reserved_32; 1457 /* 0x33: Pin Multi-function Enable 2 */ 1458 volatile uint8_t gctrl_pmer2; 1459 /* 0x34-0x36: Reserved_34_36 */ 1460 volatile uint8_t reserved_34_36[3]; 1461 /* 0x37: Eflash Protect Lock */ 1462 volatile uint8_t GCTRL_EPLR; 1463 /* 0x38-0x40: Reserved_38_40 */ 1464 volatile uint8_t reserved_38_40[9]; 1465 /* 0x41: Interrupt Vector Table Base Address */ 1466 volatile uint8_t GCTRL_IVTBAR; 1467 /* 0x42-0x43: Reserved_42_43 */ 1468 volatile uint8_t reserved_42_43[2]; 1469 /* 0x44: Memory Controller Configuration 2 */ 1470 volatile uint8_t GCTRL_MCCR2; 1471 /* 0x45: Reserved_45 */ 1472 volatile uint8_t reserved_45; 1473 /* 0x46: Pin Multi-function Enable 3 */ 1474 volatile uint8_t GCTRL_PMER3; 1475 /* 0x47-0x4A: reserved_47_4a */ 1476 volatile uint8_t reserved_47_4a[4]; 1477 /* 0x4B: ETWD and UART Control */ 1478 volatile uint8_t GCTRL_ETWDUARTCR; 1479 /* 0x4C: Wakeup MCU Control */ 1480 volatile uint8_t GCTRL_WMCR; 1481 /* 0x4D-0x4F: reserved_4d_4f */ 1482 volatile uint8_t reserved_4d_4f[3]; 1483 /* 0x50: Port 80h/81h Status Register */ 1484 volatile uint8_t GCTRL_P80H81HSR; 1485 /* 0x51: Port 80h Data Register */ 1486 volatile uint8_t GCTRL_P80HDR; 1487 /* 0x52: Port 81h Data Register */ 1488 volatile uint8_t GCTRL_P81HDR; 1489 /* 0x53: H2RAM Offset Register */ 1490 volatile uint8_t GCTRL_H2ROFSR; 1491 /* 0x54-0x5C: reserved_54_5c */ 1492 volatile uint8_t reserved_54_5c[9]; 1493 /* 0x5D: RISCV ILM Configuration 0 */ 1494 volatile uint8_t GCTRL_RVILMCR0; 1495 /* 0x5E-0x84: reserved_5e_84 */ 1496 volatile uint8_t reserved_5e_84[39]; 1497 /* 0x85: Chip ID Byte 1 */ 1498 volatile uint8_t GCTRL_ECHIPID1; 1499 /* 0x86: Chip ID Byte 2 */ 1500 volatile uint8_t GCTRL_ECHIPID2; 1501 /* 0x87: Chip ID Byte 3 */ 1502 volatile uint8_t GCTRL_ECHIPID3; 1503 }; 1504 #endif /* !__ASSEMBLER__ */ 1505 1506 /* GCTRL register fields */ 1507 /* 0x06: Reset Status */ 1508 #define IT8XXX2_GCTRL_LRS (BIT(1) | BIT(0)) 1509 #define IT8XXX2_GCTRL_IWDTR BIT(1) 1510 /* 0x10: Reset Control DMM */ 1511 #define IT8XXX2_GCTRL_UART1SD BIT(3) 1512 #define IT8XXX2_GCTRL_UART2SD BIT(2) 1513 /* 0x11: Reset Control 4 */ 1514 #define IT8XXX2_GCTRL_RPECI BIT(4) 1515 #define IT8XXX2_GCTRL_RUART2 BIT(2) 1516 #define IT8XXX2_GCTRL_RUART1 BIT(1) 1517 /* 0x1C: Special Control 4 */ 1518 #define IT8XXX2_GCTRL_LRSIWR BIT(2) 1519 #define IT8XXX2_GCTRL_LRSIPWRSWTR BIT(1) 1520 #define IT8XXX2_GCTRL_LRSIPGWR BIT(0) 1521 /* 0x20: Memory Controller Configuration 3 */ 1522 #define IT8XXX2_GCTRL_SPISLVPFE BIT(6) 1523 /* 0x30: Memory Controller Configuration */ 1524 #define IT8XXX2_GCTRL_ICACHE_RESET BIT(4) 1525 /* 0x37: Eflash Protect Lock */ 1526 #define IT8XXX2_GCTRL_EPLR_ENABLE BIT(0) 1527 /* 0x46: Pin Multi-function Enable 3 */ 1528 #define IT8XXX2_GCTRL_SMB3PSEL BIT(6) 1529 /* 0x4B: ETWD and UART Control */ 1530 #define IT8XXX2_GCTRL_ETWD_HW_RST_EN BIT(0) 1531 /* 0x5D: RISCV ILM Configuration 0 */ 1532 #define IT8XXX2_GCTRL_ILM0_ENABLE BIT(0) 1533 /* Accept Port 80h Cycle */ 1534 #define IT8XXX2_GCTRL_ACP80 BIT(6) 1535 /* USB Debug Enable */ 1536 #define IT8XXX2_GCTRL_MCCR_USB_EN BIT(7) 1537 /* USB Pad Power-On Enable */ 1538 #define IT8XXX2_GCTRL_PMER2_USB_PAD_EN BIT(7) 1539 1540 /* 1541 * VCC Detector Option. 1542 * bit[7-6] = 1: The VCC power status is treated as power-on. 1543 * The VCC supply of eSPI and related functions (EC2I, KBC, PMC and 1544 * PECI). It means VCC should be logic high before using these 1545 * functions, or firmware treats VCC logic high. 1546 */ 1547 #define IT8XXX2_GCTRL_VCCDO_MASK (BIT(6) | BIT(7)) 1548 #define IT8XXX2_GCTRL_VCCDO_VCC_ON BIT(6) 1549 /* 1550 * bit[3] = 0: The reset source of PNPCFG is RSTPNP bit in RSTCH 1551 * register and WRST#. 1552 */ 1553 #define IT8XXX2_GCTRL_HGRST BIT(3) 1554 /* bit[2] = 1: Enable global reset. */ 1555 #define IT8XXX2_GCTRL_GRST BIT(2) 1556 1557 /** 1558 * 1559 * (22xxh) Battery-backed SRAM (BRAM) registers 1560 * 1561 */ 1562 #ifndef __ASSEMBLER__ 1563 /* Battery backed RAM indices. */ 1564 #define BRAM_MAGIC_FIELD_OFFSET 0xbc 1565 enum bram_indices { 1566 1567 /* This field is used to indicate BRAM is valid or not. */ 1568 BRAM_IDX_VALID_FLAGS0 = BRAM_MAGIC_FIELD_OFFSET, 1569 BRAM_IDX_VALID_FLAGS1, 1570 BRAM_IDX_VALID_FLAGS2, 1571 BRAM_IDX_VALID_FLAGS3 1572 }; 1573 #endif /* !__ASSEMBLER__ */ 1574 1575 #ifndef __ASSEMBLER__ 1576 /* 1577 * EC2I bridge registers 1578 */ 1579 struct ec2i_regs { 1580 /* 0x00: Indirect Host I/O Address Register */ 1581 volatile uint8_t IHIOA; 1582 /* 0x01: Indirect Host Data Register */ 1583 volatile uint8_t IHD; 1584 /* 0x02: Lock Super I/O Host Access Register */ 1585 volatile uint8_t LSIOHA; 1586 /* 0x03: Super I/O Access Lock Violation Register */ 1587 volatile uint8_t SIOLV; 1588 /* 0x04: EC to I-Bus Modules Access Enable Register */ 1589 volatile uint8_t IBMAE; 1590 /* 0x05: I-Bus Control Register */ 1591 volatile uint8_t IBCTL; 1592 }; 1593 1594 /* Index list of the host interface registers of PNPCFG */ 1595 enum host_pnpcfg_index { 1596 /* Logical Device Number */ 1597 HOST_INDEX_LDN = 0x07, 1598 /* Chip ID Byte 1 */ 1599 HOST_INDEX_CHIPID1 = 0x20, 1600 /* Chip ID Byte 2 */ 1601 HOST_INDEX_CHIPID2 = 0x21, 1602 /* Chip Version */ 1603 HOST_INDEX_CHIPVER = 0x22, 1604 /* Super I/O Control */ 1605 HOST_INDEX_SIOCTRL = 0x23, 1606 /* Super I/O IRQ Configuration */ 1607 HOST_INDEX_SIOIRQ = 0x25, 1608 /* Super I/O General Purpose */ 1609 HOST_INDEX_SIOGP = 0x26, 1610 /* Super I/O Power Mode */ 1611 HOST_INDEX_SIOPWR = 0x2D, 1612 /* Depth 2 I/O Address */ 1613 HOST_INDEX_D2ADR = 0x2E, 1614 /* Depth 2 I/O Data */ 1615 HOST_INDEX_D2DAT = 0x2F, 1616 /* Logical Device Activate Register */ 1617 HOST_INDEX_LDA = 0x30, 1618 /* I/O Port Base Address Bits [15:8] for Descriptor 0 */ 1619 HOST_INDEX_IOBAD0_MSB = 0x60, 1620 /* I/O Port Base Address Bits [7:0] for Descriptor 0 */ 1621 HOST_INDEX_IOBAD0_LSB = 0x61, 1622 /* I/O Port Base Address Bits [15:8] for Descriptor 1 */ 1623 HOST_INDEX_IOBAD1_MSB = 0x62, 1624 /* I/O Port Base Address Bits [7:0] for Descriptor 1 */ 1625 HOST_INDEX_IOBAD1_LSB = 0x63, 1626 /* Interrupt Request Number and Wake-Up on IRQ Enabled */ 1627 HOST_INDEX_IRQNUMX = 0x70, 1628 /* Interrupt Request Type Select */ 1629 HOST_INDEX_IRQTP = 0x71, 1630 /* DMA Channel Select 0 */ 1631 HOST_INDEX_DMAS0 = 0x74, 1632 /* DMA Channel Select 1 */ 1633 HOST_INDEX_DMAS1 = 0x75, 1634 /* Device Specific Logical Device Configuration 1 to 10 */ 1635 HOST_INDEX_DSLDC1 = 0xF0, 1636 HOST_INDEX_DSLDC2 = 0xF1, 1637 HOST_INDEX_DSLDC3 = 0xF2, 1638 HOST_INDEX_DSLDC4 = 0xF3, 1639 HOST_INDEX_DSLDC5 = 0xF4, 1640 HOST_INDEX_DSLDC6 = 0xF5, 1641 HOST_INDEX_DSLDC7 = 0xF6, 1642 HOST_INDEX_DSLDC8 = 0xF7, 1643 HOST_INDEX_DSLDC9 = 0xF8, 1644 HOST_INDEX_DSLDC10 = 0xF9, 1645 }; 1646 1647 /* List of logical device number (LDN) assignments */ 1648 enum logical_device_number { 1649 /* Serial Port 1 */ 1650 LDN_UART1 = 0x01, 1651 /* Serial Port 2 */ 1652 LDN_UART2 = 0x02, 1653 /* System Wake-Up Control */ 1654 LDN_SWUC = 0x04, 1655 /* KBC/Mouse Interface */ 1656 LDN_KBC_MOUSE = 0x05, 1657 /* KBC/Keyboard Interface */ 1658 LDN_KBC_KEYBOARD = 0x06, 1659 /* Consumer IR */ 1660 LDN_CIR = 0x0A, 1661 /* Shared Memory/Flash Interface */ 1662 LDN_SMFI = 0x0F, 1663 /* RTC-like Timer */ 1664 LDN_RTCT = 0x10, 1665 /* Power Management I/F Channel 1 */ 1666 LDN_PMC1 = 0x11, 1667 /* Power Management I/F Channel 2 */ 1668 LDN_PMC2 = 0x12, 1669 /* Serial Peripheral Interface */ 1670 LDN_SSPI = 0x13, 1671 /* Platform Environment Control Interface */ 1672 LDN_PECI = 0x14, 1673 /* Power Management I/F Channel 3 */ 1674 LDN_PMC3 = 0x17, 1675 /* Power Management I/F Channel 4 */ 1676 LDN_PMC4 = 0x18, 1677 /* Power Management I/F Channel 5 */ 1678 LDN_PMC5 = 0x19, 1679 }; 1680 1681 /* Structure for initializing PNPCFG via ec2i. */ 1682 struct ec2i_t { 1683 /* index port */ 1684 enum host_pnpcfg_index index_port; 1685 /* data port */ 1686 uint8_t data_port; 1687 }; 1688 1689 /* EC2I access index/data port */ 1690 enum ec2i_access { 1691 /* index port */ 1692 EC2I_ACCESS_INDEX = 0, 1693 /* data port */ 1694 EC2I_ACCESS_DATA = 1, 1695 }; 1696 1697 /* EC to I-Bus Access Enabled */ 1698 #define EC2I_IBCTL_CSAE BIT(0) 1699 /* EC Read from I-Bus */ 1700 #define EC2I_IBCTL_CRIB BIT(1) 1701 /* EC Write to I-Bus */ 1702 #define EC2I_IBCTL_CWIB BIT(2) 1703 #define EC2I_IBCTL_CRWIB (EC2I_IBCTL_CRIB | EC2I_IBCTL_CWIB) 1704 1705 /* PNPCFG Register EC Access Enable */ 1706 #define EC2I_IBMAE_CFGAE BIT(0) 1707 1708 /* 1709 * KBC registers 1710 */ 1711 struct kbc_regs { 1712 /* 0x00: KBC Host Interface Control Register */ 1713 volatile uint8_t KBHICR; 1714 /* 0x01: Reserved1 */ 1715 volatile uint8_t reserved1; 1716 /* 0x02: KBC Interrupt Control Register */ 1717 volatile uint8_t KBIRQR; 1718 /* 0x03: Reserved2 */ 1719 volatile uint8_t reserved2; 1720 /* 0x04: KBC Host Interface Keyboard/Mouse Status Register */ 1721 volatile uint8_t KBHISR; 1722 /* 0x05: Reserved3 */ 1723 volatile uint8_t reserved3; 1724 /* 0x06: KBC Host Interface Keyboard Data Output Register */ 1725 volatile uint8_t KBHIKDOR; 1726 /* 0x07: Reserved4 */ 1727 volatile uint8_t reserved4; 1728 /* 0x08: KBC Host Interface Mouse Data Output Register */ 1729 volatile uint8_t KBHIMDOR; 1730 /* 0x09: Reserved5 */ 1731 volatile uint8_t reserved5; 1732 /* 0x0a: KBC Host Interface Keyboard/Mouse Data Input Register */ 1733 volatile uint8_t KBHIDIR; 1734 }; 1735 1736 /* Output Buffer Full */ 1737 #define KBC_KBHISR_OBF BIT(0) 1738 /* Input Buffer Full */ 1739 #define KBC_KBHISR_IBF BIT(1) 1740 /* A2 Address (A2) */ 1741 #define KBC_KBHISR_A2_ADDR BIT(3) 1742 #define KBC_KBHISR_STS_MASK (KBC_KBHISR_OBF | KBC_KBHISR_IBF \ 1743 | KBC_KBHISR_A2_ADDR) 1744 1745 /* Clear Output Buffer Full */ 1746 #define KBC_KBHICR_COBF BIT(6) 1747 /* IBF/OBF Clear Mode Enable */ 1748 #define KBC_KBHICR_IBFOBFCME BIT(5) 1749 /* Input Buffer Full CPU Interrupt Enable */ 1750 #define KBC_KBHICR_IBFCIE BIT(3) 1751 /* Output Buffer Empty CPU Interrupt Enable */ 1752 #define KBC_KBHICR_OBECIE BIT(2) 1753 /* Output Buffer Full Mouse Interrupt Enable */ 1754 #define KBC_KBHICR_OBFMIE BIT(1) 1755 /* Output Buffer Full Keyboard Interrupt Enable */ 1756 #define KBC_KBHICR_OBFKIE BIT(0) 1757 1758 /* 1759 * PMC registers 1760 */ 1761 struct pmc_regs { 1762 /* 0x00: Host Interface PM Channel 1 Status */ 1763 volatile uint8_t PM1STS; 1764 /* 0x01: Host Interface PM Channel 1 Data Out Port */ 1765 volatile uint8_t PM1DO; 1766 /* 0x02: Host Interface PM Channel 1 Data Out Port with SCI# */ 1767 volatile uint8_t PM1DOSCI; 1768 /* 0x03: Host Interface PM Channel 1 Data Out Port with SMI# */ 1769 volatile uint8_t PM1DOSMI; 1770 /* 0x04: Host Interface PM Channel 1 Data In Port */ 1771 volatile uint8_t PM1DI; 1772 /* 0x05: Host Interface PM Channel 1 Data In Port with SCI# */ 1773 volatile uint8_t PM1DISCI; 1774 /* 0x06: Host Interface PM Channel 1 Control */ 1775 volatile uint8_t PM1CTL; 1776 /* 0x07: Host Interface PM Channel 1 Interrupt Control */ 1777 volatile uint8_t PM1IC; 1778 /* 0x08: Host Interface PM Channel 1 Interrupt Enable */ 1779 volatile uint8_t PM1IE; 1780 /* 0x09-0x0f: Reserved1 */ 1781 volatile uint8_t reserved1[7]; 1782 /* 0x10: Host Interface PM Channel 2 Status */ 1783 volatile uint8_t PM2STS; 1784 /* 0x11: Host Interface PM Channel 2 Data Out Port */ 1785 volatile uint8_t PM2DO; 1786 /* 0x12: Host Interface PM Channel 2 Data Out Port with SCI# */ 1787 volatile uint8_t PM2DOSCI; 1788 /* 0x13: Host Interface PM Channel 2 Data Out Port with SMI# */ 1789 volatile uint8_t PM2DOSMI; 1790 /* 0x14: Host Interface PM Channel 2 Data In Port */ 1791 volatile uint8_t PM2DI; 1792 /* 0x15: Host Interface PM Channel 2 Data In Port with SCI# */ 1793 volatile uint8_t PM2DISCI; 1794 /* 0x16: Host Interface PM Channel 2 Control */ 1795 volatile uint8_t PM2CTL; 1796 /* 0x17: Host Interface PM Channel 2 Interrupt Control */ 1797 volatile uint8_t PM2IC; 1798 /* 0x18: Host Interface PM Channel 2 Interrupt Enable */ 1799 volatile uint8_t PM2IE; 1800 /* 0x19: Mailbox Control */ 1801 volatile uint8_t MBXCTRL; 1802 /* 0x1a-0x1f: Reserved2 */ 1803 volatile uint8_t reserved2[6]; 1804 /* 0x20-0xff: Reserved3 */ 1805 volatile uint8_t reserved3[0xe0]; 1806 }; 1807 1808 /* Input Buffer Full Interrupt Enable */ 1809 #define PMC_PM1CTL_IBFIE BIT(0) 1810 /* Output Buffer Full */ 1811 #define PMC_PM1STS_OBF BIT(0) 1812 /* Input Buffer Full */ 1813 #define PMC_PM1STS_IBF BIT(1) 1814 /* General Purpose Flag */ 1815 #define PMC_PM1STS_GPF BIT(2) 1816 /* A2 Address (A2) */ 1817 #define PMC_PM1STS_A2_ADDR BIT(3) 1818 1819 /* PMC2 Input Buffer Full Interrupt Enable */ 1820 #define PMC_PM2CTL_IBFIE BIT(0) 1821 /* General Purpose Flag */ 1822 #define PMC_PM2STS_GPF BIT(2) 1823 1824 /* 1825 * Dedicated Interrupt 1826 * 0b: 1827 * INT3: PMC Output Buffer Empty Int 1828 * INT25: PMC Input Buffer Full Int 1829 * 1b: 1830 * INT3: PMC1 Output Buffer Empty Int 1831 * INT25: PMC1 Input Buffer Full Int 1832 * INT26: PMC2 Output Buffer Empty Int 1833 * INT27: PMC2 Input Buffer Full Int 1834 */ 1835 #define PMC_MBXCTRL_DINT BIT(5) 1836 1837 /* 1838 * eSPI slave registers 1839 */ 1840 struct espi_slave_regs { 1841 /* 0x00-0x03: Reserved1 */ 1842 volatile uint8_t reserved1[4]; 1843 1844 /* 0x04: General Capabilities and Configuration 0 */ 1845 volatile uint8_t GCAPCFG0; 1846 /* 0x05: General Capabilities and Configuration 1 */ 1847 volatile uint8_t GCAPCFG1; 1848 /* 0x06: General Capabilities and Configuration 2 */ 1849 volatile uint8_t GCAPCFG2; 1850 /* 0x07: General Capabilities and Configuration 3 */ 1851 volatile uint8_t GCAPCFG3; 1852 1853 /* Channel 0 (Peripheral Channel) Capabilities and Configurations */ 1854 /* 0x08: Channel 0 Capabilities and Configuration 0 */ 1855 volatile uint8_t CH_PC_CAPCFG0; 1856 /* 0x09: Channel 0 Capabilities and Configuration 1 */ 1857 volatile uint8_t CH_PC_CAPCFG1; 1858 /* 0x0A: Channel 0 Capabilities and Configuration 2 */ 1859 volatile uint8_t CH_PC_CAPCFG2; 1860 /* 0x0B: Channel 0 Capabilities and Configuration 3 */ 1861 volatile uint8_t CH_PC_CAPCFG3; 1862 1863 /* Channel 1 (Virtual Wire Channel) Capabilities and Configurations */ 1864 /* 0x0C: Channel 1 Capabilities and Configuration 0 */ 1865 volatile uint8_t CH_VW_CAPCFG0; 1866 /* 0x0D: Channel 1 Capabilities and Configuration 1 */ 1867 volatile uint8_t CH_VW_CAPCFG1; 1868 /* 0x0E: Channel 1 Capabilities and Configuration 2 */ 1869 volatile uint8_t CH_VW_CAPCFG2; 1870 /* 0x0F: Channel 1 Capabilities and Configuration 3 */ 1871 volatile uint8_t CH_VW_CAPCFG3; 1872 1873 /* Channel 2 (OOB Message Channel) Capabilities and Configurations */ 1874 /* 0x10: Channel 2 Capabilities and Configuration 0 */ 1875 volatile uint8_t CH_OOB_CAPCFG0; 1876 /* 0x11: Channel 2 Capabilities and Configuration 1 */ 1877 volatile uint8_t CH_OOB_CAPCFG1; 1878 /* 0x12: Channel 2 Capabilities and Configuration 2 */ 1879 volatile uint8_t CH_OOB_CAPCFG2; 1880 /* 0x13: Channel 2 Capabilities and Configuration 3 */ 1881 volatile uint8_t CH_OOB_CAPCFG3; 1882 1883 /* Channel 3 (Flash Access Channel) Capabilities and Configurations */ 1884 /* 0x14: Channel 3 Capabilities and Configuration 0 */ 1885 volatile uint8_t CH_FLASH_CAPCFG0; 1886 /* 0x15: Channel 3 Capabilities and Configuration 1 */ 1887 volatile uint8_t CH_FLASH_CAPCFG1; 1888 /* 0x16: Channel 3 Capabilities and Configuration 2 */ 1889 volatile uint8_t CH_FLASH_CAPCFG2; 1890 /* 0x17: Channel 3 Capabilities and Configuration 3 */ 1891 volatile uint8_t CH_FLASH_CAPCFG3; 1892 /* Channel 3 Capabilities and Configurations 2 */ 1893 /* 0x18: Channel 3 Capabilities and Configuration 2-0 */ 1894 volatile uint8_t CH_FLASH_CAPCFG2_0; 1895 /* 0x19: Channel 3 Capabilities and Configuration 2-1 */ 1896 volatile uint8_t CH_FLASH_CAPCFG2_1; 1897 /* 0x1A: Channel 3 Capabilities and Configuration 2-2 */ 1898 volatile uint8_t CH_FLASH_CAPCFG2_2; 1899 /* 0x1B: Channel 3 Capabilities and Configuration 2-3 */ 1900 volatile uint8_t CH_FLASH_CAPCFG2_3; 1901 1902 /* 0x1c-0x1f: Reserved2 */ 1903 volatile uint8_t reserved2[4]; 1904 /* 0x20-0x8f: Reserved3 */ 1905 volatile uint8_t reserved3[0x70]; 1906 1907 /* 0x90: eSPI PC Control 0 */ 1908 volatile uint8_t ESPCTRL0; 1909 /* 0x91: eSPI PC Control 1 */ 1910 volatile uint8_t ESPCTRL1; 1911 /* 0x92: eSPI PC Control 2 */ 1912 volatile uint8_t ESPCTRL2; 1913 /* 0x93: eSPI PC Control 3 */ 1914 volatile uint8_t ESPCTRL3; 1915 /* 0x94: eSPI PC Control 4 */ 1916 volatile uint8_t ESPCTRL4; 1917 /* 0x95: eSPI PC Control 5 */ 1918 volatile uint8_t ESPCTRL5; 1919 /* 0x96: eSPI PC Control 6 */ 1920 volatile uint8_t ESPCTRL6; 1921 /* 0x97: eSPI PC Control 7 */ 1922 volatile uint8_t ESPCTRL7; 1923 /* 0x98-0x9f: Reserved4 */ 1924 volatile uint8_t reserved4[8]; 1925 1926 /* 0xa0: eSPI General Control 0 */ 1927 volatile uint8_t ESGCTRL0; 1928 /* 0xa1: eSPI General Control 1 */ 1929 volatile uint8_t ESGCTRL1; 1930 /* 0xa2: eSPI General Control 2 */ 1931 volatile uint8_t ESGCTRL2; 1932 /* 0xa3: eSPI General Control 3 */ 1933 volatile uint8_t ESGCTRL3; 1934 /* 0xa4-0xaf: Reserved5 */ 1935 volatile uint8_t reserved5[12]; 1936 1937 /* 0xb0: eSPI Upstream Control 0 */ 1938 volatile uint8_t ESUCTRL0; 1939 /* 0xb1: eSPI Upstream Control 1 */ 1940 volatile uint8_t ESUCTRL1; 1941 /* 0xb2: eSPI Upstream Control 2 */ 1942 volatile uint8_t ESUCTRL2; 1943 /* 0xb3: eSPI Upstream Control 3 */ 1944 volatile uint8_t ESUCTRL3; 1945 /* 0xb4-0xb5: Reserved6 */ 1946 volatile uint8_t reserved6[2]; 1947 /* 0xb6: eSPI Upstream Control 6 */ 1948 volatile uint8_t ESUCTRL6; 1949 /* 0xb7: eSPI Upstream Control 7 */ 1950 volatile uint8_t ESUCTRL7; 1951 /* 0xb8: eSPI Upstream Control 8 */ 1952 volatile uint8_t ESUCTRL8; 1953 /* 0xb9-0xbf: Reserved7 */ 1954 volatile uint8_t reserved7[7]; 1955 1956 /* 0xc0: eSPI OOB Control 0 */ 1957 volatile uint8_t ESOCTRL0; 1958 /* 0xc1: eSPI OOB Control 1 */ 1959 volatile uint8_t ESOCTRL1; 1960 /* 0xc2-0xc3: Reserved8 */ 1961 volatile uint8_t reserved8[2]; 1962 /* 0xc4: eSPI OOB Control 4 */ 1963 volatile uint8_t ESOCTRL4; 1964 /* 0xc5-0xcf: Reserved9 */ 1965 volatile uint8_t reserved9[11]; 1966 1967 /* 0xd0: eSPI SAFS Control 0 */ 1968 volatile uint8_t ESPISAFSC0; 1969 /* 0xd1: eSPI SAFS Control 1 */ 1970 volatile uint8_t ESPISAFSC1; 1971 /* 0xd2: eSPI SAFS Control 2 */ 1972 volatile uint8_t ESPISAFSC2; 1973 /* 0xd3: eSPI SAFS Control 3 */ 1974 volatile uint8_t ESPISAFSC3; 1975 /* 0xd4: eSPI SAFS Control 4 */ 1976 volatile uint8_t ESPISAFSC4; 1977 /* 0xd5: eSPI SAFS Control 5 */ 1978 volatile uint8_t ESPISAFSC5; 1979 /* 0xd6: eSPI SAFS Control 6 */ 1980 volatile uint8_t ESPISAFSC6; 1981 /* 0xd7: eSPI SAFS Control 7 */ 1982 volatile uint8_t ESPISAFSC7; 1983 }; 1984 1985 /* 1986 * eSPI VW registers 1987 */ 1988 struct espi_vw_regs { 1989 /* 0x00-0x7f: VW index */ 1990 volatile uint8_t VW_INDEX[0x80]; 1991 /* 0x80-0x8f: Reserved1 */ 1992 volatile uint8_t reserved1[0x10]; 1993 /* 0x90: VW Contrl 0 */ 1994 volatile uint8_t VWCTRL0; 1995 /* 0x91: VW Contrl 1 */ 1996 volatile uint8_t VWCTRL1; 1997 /* 0x92: VW Contrl 2 */ 1998 volatile uint8_t VWCTRL2; 1999 /* 0x93: VW Contrl 3 */ 2000 volatile uint8_t VWCTRL3; 2001 /* 0x94: Reserved2 */ 2002 volatile uint8_t reserved2; 2003 /* 0x95: VW Contrl 5 */ 2004 volatile uint8_t VWCTRL5; 2005 /* 0x96: VW Contrl 6 */ 2006 volatile uint8_t VWCTRL6; 2007 /* 0x97: VW Contrl 7 */ 2008 volatile uint8_t VWCTRL7; 2009 /* 0x98-0x99: Reserved3 */ 2010 volatile uint8_t reserved3[2]; 2011 }; 2012 2013 #define ESPI_IT8XXX2_OOB_MAX_PAYLOAD_SIZE 80 2014 /* 2015 * eSPI Queue 0 registers 2016 */ 2017 struct espi_queue0_regs { 2018 /* 0x00-0x3f: PUT_PC Data Byte 0-63 */ 2019 volatile uint8_t PUT_PC_DATA[0x40]; 2020 /* 0x40-0x7f: Reserved1 */ 2021 volatile uint8_t reserved1[0x40]; 2022 /* 0x80-0xcf: PUT_OOB Data Byte 0-79 */ 2023 volatile uint8_t PUT_OOB_DATA[ESPI_IT8XXX2_OOB_MAX_PAYLOAD_SIZE]; 2024 }; 2025 2026 /* 2027 * eSPI Queue 1 registers 2028 */ 2029 struct espi_queue1_regs { 2030 /* 0x00-0x4f: Upstream Data Byte 0-79 */ 2031 volatile uint8_t UPSTREAM_DATA[ESPI_IT8XXX2_OOB_MAX_PAYLOAD_SIZE]; 2032 /* 0x50-0x7f: Reserved1 */ 2033 volatile uint8_t reserved1[0x30]; 2034 /* 0x80-0xbf: PUT_FLASH_NP Data Byte 0-63 */ 2035 volatile uint8_t PUT_FLASH_NP_DATA[0x40]; 2036 }; 2037 2038 #endif /* !__ASSEMBLER__ */ 2039 2040 2041 /** 2042 * 2043 * (3Axxh) SPI Slave Controller (SPISC) registers 2044 * 2045 */ 2046 #ifndef __ASSEMBLER__ 2047 struct spisc_it8xxx2_regs { 2048 /* 0x00: SPI Slave General Control */ 2049 volatile uint8_t SPISC_SPISGCR; 2050 /* 0x01: Tx/Rx FIFO Access */ 2051 volatile uint8_t SPISC_TXRXFAR; 2052 /* 0x02: Tx FIFO Control */ 2053 volatile uint8_t SPISC_TXFCR; 2054 /* 0x03: SPI Slave General Control 2 */ 2055 volatile uint8_t SPISC_SPISGCR2; 2056 /* 0x04: Interrupt Mask */ 2057 volatile uint8_t SPISC_IMR; 2058 /* 0x05: Interrupt Status */ 2059 volatile uint8_t SPISC_ISR; 2060 /* 0x06: Tx FIFO Status */ 2061 volatile uint8_t SPISC_TXFSR; 2062 /* 0x07: Rx FIFO Status */ 2063 volatile uint8_t SPISC_RXFSR; 2064 /* 0x08: CPU Write Tx FIFO Data Byte0 */ 2065 volatile uint8_t SPISC_CPUWTXFDB0R; 2066 /* 0x09: FIFO Control / CPU Write Tx FIFO Data Byte1 */ 2067 volatile uint8_t SPISC_FCR; 2068 /* 0x0A: CPU Write Tx FIFO Data Byte2 */ 2069 volatile uint8_t SPISC_CPUWTXFDB2R; 2070 /* 0x0B: SPI Slave Response Data / CPU Write Tx FIFO Data Byte3 */ 2071 volatile uint8_t SPISC_SPISRDR; 2072 /* 0x0C: Rx FIFO Readout Data Byte0 */ 2073 volatile uint8_t SPISC_RXFRDRB0; 2074 /* 0x0D: Rx FIFO Readout Data Byte1 */ 2075 volatile uint8_t SPISC_RXFRDRB1; 2076 /* 0x0E: Rx FIFO Readout Data Byte2 */ 2077 volatile uint8_t SPISC_RXFRDRB2; 2078 /* 0x0F: Rx FIFO Readout Data Byte3 */ 2079 volatile uint8_t SPISC_RXFRDRB3; 2080 /* 0x10-0x17: Reserved1 */ 2081 volatile uint8_t reserved1[8]; 2082 /* 0x18: FIFO Target Count Byte0 */ 2083 volatile uint8_t SPISC_FTCB0R; 2084 /* 0x19: FIFO Target Count Byte1 */ 2085 volatile uint8_t SPISC_FTCB1R; 2086 /* 0x1A: Target Count Capture Byte0 */ 2087 volatile uint8_t SPISC_TCCB0; 2088 /* 0x1B: Target Count Capture Byte1 */ 2089 volatile uint8_t SPISC_TCCB1; 2090 /* 0x1C-0x1D: Reserved2 */ 2091 volatile uint8_t reserved2[2]; 2092 /* 0x1E: Hardware Parsing 2 */ 2093 volatile uint8_t SPISC_HPR2; 2094 /* 0x1F-0x25: Reserved3 */ 2095 volatile uint8_t reserved3[7]; 2096 /* 0x26: Rx Valid Length Interrupt Status Mask */ 2097 volatile uint8_t SPISC_RXVLISMR; 2098 /* 0x27: Rx Valid Length Interrupt Status */ 2099 volatile uint8_t SPISC_RXVLISR; 2100 }; 2101 #endif /* !__ASSEMBLER__ */ 2102 2103 /* SPISC register fields */ 2104 /* 0x00: SPI Slave General Control */ 2105 #define IT8XXX2_SPISC_SPISCEN BIT(0) 2106 /* 0x01: Tx/Rx FIFO Access */ 2107 #define IT8XXX2_SPISC_CPURXF1A BIT(3) 2108 #define IT8XXX2_SPISC_CPUTFA BIT(1) 2109 /* 0x02: Tx FIFO Control */ 2110 #define IT8XXX2_SPISC_TXFCMR BIT(2) 2111 #define IT8XXX2_SPISC_TXFR BIT(1) 2112 #define IT8XXX2_SPISC_TXFS BIT(0) 2113 /* 0x03: SPI Slave General Control 2 */ 2114 #define IT8XXX2_SPISC_RXF2OC BIT(4) 2115 #define IT8XXX2_SPISC_RXF1OC BIT(3) 2116 #define IT8XXX2_SPISC_RXFAR BIT(0) 2117 /* 0x04: Interrupt Mask */ 2118 #define IT8XXX2_SPISC_EDIM BIT(2) 2119 /* 0x06: Tx FIFO Status */ 2120 #define IT8XXX2_SPISC_ENDDETECTINT BIT(2) 2121 /* 0x09: FIFO Control */ 2122 #define IT8XXX2_SPISC_SPISRTXF BIT(2) 2123 #define IT8XXX2_SPISC_RXFR BIT(1) 2124 #define IT8XXX2_SPISC_RXFCMR BIT(0) 2125 /* 0x26: Rx Valid Length Interrupt Status Mask */ 2126 #define IT8XXX2_SPISC_RVLIM BIT(0) 2127 /* 0x27: Rx Valid Length Interrupt Status */ 2128 #define IT8XXX2_SPISC_RVLI BIT(0) 2129 2130 #endif /* CHIP_CHIPREGS_H */ 2131
