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Searched refs:r2 (Results 1 – 25 of 56) sorted by relevance

123

/Zephyr-Core-3.4.0/arch/nios2/core/
Dcrt0.S46 movhi r2, %hi(ALT_CPU_ICACHE_SIZE)
48 movui r2, ALT_CPU_ICACHE_SIZE
55 subi r2, r2, 4
57 subi r2, r2, ALT_CPU_ICACHE_LINE_SIZE
59 initi r2
60 bgt r2, zero, 0b
85 movhi r2, %hi(ALT_CPU_DCACHE_SIZE)
87 movui r2, ALT_CPU_DCACHE_SIZE
94 subi r2, r2, 4
96 subi r2, r2, ALT_CPU_DCACHE_LINE_SIZE
[all …]
Dswap.S75 ldw r2, _kernel_offset_to_ready_q_cache(r10)
80 stw r2, _kernel_offset_to_current(r10)
85 ldw r16, _thread_offset_to_r16(r2)
86 ldw r17, _thread_offset_to_r17(r2)
87 ldw r18, _thread_offset_to_r18(r2)
88 ldw r19, _thread_offset_to_r19(r2)
89 ldw r20, _thread_offset_to_r20(r2)
90 ldw r21, _thread_offset_to_r21(r2)
91 ldw r22, _thread_offset_to_r22(r2)
92 ldw r23, _thread_offset_to_r23(r2)
[all …]
/Zephyr-Core-3.4.0/arch/arm/core/aarch32/cortex_m/
Dpm_s2ram.S33 mrs r2, msp
34 str r2, [r1, #___cpu_context_t_msp_OFFSET]
36 mrs r2, msplim
37 str r2, [r1, #___cpu_context_t_msplim_OFFSET]
39 mrs r2, psp
40 str r2, [r1, #___cpu_context_t_psp_OFFSET]
42 mrs r2, psplim
43 str r2, [r1, #___cpu_context_t_psplim_OFFSET]
45 mrs r2, apsr
46 str r2, [r1, #___cpu_context_t_apsr_OFFSET]
[all …]
Dfault_s.S87 push { r1, r2 }
90 mov r2, r10
91 push {r2, r3}
93 mov r2, r8
94 push {r2, r3}
101 mov r2, lr /* EXC_RETURN */
Dexc_exit.S79 ldr r2, =_SCS_ICSR_PENDSV
80 str r2, [r1]
/Zephyr-Core-3.4.0/arch/arm/core/aarch32/
Dswap_helper.S77 ldr r2, [r1, #_kernel_offset_to_current]
81 strb lr, [r2, #_thread_offset_to_mode_exc_return]
86 add r0, r2
116 add r0, r2, #_thread_offset_to_preempt_float
132 ldrb r0, [r2, #_thread_offset_to_user_options]
155 add r0, r2, #_thread_offset_to_preempt_float
205 ldr r2, [r1, #_kernel_offset_to_ready_q_cache]
207 str r2, [r1, #_kernel_offset_to_current]
226 adds r4, r2, r4
250 ldrsb lr, [r2, #_thread_offset_to_mode_exc_return]
[all …]
Disr_wrapper.S110 ldr r2, =_kernel
111 ldr r0, [r2, #_kernel_offset_to_fp_ctx]
113 streq sp, [r2, #_kernel_offset_to_fp_ctx]
138 push {r2, r3}
141 ldr r2, =_kernel
142 ldr r0, [r2, #_kernel_offset_to_nested]
144 str r0, [r2, #_kernel_offset_to_nested]
172 ldr r2, =_kernel
174 ldr r0, [r2, #_kernel_offset_to_idle]
181 str r1, [r2, #_kernel_offset_to_idle]
[all …]
Duserspace.S111 push {r1,r2,r3,lr}
160 mov r2, ip
183 pop {r1,r2,r3,r4}
188 pop {r1,r2,r3,lr}
253 push {r0, r1, r2, r3}
258 movs r2, #1
259 orrs r1, r1, r2
261 orrs r3, r3, r2
264 ldr r2, =_thread_offset_to_mode
265 str r1, [r0, r2]
[all …]
/Zephyr-Core-3.4.0/soc/arm/nxp_lpc/lpc54xxx/gcc/
Dstartup_LPC54114_cm4.S53 ldrh r2, [r6, #16] /* Mask for CPU ID bits */
54 ands r2, r1, r2 /* r2 = ARM COrtex CPU ID */
56 cmp r3, r2 /* Core ID matches M4 identifier */
79 ldr r2, [r0] /* r1 = SYSCON co-processor boot address */
81 cmp r2, #0 /* Slave boot address = 0 (not set up)? */
91 bx r2 /* Jump to slave boot address */
/Zephyr-Core-3.4.0/arch/arc/core/
Dfast_irq.S55 lr r2, [_ARC_V2_SEC_STAT]
56 bclr r2, r2, _ARC_V2_SEC_STAT_SSC_BIT
57 sflag r2
60 lr r2, [_ARC_V2_STATUS32]
61 bclr r2, r2, _ARC_V2_STATUS32_SC_BIT
62 kflag r2
184 st r2, [r1, -8]
238 ld r2, [r1, -8]
241 st _CAUSE_FIRQ, [r2, _thread_offset_to_relinquish_cause]
247 mov r2, r0
Disr_wrapper.S227 mov_s r2, _firq_enter
228 j_s [r2]
232 mov_s r2, _rirq_enter
233 j_s [r2]
236 mov.z r2, _firq_enter
238 mov.nz r2, _rirq_enter
239 j_s [r2]
243 MOVR r2, _rirq_enter
244 j_s [r2]
Dreset.S97 mov_s r2, 0
98 sr r2, [_ARC_V2_IC_IVIC]
140 mov_s r2, 0
143 brge r2, r3, done_mpu_regions_reset
144 sr r2, [_ARC_V2_MPU_INDEX]
148 add_s r2, r2, 1
193 mov_s r2, CONFIG_ISR_STACK_SIZE
Dfault_s.S124 STR r2, r2, ___thread_t_switch_handle_OFFSET
126 MOVR r2, r0
149 mov ilink, r2
168 push_s r2
173 pop_s r2
179 mov r2, ilink
Duserspace.S18 mov_s r2, 0
64 pop_s r2
74 st.aw r2, [r5, -4]
109 push_s r2
132 mov r2, r6
205 ld_s r2, [sp, ___isf_t_r2_OFFSET]
279 st_s r1, [r2, 0]
Dswitch.S64 SUBR r2, r1, ___thread_t_switch_handle_OFFSET
67 _st32_huge_offset _CAUSE_COOP, r2, _thread_offset_to_relinquish_cause, r3
94 MOVR r2, r0
Dregular_irq.S208 _disable_stack_checking r2
260 _st32_huge_offset _CAUSE_RIRQ, r2, _thread_offset_to_relinquish_cause, r1
265 MOVR r2, r0
/Zephyr-Core-3.4.0/soc/arm/ti_lm3s6965/
Dreboot.S44 ldreq r2, =z_force_exit_one_nested_irq
46 ldrne r2, =z_do_software_reboot
51 and.w r2, r1
52 str r2, [ip, #(6 * 4)]
53 ldr r2, =0x01000000
54 str r2, [ip, #(7 * 4)]
/Zephyr-Core-3.4.0/include/zephyr/arch/arm/aarch32/
Dsyscall.h46 register uint32_t r2 __asm__("r2") = arg3; in arch_syscall_invoke6()
53 : "=r"(ret), "=r"(r1), "=r"(r2), "=r"(r3) in arch_syscall_invoke6()
55 "r" (ret), "r" (r1), "r" (r2), "r" (r3), in arch_syscall_invoke6()
69 register uint32_t r2 __asm__("r2") = arg3; in arch_syscall_invoke5()
75 : "=r"(ret), "=r"(r1), "=r"(r2), "=r"(r3) in arch_syscall_invoke5()
77 "r" (ret), "r" (r1), "r" (r2), "r" (r3), in arch_syscall_invoke5()
90 register uint32_t r2 __asm__("r2") = arg3; in arch_syscall_invoke4()
95 : "=r"(ret), "=r"(r1), "=r"(r2), "=r"(r3) in arch_syscall_invoke4()
97 "r" (ret), "r" (r1), "r" (r2), "r" (r3), in arch_syscall_invoke4()
110 register uint32_t r2 __asm__("r2") = arg3; in arch_syscall_invoke3()
[all …]
/Zephyr-Core-3.4.0/arch/arm/core/aarch32/cortex_a_r/
Dexc.S61 mov r2, sp
62 vstmia r2!, {s0-s15}
63 stm r2, {r0, r1}
86 ldr r2, =_kernel
87 ldr r1, [r2, #_kernel_offset_to_nested]
89 str r1, [r2, #_kernel_offset_to_nested]
128 ldr r2, =_kernel
129 ldr r1, [r2, #_kernel_offset_to_nested]
131 str r1, [r2, #_kernel_offset_to_nested]
145 mov r2, sp
[all …]
Dexc_exit.S71 ldr r2, =_kernel
72 ldr r1, [r2, #_kernel_offset_to_fp_ctx]
82 streq r1, [r2, #_kernel_offset_to_fp_ctx]
87 ldm r3, {r1, r2}
88 tst r2, #FPEXC_EN
91 vmsr fpexc, r2
152 ldr r2, =_kernel
153 ldr r0, [r2, #_kernel_offset_to_nested]
155 str r0, [r2, #_kernel_offset_to_nested]
158 pop {r2, r3}
/Zephyr-Core-3.4.0/arch/arc/include/
Dswap_macros.h73 ld_s r13, [r2, ___thread_base_t_user_options_OFFSET]
94 STR sp, r2, _thread_offset_to_sp
100 LDR sp, r2, _thread_offset_to_sp
110 ld_s r13, [r2, ___thread_base_t_user_options_OFFSET]
199 STR r2, sp, ___isf_t_r2_OFFSET
215 lr r2, [_ARC_V2_EI_BASE]
218 st_s r2, [sp, ___isf_t_ei_base_OFFSET]
234 ld_s r2, [sp, ___isf_t_ei_base_OFFSET]
237 sr r2, [_ARC_V2_EI_BASE]
260 LDR r2, sp, ___isf_t_r2_OFFSET
[all …]
/Zephyr-Core-3.4.0/include/zephyr/arch/arm64/
Dsyscall.h46 register uint64_t r2 __asm__("x2") = arg3; in arch_syscall_invoke6()
55 "r" (ret), "r" (r1), "r" (r2), "r" (r3), in arch_syscall_invoke6()
69 register uint64_t r2 __asm__("x2") = arg3; in arch_syscall_invoke5()
77 "r" (ret), "r" (r1), "r" (r2), "r" (r3), in arch_syscall_invoke5()
90 register uint64_t r2 __asm__("x2") = arg3; in arch_syscall_invoke4()
97 "r" (ret), "r" (r1), "r" (r2), "r" (r3), in arch_syscall_invoke4()
110 register uint64_t r2 __asm__("x2") = arg3; in arch_syscall_invoke3()
116 "r" (ret), "r" (r1), "r" (r2), "r" (r8) in arch_syscall_invoke3()
/Zephyr-Core-3.4.0/include/zephyr/arch/arc/
Dsyscall.h47 register uint32_t r2 __asm__("r2") = arg3; in arch_syscall_invoke6()
59 "r" (ret), "r" (r1), "r" (r2), "r" (r3), in arch_syscall_invoke6()
72 register uint32_t r2 __asm__("r2") = arg3; in arch_syscall_invoke5()
83 "r" (ret), "r" (r1), "r" (r2), "r" (r3), in arch_syscall_invoke5()
95 register uint32_t r2 __asm__("r2") = arg3; in arch_syscall_invoke4()
105 "r" (ret), "r" (r1), "r" (r2), "r" (r3), in arch_syscall_invoke4()
117 register uint32_t r2 __asm__("r2") = arg3; in arch_syscall_invoke3()
126 "r" (ret), "r" (r1), "r" (r2), "r" (r6)); in arch_syscall_invoke3()
/Zephyr-Core-3.4.0/include/zephyr/arch/arc/v2/secureshield/
Darc_secure.h59 register uint32_t r2 __asm__("r2") = arg3; in _arc_s_call_invoke6()
71 "r" (ret), "r" (r1), "r" (r2), "r" (r3), in _arc_s_call_invoke6()
82 register uint32_t r2 __asm__("r2") = arg3; in _arc_s_call_invoke5()
93 "r" (ret), "r" (r1), "r" (r2), "r" (r3), in _arc_s_call_invoke5()
104 register uint32_t r2 __asm__("r2") = arg3; in _arc_s_call_invoke4()
114 "r" (ret), "r" (r1), "r" (r2), "r" (r3), in _arc_s_call_invoke4()
125 register uint32_t r2 __asm__("r2") = arg3; in _arc_s_call_invoke3()
134 "r" (ret), "r" (r1), "r" (r2), "r" (r6)); in _arc_s_call_invoke3()
/Zephyr-Core-3.4.0/soc/arm/nxp_kinetis/kv5x/
Dwdog.S68 mov r2, #1
69 bics r1, r2

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