Searched refs:psr (Results 1 – 16 of 16) sorted by relevance
| /Zephyr-Core-3.4.0/drivers/timer/ |
| D | rv32m1_lptmr_timer.c | 76 uint32_t csr, psr, sircdiv; /* LPTMR registers */ in sys_clock_driver_init() local
123 psr = SYSTEM_TIMER_INSTANCE->PSR; in sys_clock_driver_init()
124 psr &= ~LPTMR_PSR_PCS_MASK; in sys_clock_driver_init()
125 psr |= (LPTMR_PSR_PBYP(1) | LPTMR_PSR_PCS(PCS_SOURCE_SIRCDIV3)); in sys_clock_driver_init()
126 SYSTEM_TIMER_INSTANCE->PSR = psr; in sys_clock_driver_init()
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| /Zephyr-Core-3.4.0/arch/sparc/core/ |
| D | thread.c | 47 thread->callee_saved.psr = PSR_S | PSR_PS | PSR_ET; in arch_new_thread()
52 thread->callee_saved.psr |= PSR_EF; in arch_new_thread()
56 thread->callee_saved.psr |= PSR_EF; in arch_new_thread()
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| D | switch.S | 46 rd %psr, %o4
51 wr %g1, %psr /* disable traps */
90 wr %g1, %psr /* restore cwp */
142 wr %g1, %psr /* restore status register and ET */
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| D | window_trap.S | 105 rd %psr, %g2
107 wr %g2, PSR_ET, %psr
136 wr %l0, %psr
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| D | interrupt_trap.S | 143 wr %l6, PSR_ET, %psr
204 wr %l6, %l5, %psr
275 rd %psr, %l3
279 mov %l0, %psr
326 wr %l0, %psr
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| D | sw_trap_set_pil.S | 34 wr %l5, %psr
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| D | reset_trap.S | 18 wr PSR_PIL | PSR_S | PSR_PS | PSR_ET, %psr
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| D | trap_table_mvt.S | 17 rd %psr, %l0; \
23 rd %psr, %l0; \
29 rd %psr, %l0; \
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| D | fault_trap.S | 100 wr %o2, PSR_ET, %psr
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| D | fatal.c | 166 esf->psr, esf->wim, esf->tbr, esf->y in print_special_registers()
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| /Zephyr-Core-3.4.0/arch/sparc/core/offsets/ |
| D | offsets.c | 21 GEN_OFFSET_SYM(_callee_saved_t, psr);
37 GEN_OFFSET_SYM(z_arch_esf_t, psr);
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| /Zephyr-Core-3.4.0/include/zephyr/arch/sparc/ |
| D | thread.h | 34 uint32_t psr; member
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| D | arch.h | 113 uint32_t psr; member
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| /Zephyr-Core-3.4.0/drivers/sensor/dps310/ |
| D | dps310.c | 439 float psr = ((float)psr_raw) / IFX_DPS310_SF_PSR; in dps310_scale_pressure() local
445 psr_final += psr * (comp->c10 + psr * (comp->c20 + psr * comp->c30)); in dps310_scale_pressure()
447 psr_final += tmp * psr * (comp->c11 + psr * comp->c21); in dps310_scale_pressure()
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| /Zephyr-Core-3.4.0/drivers/i2c/ |
| D | i2c_ite_enhance.c | 247 uint32_t clk_div, psr, pll_clock; in i2c_enhanced_port_set_frequency() local
264 psr = (pll_clock / (clk_div * (2U * freq_hz))) - 2U; in i2c_enhanced_port_set_frequency()
266 if (psr > 0xFD) { in i2c_enhanced_port_set_frequency()
267 psr = 0xFD; in i2c_enhanced_port_set_frequency()
271 psr += config->prescale_scl_low; in i2c_enhanced_port_set_frequency()
274 IT8XXX2_I2C_PSR(base) = psr & 0xFF; in i2c_enhanced_port_set_frequency()
275 IT8XXX2_I2C_HSPR(base) = psr & 0xFF; in i2c_enhanced_port_set_frequency()
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| /Zephyr-Core-3.4.0/drivers/display/ |
| D | uc81xx.c | 221 uint8_t psr = in uc81xx_set_profile() local
264 psr |= UC81XX_PSR_REG; in uc81xx_set_profile()
269 LOG_DBG("PSR: %#hhx", psr); in uc81xx_set_profile()
270 if (uc81xx_write_cmd_uint8(dev, UC81XX_CMD_PSR, psr)) { in uc81xx_set_profile()
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