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/Zephyr-Core-3.4.0/drivers/clock_control/
Dclock_agilex_ll.c25 uint32_t get_ref_clk(uint32_t pllglob) in get_ref_clk() argument
30 switch (CLKMGR_PSRC(pllglob)) { in get_ref_clk()
47 arefclkdiv = CLKMGR_PLLGLOB_AREFCLKDIV(pllglob); in get_ref_clk()