pllc_reg (reference) in projects: Zephyr-Core-3.4.0

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/Zephyr-Core-3.4.0/drivers/clock_control/
D	clock_agilex_ll.c	`57 uint32_t pllm_reg, pllc_reg, pllc_div, pllglob_reg; in get_clk_freq() local 64 pllc_reg = CLKMGR_MAINPLL + main_pllc; in get_clk_freq() 69 pllc_reg = CLKMGR_PERPLL + per_pllc; in get_clk_freq() 80 pllc_div = mmio_read_32(pllc_reg) & 0x7ff; in get_clk_freq()`

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
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