| /Zephyr-Core-3.4.0/soc/riscv/riscv-ite/it8xxx2/ |
| D | soc.c | 103 void __soc_ram_code chip_run_pll_sequence(const struct pll_config_t *pll) in chip_run_pll_sequence() argument
116 IT8XXX2_ECPM_PLLFREQR = pll->pll_freq; in chip_run_pll_sequence()
120 IT8XXX2_ECPM_SCDCR3 = (pll->div_jtag << 4) | pll->div_ec; in chip_run_pll_sequence()
126 IT8XXX2_ECPM_SCDCR0 = pll->div_fnd << 4; in chip_run_pll_sequence()
130 IT8XXX2_ECPM_SCDCR1 = pll->div_uart; in chip_run_pll_sequence()
132 IT8XXX2_ECPM_SCDCR2 = (pll->div_sspi << 4) | pll->div_smb; in chip_run_pll_sequence()
134 IT8XXX2_ECPM_SCDCR4 = (pll->div_usbpd << 4) | pll->div_pwm; in chip_run_pll_sequence()
137 static void chip_configure_pll(const struct pll_config_t *pll) in chip_configure_pll() argument
140 if (((IT8XXX2_ECPM_PLLFREQR & 0xf) != pll->pll_freq) || in chip_configure_pll()
141 ((IT8XXX2_ECPM_SCDCR0 & 0xf0) != (pll->div_fnd << 4)) || in chip_configure_pll()
[all …]
|
| /Zephyr-Core-3.4.0/include/zephyr/drivers/clock_control/ |
| D | stm32_clock_control.h | 92 #if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(pll))
114 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f2_pll_clock, okay) || \
115 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f4_pll_clock, okay) || \
116 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f7_pll_clock, okay) || \
117 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g0_pll_clock, okay) || \
118 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g4_pll_clock, okay) || \
119 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l4_pll_clock, okay) || \
120 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32u5_pll_clock, okay) || \
121 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wb_pll_clock, okay) || \
122 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7_pll_clock, okay)
[all …]
|
| /Zephyr-Core-3.4.0/boards/shields/st_b_lcd40_dsi1_mb1166/boards/ |
| D | stm32h747i_disco_m7.overlay | 57 * F_VCO = CLK_IN / pll-idf * 2 * pll-ndiv
58 * PHI = F_VCO / 2 / (1 << pll-odf) = lane_byte_clk
61 pll-ndiv = <100>;
62 pll-idf = <5>;
63 pll-odf = <0>;
|
| /Zephyr-Core-3.4.0/dts/arm/st/f1/ |
| D | stm32f100Xb.dtsi | 18 /delete-node/ pll;
20 pll: pll { label
22 compatible = "st,stm32f100-pll-clock";
|
| /Zephyr-Core-3.4.0/drivers/clock_control/ |
| D | clock_control_smartbond.c | 42 case DT_DEP_ORD(DT_NODELABEL(pll)): in smartbond_clock_control_on()
96 case DT_DEP_ORD(DT_NODELABEL(pll)): in smartbond_clock_control_off()
128 case DT_DEP_ORD(DT_NODELABEL(pll)): in smartbond_clock_control_get_rate()
129 *rate = DT_PROP(DT_NODELABEL(pll), clock_frequency); in smartbond_clock_control_get_rate()
181 BUILD_ASSERT(DT_NODE_HAS_STATUS(DT_NODELABEL(pll), disabled) || in smartbond_clocks_init()
202 DT_NODELABEL(pll))) { in smartbond_clocks_init()
204 SystemCoreClock = DT_PROP(DT_NODELABEL(pll), clock_frequency); in smartbond_clocks_init()
|
| /Zephyr-Core-3.4.0/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/boards/ |
| D | f1_pll_64_hsi_8.overlay | 16 &pll {
23 clocks = <&pll>;
|
| D | pll_32_hsi_16.overlay | 16 &pll {
24 clocks = <&pll>;
|
| D | f0_f3_pll_32_hsi_8.overlay | 17 &pll {
25 clocks = <&pll>;
|
| D | pll_64_hsi_16.overlay | 16 &pll {
26 clocks = <&pll>;
|
| D | f2_f4_f7_pll_64_hsi_16.overlay | 16 &pll {
26 clocks = <&pll>;
|
| D | pll_48_hsi_16.overlay | 16 &pll {
27 clocks = <&pll>;
|
| D | f0_f3_pll_32_hse_8.overlay | 18 &pll {
26 clocks = <&pll>;
|
| D | f1_pll_64_hse_8.overlay | 18 &pll {
26 clocks = <&pll>;
|
| D | pll_32_hse_8.overlay | 18 &pll {
26 clocks = <&pll>;
|
| D | pll_g0_64_hsi_16.overlay | 17 &pll {
27 clocks = <&pll>;
|
| D | pll_170_hse_24.overlay | 17 &pll {
28 clocks = <&pll>;
|
| D | wb_pll_48_hsi_16.overlay | 18 &pll {
29 clocks = <&pll>;
|
| D | f2_f4_f7_pll_100_hsi_16_ahb_2.overlay | 16 &pll {
25 clocks = <&pll>;
|
| D | f2_f4_f7_pll_64_hse_8.overlay | 18 &pll {
28 clocks = <&pll>;
|
| D | pll_64_hse_8.overlay | 18 &pll {
28 clocks = <&pll>;
|
| D | wb_pll_64_hse_32.overlay | 18 &pll {
29 clocks = <&pll>;
|
| /Zephyr-Core-3.4.0/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/ |
| D | f3_i2c1_hsi.overlay | 29 &pll {
53 &pll {
61 clocks = <&pll>;
|
| D | f0_i2c1_hsi.overlay | 29 &pll {
53 &pll {
61 clocks = <&pll>;
|
| /Zephyr-Core-3.4.0/boards/arm/legend/ |
| D | legend_25ssd.overlay | 21 &pll {
29 clocks = <&pll>;
|
| /Zephyr-Core-3.4.0/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/boards/ |
| D | pll_csi_96.overlay | 16 &pll {
27 clocks = <&pll>;
|
