1 /* SPDX-License-Identifier: Apache-2.0 */
2 /*
3 * Copyright (c) 2023 Intel Corporation
4 *
5 * Author: Adrian Warecki <adrian.warecki@intel.com>
6 */
7
8 #ifndef ZEPHYR_DRIVERS_WATCHDOG_WDT_DW_H_
9 #define ZEPHYR_DRIVERS_WATCHDOG_WDT_DW_H_
10
11 #include <zephyr/sys/util.h>
12
13 /**
14 * @file
15 * @brief Synopsys Designware Watchdog driver
16 *
17 * The DW_apb_wdt is an APB slave peripheral that can be used to prevent system lockup that may be
18 * caused by conflicting parts or programs in an SoC. This component can be configured, synthesized,
19 * and programmed based on user-defined options.
20 *
21 * The generated interrupt is passed to an interrupt controller. The generated reset is passed to a
22 * reset controller, which in turn generates a reset for the components in the system. The WDT may
23 * be reset independently to the other components.
24 *
25 * For more information about the specific IP capability, please refer to the DesignWare DW_apb_wdt
26 * Databook.
27 */
28
29 /*
30 * Control Register
31 */
32 #define WDT_CR 0x0
33
34 /*
35 * WDT enable
36 */
37 #define WDT_CR_WDT_EN BIT(0)
38
39 /* Watchdog timer disabled
40 */
41 #define WDT_EN_DISABLED 0x0
42
43 /* Watchdog timer enabled
44 */
45 #define WDT_EN_ENABLED 0x1
46
47 /*
48 * Response mode
49 */
50 #define WDT_CR_RMOD BIT(1)
51
52 /* Generate a system reset
53 */
54 #define RMOD_RESET 0x0
55
56 /* First generate an interrupt and even if it is cleared
57 * by the time a second timeout occurs then generate a system reset
58 */
59 #define RMOD_INTERRUPT 0x1
60
61 /*
62 * Reset pulse length
63 */
64 #define WDT_CR_RPL GENMASK(4, 2)
65
66 #define RPL_PCLK_CYCLES2 0x0 /* 2 pclk cycles */
67 #define RPL_PCLK_CYCLES4 0x1 /* 4 pclk cycles */
68 #define RPL_PCLK_CYCLES8 0x2 /* 8 pclk cycles */
69 #define RPL_PCLK_CYCLES16 0x3 /* 16 pclk cycles */
70 #define RPL_PCLK_CYCLES32 0x4 /* 32 pclk cycles */
71 #define RPL_PCLK_CYCLES64 0x5 /* 64 pclk cycles */
72 #define RPL_PCLK_CYCLES128 0x6 /* 128 pclk cycles */
73 #define RPL_PCLK_CYCLES256 0x7 /* 256 pclk cycles */
74
75 /*
76 * Redundant R/W bit.
77 */
78 #define WDT_CR_NO_NAME BIT(5)
79
80
81 /*
82 * Timeout Range Register
83 */
84 #define WDT_TORR 0x4
85
86 #define TORR_USER0_OR_64K 0x0 /* Time out of WDT_USER_TOP_0 or 64K Clocks */
87 #define TORR_USER1_OR_128K 0x1 /* Time out of WDT_USER_TOP_1 or 128K Clocks */
88 #define TORR_USER2_OR_256K 0x2 /* Time out of WDT_USER_TOP_2 or 256K Clocks */
89 #define TORR_USER3_OR_512K 0x3 /* Time out of WDT_USER_TOP_3 or 512K Clocks */
90 #define TORR_USER4_OR_1M 0x4 /* Time out of WDT_USER_TOP_4 or 1M Clocks */
91 #define TORR_USER5_OR_2M 0x5 /* Time out of WDT_USER_TOP_5 or 2M Clocks */
92 #define TORR_USER6_OR_4M 0x6 /* Time out of WDT_USER_TOP_6 or 4M Clocks */
93 #define TORR_USER7_OR_8M 0x7 /* Time out of WDT_USER_TOP_7 or 8M Clocks */
94 #define TORR_USER8_OR_16M 0x8 /* Time out of WDT_USER_TOP_8 or 16M Clocks */
95 #define TORR_USER9_OR_32M 0x9 /* Time out of WDT_USER_TOP_9 or 32M Clocks */
96 #define TORR_USER10_OR_64M 0xa /* Time out of WDT_USER_TOP_10 or 64M Clocks */
97 #define TORR_USER11_OR_128M 0xb /* Time out of WDT_USER_TOP_11 or 128M Clocks */
98 #define TORR_USER12_OR_256M 0xc /* Time out of WDT_USER_TOP_12 or 256M Clocks */
99 #define TORR_USER13_OR_512M 0xd /* Time out of WDT_USER_TOP_13 or 512M Clocks */
100 #define TORR_USER14_OR_1G 0xe /* Time out of WDT_USER_TOP_14 or 1G Clocks */
101 #define TORR_USER15_OR_2G 0xf /* Time out of WDT_USER_TOP_15 or 2G Clocks */
102
103 /*
104 * Timeout period
105 */
106 #define WDT_TORR_TOP GENMASK(3, 0)
107
108 /*
109 * Timeout period for initialization
110 */
111 #define WDT_TORR_TOP_INIT GENMASK(7, 4)
112
113
114 /*
115 * Current Counter Value Register.
116 * bits WDT_CNT_WIDTH - 1 to 0
117 */
118 #define WDT_CCVR 0x8
119
120 /*
121 * Counter Restart Register
122 */
123 #define WDT_CRR 0xc
124 #define WDT_CRR_MASK GENMASK(7, 0)
125
126 /*
127 * Watchdog timer restart command
128 */
129 #define WDT_CRR_RESTART_KEY 0x76
130
131
132 /*
133 * Interrupt Status Register
134 */
135 #define WDT_STAT 0x10
136 #define WDT_STAT_MASK BIT(0)
137
138
139 /*
140 * Interrupt Clear Register
141 */
142 #define WDT_EOI 0x14
143 #define WDT_EOI_MASK BIT(0)
144
145
146 /*
147 * WDT Protection level register
148 */
149 #define WDT_PROT_LEVEL 0x1c
150 #define WDT_PROT_LEVEL_MASK GENMASK(2, 0)
151
152
153 /*
154 * Component Parameters Register 5
155 * Upper limit of Timeout Period parameters
156 */
157 #define WDT_COMP_PARAM_5 0xe4
158 #define CP_WDT_USER_TOP_MAX WDT_COMP_PARAM_5
159
160
161 /*
162 * Component Parameters Register 4
163 * Upper limit of Initial Timeout Period parameters
164 */
165 #define WDT_COMP_PARAM_4 0xe8
166 #define CP_WDT_USER_TOP_INIT_MAX WDT_COMP_PARAM_4
167
168 /*
169 * Component Parameters Register 3
170 * The value of this register is derived from the WDT_TOP_RST core Consultant parameter.
171 */
172 #define WDT_COMP_PARAM_3 0xec
173 #define CD_WDT_TOP_RST WDT_COMP_PARAM_3
174
175
176 /*
177 * Component Parameters Register 2
178 * The value of this register is derived from the WDT_CNT_RST core Consultant parameter.
179 */
180 #define WDT_COMP_PARAM_2 0xf0
181 #define CP_WDT_CNT_RST WDT_COMP_PARAM_2
182
183
184 /*
185 * Component Parameters Register 1
186 */
187 #define WDT_COMP_PARAM_1 0xf4
188
189 /*
190 * The Watchdog Timer counter width.
191 */
192 #define WDT_CNT_WIDTH GENMASK(28, 24)
193
194 /*
195 * Describes the initial timeout period that is available directly after reset. It controls the
196 * reset value of the register. If WDT_HC_TOP is 1, then the default initial time period is the
197 * only possible period.
198 */
199 #define WDT_DFLT_TOP_INIT GENMASK(23, 20)
200
201 /*
202 * Selects the timeout period that is available directly after reset. It controls the reset value
203 * of the register. If WDT_HC_TOP is set to 1, then the default timeout period is the only possible
204 * timeout period. Can choose one of 16 values.
205 */
206 #define WDT_DFLT_TOP GENMASK(19, 16)
207
208 /*
209 * The reset pulse length that is available directly after reset.
210 */
211 #define WDT_DFLT_RPL GENMASK(12, 10)
212
213 /*
214 * Width of the APB Data Bus to which this component is attached.
215 */
216 #define APB_DATA_WIDTH GENMASK(9, 8)
217
218 /*
219 * APB data width is 8 bits
220 */
221 #define APB_8BITS 0x0
222
223 /*
224 * APB data width is 16 bits
225 */
226 #define APB_16BITS 0x1
227
228 /*
229 * APB data width is 32 bits
230 */
231 #define APB_32BITS 0x2
232
233 /*
234 * Configures the peripheral to have a pause enable signal (pause) on the interface that can be used
235 * to freeze the watchdog counter during pause mode.
236 */
237 #define WDT_PAUSE BIT(7)
238
239 /*
240 * When this parameter is set to 1, timeout period range is fixed. The range increments by the power
241 * of 2 from 2^16 to 2^(WDT_CNT_WIDTH-1). When this parameter is set to 0, the user must define the
242 * timeout period range (2^8 to 2^(WDT_CNT_WIDTH)-1) using the WDT_USER_TOP_(i) parameter.
243 */
244 #define WDT_USE_FIX_TOP BIT(6)
245
246 /*
247 * When set to 1, the selected timeout period(s)
248 */
249 #define WDT_HC_TOP BIT(5)
250
251 /*
252 * Configures the reset pulse length to be hard coded.
253 */
254 #define WDT_HC_RPL BIT(4)
255
256 /*
257 * Configures the output response mode to be hard coded.
258 */
259 #define WDT_HC_RMOD BIT(3)
260
261 /*
262 * When set to 1, includes a second timeout period that is used for initialization prior to the
263 * first kick.
264 */
265 #define WDT_DUAL_TOP BIT(2)
266
267 /*
268 * Describes the output response mode that is available directly after reset. Indicates the output
269 * response the WDT gives if a zero count is reached; that is, a system reset if equals 0 and
270 * an interrupt followed by a system reset, if equals 1. If WDT_HC_RMOD is 1, then default response
271 * mode is the only possible output response mode.
272 */
273 #define WDT_DFLT_RMOD BIT(1)
274
275 /*
276 * Configures the WDT to be enabled from reset. If this setting is 1, the WDT is always enabled and
277 * a write to the WDT_EN field (bit 0) of the Watchdog Timer Control Register (WDT_CR) to disable
278 * it has no effect.
279 */
280 #define WDT_ALWAYS_EN BIT(0)
281
282
283 /*
284 * Component Version Register
285 * ASCII value for each number in the version, followed by *.
286 * For example, 32_30_31_2A represents the version 2.01*.
287 */
288 #define WDT_COMP_VERSION 0xf8
289
290
291 /*
292 * Component Type Register
293 * Designware Component Type number = 0x44_57_01_20.
294 * This assigned unique hex value is constant, and is derived from the two ASCII letters "DW"
295 * followed by a 16-bit unsigned number.
296 */
297 #define WDT_COMP_TYPE 0xfc
298 #define WDT_COMP_TYPE_VALUE 0x44570120
299
300 /**
301 * @brief Enable watchdog
302 *
303 * @param base Device base address.
304 */
dw_wdt_enable(const uint32_t base)305 static inline void dw_wdt_enable(const uint32_t base)
306 {
307 uint32_t control = sys_read32(base + WDT_CR);
308
309 control |= WDT_CR_WDT_EN;
310 sys_write32(control, base + WDT_CR);
311 }
312
313 /**
314 * @brief Set response mode.
315 *
316 * Selects whether watchdog should generate interrupt on the first timeout (true) or reset system
317 * (false)
318 *
319 * @param base Device base address.
320 * @param mode Response mode.
321 * false = Generate a system reset,
322 * true = First generate an interrupt and even if it is cleared by the time a second
323 * timeout occurs then generate a system reset
324 */
dw_wdt_response_mode_set(const uint32_t base,const bool mode)325 static inline void dw_wdt_response_mode_set(const uint32_t base, const bool mode)
326 {
327 uint32_t control = sys_read32(base + WDT_CR);
328
329 if (mode)
330 control |= WDT_CR_RMOD;
331 else
332 control &= ~WDT_CR_RMOD;
333
334 sys_write32(control, base + WDT_CR);
335 }
336
337 /**
338 * @brief Set reset pulse length.
339 *
340 * @param base Device base address.
341 * @param pclk_cycles Reset pulse length selector (2 to 256 pclk cycles)
342 */
dw_wdt_reset_pulse_length_set(const uint32_t base,const uint32_t pclk_cycles)343 static inline void dw_wdt_reset_pulse_length_set(const uint32_t base, const uint32_t pclk_cycles)
344 {
345 uint32_t control = sys_read32(base + WDT_CR);
346
347 control &= ~WDT_CR_RPL;
348 control |= FIELD_PREP(WDT_CR_RPL, pclk_cycles);
349
350 sys_write32(control, base + WDT_CR);
351 }
352
353 /**
354 * @brief Set timeout period.
355 *
356 * @param base Device base address.
357 * @param timeout_period Timeout period value selector
358 */
dw_wdt_timeout_period_set(const uint32_t base,const uint32_t timeout_period)359 static inline void dw_wdt_timeout_period_set(const uint32_t base, const uint32_t timeout_period)
360 {
361 uint32_t timeout = sys_read32(base + WDT_TORR);
362
363 timeout &= ~WDT_TORR_TOP;
364 timeout |= FIELD_PREP(WDT_TORR_TOP, timeout_period);
365 sys_write32(timeout, base + WDT_TORR);
366 }
367
368 /**
369 * @brief Get actual timeout period range.
370 *
371 * @param base Device base address.
372 * @return Actual timeout period range
373 */
dw_wdt_timeout_period_get(const uint32_t base)374 static inline uint32_t dw_wdt_timeout_period_get(const uint32_t base)
375 {
376 return FIELD_GET(WDT_TORR_TOP, sys_read32(base + WDT_TORR));
377 }
378
379 /**
380 * @brief Timeout period for initialization.
381 *
382 * @param base Device base address.
383 * @param timeout_period Timeout period value selector
384 */
dw_wdt_timeout_period_init_set(const uint32_t base,const uint32_t timeout_period)385 static inline void dw_wdt_timeout_period_init_set(const uint32_t base,
386 const uint32_t timeout_period)
387 {
388 uint32_t timeout = sys_read32(base + WDT_TORR);
389
390 timeout &= ~WDT_TORR_TOP_INIT;
391 timeout |= FIELD_PREP(WDT_TORR_TOP_INIT, timeout_period);
392 sys_write32(timeout, base + WDT_TORR);
393 }
394
395 /**
396 * @brief Get WDT Current Counter Value Register.
397 *
398 * @param base Device base address.
399 * @param wdt_counter_width Watchdog Timer counter width
400 * @return The current value of the internal counter
401 */
dw_wdt_current_counter_value_register_get(const uint32_t base,uint32_t wdt_counter_width)402 static inline uint32_t dw_wdt_current_counter_value_register_get(const uint32_t base,
403 uint32_t wdt_counter_width)
404 {
405 uint32_t current_counter_value = sys_read32(base + WDT_CCVR);
406
407 current_counter_value &= (1 << (wdt_counter_width - 1));
408 return current_counter_value;
409 }
410
411 /**
412 * @brief Counter Restart
413 *
414 * Restart the WDT counter. A restart also clears the WDT interrupt.
415 *
416 * @param base Device base address.
417 */
dw_wdt_counter_restart(const uint32_t base)418 static inline void dw_wdt_counter_restart(const uint32_t base)
419 {
420 sys_write32(WDT_CRR_RESTART_KEY, base + WDT_CRR);
421 }
422
423 /**
424 * @brief Get Interrupt status
425 *
426 * @param base Device base address.
427 * @return 0x0 (INACTIVE): Interrupt is inactive,
428 * 0x1 (ACTIVE): Interrupt is active regardless of polarity
429 */
dw_wdt_interrupt_status_register_get(const uint32_t base)430 static inline uint32_t dw_wdt_interrupt_status_register_get(const uint32_t base)
431 {
432 return sys_read32(base + WDT_STAT) & 1;
433 }
434
435 /**
436 * @brief Clears the watchdog interrupt.
437 *
438 * This can be used to clear the interrupt without restarting the watchdog counter.
439 *
440 * @param base Device base address.
441 */
dw_wdt_clear_interrupt(const uint32_t base)442 static inline void dw_wdt_clear_interrupt(const uint32_t base)
443 {
444 sys_read32(base + WDT_EOI);
445 }
446
447 /**
448 * @brief Gets the upper limit of Timeout Period parameters.
449 *
450 * @param base Device base address.
451 * @return Upper limit of Timeout Period parameters.
452 */
dw_wdt_user_top_max_get(const uint32_t base)453 static inline uint32_t dw_wdt_user_top_max_get(const uint32_t base)
454 {
455 return sys_read32(base + WDT_COMP_PARAM_5);
456 }
457
458 /**
459 * @brief Gets the Upper limit of Initial Timeout Period parameters.
460 *
461 * @param base Device base address.
462 * @return Upper limit of Initial Timeout Period parameters.
463 */
dw_wdt_user_top_init_max_get(const uint32_t base)464 static inline uint32_t dw_wdt_user_top_init_max_get(const uint32_t base)
465 {
466 return sys_read32(base + WDT_COMP_PARAM_4);
467 }
468
469 /**
470 * @brief Get the default value of the timeout range that is selected after reset.
471 *
472 * @param base Device base address.
473 * @return Default timeout range after reset
474 */
dw_wdt_timeout_period_rst_get(const uint32_t base)475 static inline uint32_t dw_wdt_timeout_period_rst_get(const uint32_t base)
476 {
477 return sys_read32(base + WDT_COMP_PARAM_3);
478 }
479
480 /**
481 * @brief Get the default value of the timeout counter that is set after reset.
482 *
483 * @param base Device base address.
484 * @return Default timeout counter value
485 */
dw_wdt_cnt_rst_get(const uint32_t base)486 static inline uint32_t dw_wdt_cnt_rst_get(const uint32_t base)
487 {
488 return sys_read32(base + WDT_COMP_PARAM_2);
489 }
490
491 /**
492 * @brief Get the Watchdog timer counter width.
493 *
494 * @param base Device base address.
495 * @return Width of the counter register
496 */
dw_wdt_cnt_width_get(const uint32_t base)497 static inline uint32_t dw_wdt_cnt_width_get(const uint32_t base)
498 {
499 return FIELD_GET(WDT_CNT_WIDTH, sys_read32(base + WDT_COMP_PARAM_1)) + 16;
500 }
501
502 /**
503 * @brief Describes the initial timeout period that is available directly after reset.
504 *
505 * It controls the reset value of the register. If WDT_HC_TOP is 1, then the default initial time
506 * period is the only possible period.
507 *
508 * @param base Device base address.
509 * @return Initial timeout period
510 */
dw_wdt_dflt_timeout_period_init_get(const uint32_t base)511 static inline uint32_t dw_wdt_dflt_timeout_period_init_get(const uint32_t base)
512 {
513 return FIELD_GET(WDT_DFLT_TOP_INIT, sys_read32(base + WDT_COMP_PARAM_1));
514 }
515
516 /**
517 * @brief Get default timeout period
518 *
519 * Selects the timeout period that is available directly after reset. It controls the reset value
520 * of the register. If WDT_HC_TOP is set to 1, then the default timeout period is the only possible
521 * timeout period. Can choose one of 16 values.
522 *
523 * @param base Device base address.
524 * @return Default timeout period
525 */
dw_wdt_dflt_timeout_period_get(const uint32_t base)526 static inline uint32_t dw_wdt_dflt_timeout_period_get(const uint32_t base)
527 {
528 return FIELD_GET(WDT_DFLT_TOP, sys_read32(base + WDT_COMP_PARAM_1));
529 }
530
531 /**
532 * @brief The reset pulse length that is available directly after reset.
533 *
534 * @param base Device base address.
535 * @return Reset pulse length
536 */
dw_wdt_dflt_rpl_get(const uint32_t base)537 static inline uint32_t dw_wdt_dflt_rpl_get(const uint32_t base)
538 {
539 return FIELD_GET(WDT_DFLT_RPL, sys_read32(base + WDT_COMP_PARAM_1));
540 }
541
542 /**
543 * @brief Width of the APB Data Bus to which this component is attached.
544 *
545 * @param base Device base address.
546 * @return APB data width
547 * 0x0 (APB_8BITS): APB data width is 8 bits
548 * 0x1 (APB_16BITS): APB data width is 16 bits
549 * 0x2 (APB_32BITS): APB data width is 32 bits
550 */
dw_wdt_apb_data_width_get(const uint32_t base)551 static inline uint32_t dw_wdt_apb_data_width_get(const uint32_t base)
552 {
553 return FIELD_GET(APB_DATA_WIDTH, sys_read32(base + WDT_COMP_PARAM_1));
554 }
555
556 /**
557 * @brief Get configuration status of a pause signal
558 *
559 * Check the peripheral is configured to have a pause enable signal (pause) on the interface that
560 * can be used to freeze the watchdog counter during pause mode.
561 *
562 * @param base Device base address.
563 * @return 0x0 (DISABLED): Pause enable signal is non existent
564 * 0x1 (ENABLED): Pause enable signal is included
565 */
dw_wdt_pause_get(const uint32_t base)566 static inline uint32_t dw_wdt_pause_get(const uint32_t base)
567 {
568 return FIELD_GET(WDT_PAUSE, sys_read32(base + WDT_COMP_PARAM_1));
569 }
570
571 /**
572 * @brief Get fixed period status
573 *
574 * When this parameter is set to 1, timeout period range is fixed. The range increments by the power
575 * of 2 from 2^16 to 2^(WDT_CNT_WIDTH-1). When this parameter is set to 0, the user must define the
576 * timeout period range (2^8 to 2^(WDT_CNT_WIDTH)-1) using the WDT_USER_TOP_(i) parameter.
577 *
578 * @param base Device base address.
579 * @return 0x0 (USERDEFINED): User must define timeout values
580 * 0x1 (PREDEFINED): Use predefined timeout values
581 */
dw_wdt_use_fix_timeout_period_get(const uint32_t base)582 static inline uint32_t dw_wdt_use_fix_timeout_period_get(const uint32_t base)
583 {
584 return FIELD_GET(WDT_USE_FIX_TOP, sys_read32(base + WDT_COMP_PARAM_1));
585 }
586
587 /**
588 * @brief Checks if period is hardcoded
589 *
590 * When set to 1, the selected timeout period(s) is set to be hard coded.
591 *
592 * @param base Device base address.
593 * @return 0x0 (PROGRAMMABLE): Timeout period is programmable
594 * 0x1 (HARDCODED): Timeout period is hard coded
595 */
dw_wdt_hc_timeout_period_get(const uint32_t base)596 static inline uint32_t dw_wdt_hc_timeout_period_get(const uint32_t base)
597 {
598 return FIELD_GET(WDT_HC_TOP, sys_read32(base + WDT_COMP_PARAM_1));
599 }
600
601 /**
602 * @brief Checks if reset pulse length is hardcoded.
603 *
604 * @param base Device base address.
605 * @return 0x0 (PROGRAMMABLE): Reset pulse length is programmable
606 * 0x1 (HARDCODED): Reset pulse length is hardcoded
607 */
dw_wdt_hc_reset_pulse_length_get(const uint32_t base)608 static inline uint32_t dw_wdt_hc_reset_pulse_length_get(const uint32_t base)
609 {
610 return FIELD_GET(WDT_HC_RPL, sys_read32(base + WDT_COMP_PARAM_1));
611 }
612
613 /**
614 * @brief Checks if the output response mode is hardcoded.
615 *
616 * @param base Device base address.
617 * @return 0x0 (PROGRAMMABLE): Output response mode is programmable
618 * 0x1 (HARDCODED): Output response mode is hard coded
619 */
dw_wdt_hc_response_mode_get(const uint32_t base)620 static inline uint32_t dw_wdt_hc_response_mode_get(const uint32_t base)
621 {
622 return FIELD_GET(WDT_HC_RMOD, sys_read32(base + WDT_COMP_PARAM_1));
623 }
624
625 /**
626 * @brief Checks if a second timeout period if supported.
627 *
628 * When set to 1, includes a second timeout period that is used for initialization prior to the
629 * first kick.
630 *
631 * @param base Device base address.
632 * @return 0x0 (DISABLED): Second timeout period is not present
633 * 0x1 (ENABLED): Second timeout period is present
634 */
dw_wdt_dual_timeout_period_get(const uint32_t base)635 static inline uint32_t dw_wdt_dual_timeout_period_get(const uint32_t base)
636 {
637 return FIELD_GET(WDT_DUAL_TOP, sys_read32(base + WDT_COMP_PARAM_1));
638 }
639
640 /**
641 * @brief Get default response mode
642 *
643 * Describes the output response mode that is available directly after reset. Indicates the output
644 * response the WDT gives if a zero count is reached; that is, a system reset if equals 0 and an
645 * interrupt followed by a system reset, if equals 1. If WDT_HC_RMOD is 1, then default response
646 * mode is the only possible output response mode.
647 *
648 * @param base Device base address.
649 * @return 0x0 (DISABLED): System reset only
650 * 0x1 (ENABLED): Interrupt and system reset
651 */
dw_wdt_dflt_response_mode_get(const uint32_t base)652 static inline uint32_t dw_wdt_dflt_response_mode_get(const uint32_t base)
653 {
654 return FIELD_GET(WDT_DFLT_RMOD, sys_read32(base + WDT_COMP_PARAM_1));
655 }
656
657 /**
658 * @brief Checks if watchdog is enabled from reset
659 *
660 * If this setting is 1, the WDT is always enabled and a write to the WDT_EN field (bit 0) of the
661 * Watchdog Timer Control Register (WDT_CR) to disable it has no effect.
662 *
663 * @param base Device base address.
664 * @return 0x0 (DISABLED): Watchdog timer disabled on reset
665 * 0x1 (ENABLED): Watchdog timer enabled on reset
666 */
dw_wdt_always_en_get(const uint32_t base)667 static inline uint32_t dw_wdt_always_en_get(const uint32_t base)
668 {
669 return FIELD_GET(WDT_ALWAYS_EN, sys_read32(base + WDT_COMP_PARAM_1));
670 }
671
672 /**
673 * @brief ASCII value for each number in the version
674 *
675 * For example, 32_30_31_2A represents the version 2.01s
676 *
677 * @param base Device base address.
678 * @return Component version code
679 */
dw_wdt_comp_version_get(const uint32_t base)680 static inline uint32_t dw_wdt_comp_version_get(const uint32_t base)
681 {
682 return sys_read32(base + WDT_COMP_VERSION);
683 }
684
685 /**
686 * @brief Get Component Type
687 *
688 * @param base Device base address.
689 * @return Components type code
690 */
dw_wdt_comp_type_get(const uint32_t base)691 static inline uint32_t dw_wdt_comp_type_get(const uint32_t base)
692 {
693 return sys_read32(base + WDT_COMP_TYPE);
694 }
695
696 #endif /* !ZEPHYR_DRIVERS_WATCHDOG_WDT_DW_H_ */
697
