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/Zephyr-Core-3.4.0/subsys/logging/
Dlog_cache.c22 int log_cache_init(struct log_cache *cache, const struct log_cache_config *config) in log_cache_init() argument
24 sys_slist_init(&cache->active); in log_cache_init()
25 sys_slist_init(&cache->idle); in log_cache_init()
34 sys_slist_append(&cache->idle, &entry->node); in log_cache_init()
38 cache->cmp = config->cmp; in log_cache_init()
39 cache->item_size = config->item_size; in log_cache_init()
40 cache->hit = 0; in log_cache_init()
41 cache->miss = 0; in log_cache_init()
46 bool log_cache_get(struct log_cache *cache, uintptr_t id, uint8_t **data) in log_cache_get() argument
53 SYS_SLIST_FOR_EACH_CONTAINER(&cache->active, entry, node) { in log_cache_get()
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Dlog_cache.h39 int log_cache_init(struct log_cache *cache, const struct log_cache_config *config);
50 bool log_cache_get(struct log_cache *cache, uintptr_t id, uint8_t **data);
58 void log_cache_put(struct log_cache *cache, uint8_t *data);
68 void log_cache_release(struct log_cache *cache, uint8_t *data);
76 static inline uint32_t log_cache_get_hit(struct log_cache *cache) in log_cache_get_hit() argument
78 return cache->hit; in log_cache_get_hit()
87 static inline uint32_t log_cache_get_miss(struct log_cache *cache) in log_cache_get_miss() argument
89 return cache->miss; in log_cache_get_miss()
/Zephyr-Core-3.4.0/tests/subsys/logging/log_cache/src/
Dmain.c61 static void cache_get(struct log_cache *cache, uintptr_t id, in cache_get() argument
64 uint32_t hit = log_cache_get_hit(cache); in cache_get()
65 uint32_t miss = log_cache_get_miss(cache); in cache_get()
68 res = log_cache_get(cache, id, buf); in cache_get()
71 zassert_equal(hit + 1, log_cache_get_hit(cache), "line %u\n", line); in cache_get()
72 zassert_equal(miss, log_cache_get_miss(cache), "line %u\n", line); in cache_get()
74 zassert_equal(hit, log_cache_get_hit(cache), "line %u\n", line); in cache_get()
75 zassert_equal(miss + 1, log_cache_get_miss(cache), "line %u\n", line); in cache_get()
91 struct log_cache cache; in ZTEST() local
105 err = log_cache_init(&cache, &config); in ZTEST()
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/Zephyr-Core-3.4.0/subsys/net/l2/ieee802154/
Dieee802154_6lo_fragment.c48 static struct frag_cache cache[REASS_CACHE_SIZE]; variable
264 if (!(cache[i].size == size && cache[i].tag == tag)) { in clear_reass_cache()
268 if (cache[i].pkt) { in clear_reass_cache()
269 net_pkt_unref(cache[i].pkt); in clear_reass_cache()
272 cache[i].pkt = NULL; in clear_reass_cache()
273 cache[i].size = 0U; in clear_reass_cache()
274 cache[i].tag = 0U; in clear_reass_cache()
275 cache[i].used = false; in clear_reass_cache()
276 k_work_cancel_delayable(&cache[i].timer); in clear_reass_cache()
287 struct frag_cache *cache = CONTAINER_OF(dwork, struct frag_cache, timer); in reass_timeout() local
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/Zephyr-Core-3.4.0/doc/hardware/cache/
Dindex.rst6 This is a high-level guide to cache interface and Kconfig options related to
7 cache controllers. See :ref:`cache_api` for API reference material.
9 Zephyr has different Kconfig options to control how the cache controller is
15 instruction cache. The cache controller can be in the core or can be an
16 external cache controller for which a driver is provided.
22 options must be selected when support for data or instruction cache is
25 All the code paths related to cache control must be conditionally enabled
26 depending on these symbols. When the symbol is set the cache is considered
30 For example a platform using the data cache can enable the
32 some platform-specific code to enable and manage the d-cache.
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/Zephyr-Core-3.4.0/dts/riscv/starfive/
Dstarfive_jh7100_beagle_v.dtsi24 d-cache-block-size = <64>;
25 d-cache-sets = <64>;
26 d-cache-size = <32768>;
30 i-cache-block-size = <64>;
31 i-cache-sets = <64>;
32 i-cache-size = <32768>;
36 next-level-cache = <&cachectrl>;
53 d-cache-block-size = <64>;
54 d-cache-sets = <64>;
55 d-cache-size = <32768>;
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/Zephyr-Core-3.4.0/cmake/modules/
Duser_cache.cmake5 # Configure user cache directory.
7 # The user cache can be used for caching of data that should be persistent
11 # Only data that can be safely re-generated should be placed in this cache.
13 # Zephyr build system uses this user cache to store Zephyr compiler check
20 # - USER_CACHE_DIR: User cache directory in use.
33 set(env_suffix_LOCALAPPDATA .cache)
36 # On macOS, ~/Library/Caches is the preferred cache directory.
39 set(env_suffix_HOME .cache)
51 # that is defined and defaulting to $HOME/.cache otherwise.
83 # Zephyr's cache files go in the "zephyr" subdirectory of the
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/Zephyr-Core-3.4.0/subsys/fs/nvs/
DKconfig15 bool "Non-volatile Storage lookup cache"
17 Enable Non-volatile Storage cache, used to reduce the NVS data lookup
18 time. Each cache entry holds an address of the most recent allocation
19 table entry (ATE) for all NVS IDs that fall into that cache position.
22 int "Non-volatile Storage lookup cache size"
27 Number of entries in Non-volatile Storage lookup cache.
/Zephyr-Core-3.4.0/drivers/cache/
DKconfig5 bool "External cache controller drivers"
8 Enable support for external cache controllers drivers
16 module-str = cache
21 source "drivers/cache/Kconfig.aspeed"
/Zephyr-Core-3.4.0/arch/posix/core/
Dswap.c46 _kernel.ready_q.cache->callee_saved.thread_status; in arch_swap()
53 _current = _kernel.ready_q.cache; in arch_swap()
91 _kernel.ready_q.cache->callee_saved.thread_status; in arch_switch_to_main_thread()
97 _current = _kernel.ready_q.cache; in arch_switch_to_main_thread()
/Zephyr-Core-3.4.0/dts/riscv/andes/
Dandes_v5_ae350.dtsi27 i-cache-line-size = <32>;
28 d-cache-line-size = <32>;
44 i-cache-line-size = <32>;
45 d-cache-line-size = <32>;
61 i-cache-line-size = <32>;
62 d-cache-line-size = <32>;
78 i-cache-line-size = <32>;
79 d-cache-line-size = <32>;
95 i-cache-line-size = <32>;
96 d-cache-line-size = <32>;
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/Zephyr-Core-3.4.0/soc/xtensa/esp32s3/
DKconfig.soc141 prompt "Instruction cache size"
144 Instruction cache size to be set on application startup.
145 If you use 16KB instruction cache rather than 32KB instruction cache,
160 prompt "Instruction cache associated ways"
163 Instruction cache associated ways to be set on application startup.
177 prompt "Instruction cache line size"
180 Instruction cache line size to be set on application startup.
195 bool "Define instruction cache wrap mode"
197 If enabled, instruction cache will use wrap mode to read spi flash or spi ram.
202 prompt "Data cache size"
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/Zephyr-Core-3.4.0/boards/arc/hsdk/support/
Dopenocd.cfg65 # Enable L2 cache support for core 2.
66 $_TARGETNAME2 arc cache l2 auto 1
80 # Enable L2 cache support for core 3.
81 $_TARGETNAME3 arc cache l2 auto 1
96 # Enable L2 cache support for core 4.
97 $_TARGETNAME4 arc cache l2 auto 1
111 # Enable L2 cache support for core 1.
112 $_TARGETNAME1 arc cache l2 auto 1
Dopenocd-2-cores.cfg65 # Enable L2 cache support for core 2.
66 $_TARGETNAME2 arc cache l2 auto 1
80 # Enable L2 cache support for core 1.
81 $_TARGETNAME1 arc cache l2 auto 1
/Zephyr-Core-3.4.0/boards/arc/hsdk4xd/support/
Dopenocd.cfg65 # Enable L2 cache support for core 2.
66 $_TARGETNAME2 arc cache l2 auto 1
80 # Enable L2 cache support for core 3.
81 $_TARGETNAME3 arc cache l2 auto 1
96 # Enable L2 cache support for core 4.
97 $_TARGETNAME4 arc cache l2 auto 1
111 # Enable L2 cache support for core 1.
112 $_TARGETNAME1 arc cache l2 auto 1
/Zephyr-Core-3.4.0/subsys/fs/
DKconfig.littlefs46 Each cache buffers a portion of a block in RAM. The littlefs
47 needs a read cache, a program cache, and one additional cache
73 int "Enable flexible file cache sizes for littlefs"
76 littlefs requires a per-file buffer to cache data.
79 different cache sizes for different partitions this preallocation is
81 using a large cache size and a larger number of files using a
82 smaller cache size. In that case application should provide a
99 For the purpose of heap size calculation the size of each cache block
/Zephyr-Core-3.4.0/scripts/west_commands/
Dbuild_helpers.py131 cache = zcmake.CMakeCache.from_build_dir(path)
133 cache = {}
135 if 'ZEPHYR_BASE' in cache or 'ZEPHYR_TOOLCHAIN_VARIANT' in cache:
/Zephyr-Core-3.4.0/
D.gitignore22 # The .cache directory will be used to cache toolchain capabilities if
24 .cache
/Zephyr-Core-3.4.0/samples/subsys/fs/fat_fs/boards/
Dnrf52840dk_nrf52840_qspi.overlay32 /* cache-size == page erase size */
33 cache-size = <4096>;
Dnrf52840dk_nrf52840.overlay45 /* cache-size == page erase size */
46 cache-size = <4096>;
/Zephyr-Core-3.4.0/lib/os/
DKconfig85 bool "Use cache flag"
87 Use instance specific configuration flag for cache handling.
90 bool "Always handle cache"
92 Handle cache writeback and invalidation for all instances. Option used
96 bool "Never handle cache"
98 Discar cache handling for all instances. Option used to avoid runtime
112 int "Remote cache line size"
116 this value should be set to the data cache line size of the remote core.
117 If local data cache line is detected at runtime then it should be
/Zephyr-Core-3.4.0/boards/arc/em_starterkit/
DKconfig.board14 EM7D and EM11D have access to 128MB DRAM and use i-cache and d-cache.
/Zephyr-Core-3.4.0/modules/
DKconfig.open-amp32 bool "Build OpenAMP with vrings cache operations enabled"
35 Build OpenAMP with vrings cache operations enabled.
/Zephyr-Core-3.4.0/drivers/gpio/
Dgpio_fxl6408.c67 static int read_port_regs(const struct device *dev, uint8_t reg, uint8_t *cache) in read_port_regs() argument
78 *cache = port_data; in read_port_regs()
79 LOG_DBG("Read: REG[0x%X] = 0x%X", reg, *cache); in read_port_regs()
97 uint8_t *cache, uint8_t value) in write_port_regs() argument
102 if (*cache != value) { in write_port_regs()
109 *cache = value; in write_port_regs()
110 LOG_DBG("Write: REG[0x%X] = 0x%X", reg, *cache); in write_port_regs()
/Zephyr-Core-3.4.0/subsys/settings/src/
Dsettings_nvs.c82 cf->cache[cf->cache_next].name_hash = name_hash; in settings_nvs_cache_add()
83 cf->cache[cf->cache_next++].name_id = name_id; in settings_nvs_cache_add()
95 if (cf->cache[i].name_hash != name_hash) { in settings_nvs_cache_match()
99 if (cf->cache[i].name_id <= NVS_NAMECNT_ID) { in settings_nvs_cache_match()
103 rc = nvs_read(&cf->cf_nvs, cf->cache[i].name_id, rdname, len); in settings_nvs_cache_match()
114 return cf->cache[i].name_id; in settings_nvs_cache_match()

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