Home
last modified time | relevance | path

Searched refs:a5 (Results 1 – 25 of 31) sorted by relevance

12

/Zephyr-Core-3.4.0/arch/riscv/core/
Duserspace.S28 li a5, 0 # Counter
29 sw a5, 0(a2) # Init error value to 0
32 add a4, a0, a5 # Determine character address
38 bne a5, a1, continue # Check if max length is reached
41 mv a0, a5 # Return counter value (length)
45 addi a5, a5, 1 # Increment counter
Dcoredump.c24 uint32_t a5; member
72 arch_blk.r.a5 = esf->a5; in arch_coredump_info_dump()
Dfatal.c41 LOG_ERR(" a5: " PR_REG, esf->a5); in z_riscv_fatal_error()
45 LOG_ERR(" a5: " PR_REG " t5: " PR_REG, esf->a5, esf->t5); in z_riscv_fatal_error()
/Zephyr-Core-3.4.0/arch/xtensa/core/
Dwindow_vectors.S56 s32e a0, a5, -16 /* save a0 to call[j+1]'s stack frame */
57 s32e a1, a5, -12 /* save a1 to call[j+1]'s stack frame */
58 s32e a2, a5, -8 /* save a2 to call[j+1]'s stack frame */
59 s32e a3, a5, -4 /* save a3 to call[j+1]'s stack frame */
78 l32e a0, a5, -16 /* restore a0 from call[i+1]'s stack frame */
79 l32e a1, a5, -12 /* restore a1 from call[i+1]'s stack frame */
80 l32e a2, a5, -8 /* restore a2 from call[i+1]'s stack frame */
81 l32e a3, a5, -4 /* restore a3 from call[i+1]'s stack frame */
140 s32e a5, a0, -28 /* save a5 to call[j]'s stack frame */
169 l32e a5, a7, -28 /* restore a5 from call[i]'s stack frame */
[all …]
Ddebug_helpers_asm.S27 l32i a6, a5, 0
Dcoredump.c66 uint32_t a5; member
150 arch_blk.r.a5 = frame->blks[regs_blk_remaining].r1; in arch_coredump_info_dump()
Dcrt1.S37 # define ARG4 a5 /* 4th outgoing call argument */
Dxtensa-asm2-util.S63 s32i a5, a1, 4
110 l32i a5, a2, 4
/Zephyr-Core-3.4.0/arch/xtensa/core/startup/
Dreset-vector.S109 movi a5, CORE_STATE_SIGNATURE
118 sub a4, a4, a5
240 sub a4, a4, a5
249 addi a5, a7, - PWRSTAT_WAKEUP_RESET
251 movnez a7, a5, a4
412 extui a5, a8, 0, 2 /* lower two bit indicate whether cached */
415 moveqz a9, a10, a5 /* ... that region is non-cacheable */
416 addx4 a5, a8, a3 /* index into _xtos_mpu_attribs table */
418 movgez a5, a3, a8 /* if not valid attrib, use Illegal */
419 l32i a5, a5, 0 /* load access rights, memtype from table
[all …]
/Zephyr-Core-3.4.0/include/zephyr/arch/arm64/
Darm-smccc.h20 unsigned long a5; member
42 unsigned long a4, unsigned long a5,
55 unsigned long a4, unsigned long a5,
/Zephyr-Core-3.4.0/tests/bluetooth/ctrl_sw_privacy_unit/src/
Dmain.c42 bt_addr_t a1, a2, a3, a4, a5; in helper_privacy_add() local
49 bt_addr_copy(&a5, BT_ADDR_INIT(0x52, 0x53, 0x54, 0x55, 0x56, 0x57)); in helper_privacy_add()
73 prpa_cache_add(&a5); in helper_privacy_add()
74 pos = prpa_cache_find(&a5); in helper_privacy_add()
/Zephyr-Core-3.4.0/drivers/console/
Dxtensa_sim_console.c23 register int a5 __asm__ ("a5") = 1; in console_out()
30 : "a" (a2), "a" (a3), "a" (a4), "a" (a5) in console_out()
Dwinstream_console.c30 register int a5 __asm__("a5") = len; in winstream_console_trace_out()
32 __asm__ volatile("simcall" : "+r"(a2), "+r"(a3) : "r"(a4), "r"(a5) : "memory"); in winstream_console_trace_out()
/Zephyr-Core-3.4.0/tests/lib/cmsis_dsp/common/
Dtest_common.h54 #define DEFINE_TEST_VARIANT5(suite, name, variant, a1, a2, a3, a4, a5) \ argument
57 test_##name(a1, a2, a3, a4, a5); \
60 #define DEFINE_TEST_VARIANT6(suite, name, variant, a1, a2, a3, a4, a5, a6) \ argument
63 test_##name(a1, a2, a3, a4, a5, a6); \
66 #define DEFINE_TEST_VARIANT7(suite, name, variant, a1, a2, a3, a4, a5, a6, a7) \ argument
69 test_##name(a1, a2, a3, a4, a5, a6, a7); \
96 #define DEFINE_TEST_VARIANT5(name, variant, a1, a2, a3, a4, a5) \ argument
99 test_##name(a1, a2, a3, a4, a5); \
102 #define DEFINE_TEST_VARIANT6(name, variant, a1, a2, a3, a4, a5, a6) \ argument
105 test_##name(a1, a2, a3, a4, a5, a6); \
[all …]
/Zephyr-Core-3.4.0/samples/drivers/spi_bitbang/
DREADME.rst38 wrote 0101 00ff 00a5 0000 0102
44 wrote 0101 00ff 00a5 0000 0102
50 wrote 0101 00ff 00a5 0000 0102
/Zephyr-Core-3.4.0/arch/xtensa/include/
Dxtensa-asm2-context.h178 uintptr_t a5; member
199 uintptr_t a5; member
215 uintptr_t a5; member
/Zephyr-Core-3.4.0/subsys/logging/backends/
Dlog_backend_xtensa_sim.c28 register int a5 __asm__ ("a5") = length; in char_out()
32 : "a"(a2), "a"(a3), "a"(a4), "a"(a5)); in char_out()
/Zephyr-Core-3.4.0/include/zephyr/drivers/sip_svc/
Dsip_svc_driver.h73 unsigned long *a4, unsigned long *a5, unsigned long *a6,
272 unsigned long *a4, unsigned long *a5, unsigned long *a6,
277 unsigned long *a5, unsigned long *a6, in z_impl_sip_svc_plat_async_res_req() argument
290 __ASSERT(a5, "a5 shouldn't be NULL"); in z_impl_sip_svc_plat_async_res_req()
295 return api->sip_svc_plat_async_res_req(dev, a0, a1, a2, a3, a4, a5, a6, a7, buf, size); in z_impl_sip_svc_plat_async_res_req()
Dsip_svc_proto.h140 unsigned long a5; member
/Zephyr-Core-3.4.0/include/zephyr/arch/riscv/
Dexp.h69 unsigned long a5; /* function argument */ member
Dsyscall.h49 register unsigned long a5 __asm__ ("a5") = arg6; in arch_syscall_invoke6()
54 : "r" (a1), "r" (a2), "r" (a3), "r" (a4), "r" (a5), in arch_syscall_invoke6()
/Zephyr-Core-3.4.0/drivers/sip_svc/
Dsip_smc_intel_socfpga.c118 unsigned long *a4, unsigned long *a5, unsigned long *a6, in intel_sip_smc_plat_async_res_req() argument
193 LOG_DBG("\tres->a5 %08lx", res->a5); in intel_sip_secure_monitor_call()
/Zephyr-Core-3.4.0/include/zephyr/
Ddevicetree.h4146 #define DT_CAT5(a1, a2, a3, a4, a5) a1 ## a2 ## a3 ## a4 ## a5 argument
4148 #define DT_CAT6(a1, a2, a3, a4, a5, a6) a1 ## a2 ## a3 ## a4 ## a5 ## a6 argument
4150 #define DT_CAT7(a1, a2, a3, a4, a5, a6, a7) \ argument
4151 a1 ## a2 ## a3 ## a4 ## a5 ## a6 ## a7
4153 #define DT_CAT8(a1, a2, a3, a4, a5, a6, a7, a8) \ argument
4154 a1 ## a2 ## a3 ## a4 ## a5 ## a6 ## a7 ## a8
/Zephyr-Core-3.4.0/subsys/sip_svc/
Dsip_svc_agilex_mailbox_shell.c141 request.a5 = 0; in cmd_close()
309 request.a5 = 0; in cmd_send()
/Zephyr-Core-3.4.0/arch/riscv/core/offsets/
Doffsets.c99 GEN_OFFSET_SYM(z_arch_esf_t, a5);

12