1 /* 2 * Copyright (c) 2021 Linaro Limited 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_STM32_AFIO_H_ 8 #define ZEPHYR_STM32_AFIO_H_ 9 10 #define STM32_REMAP_REG_MASK 0x1U 11 #define STM32_REMAP_REG_SHIFT 0U 12 #define STM32_REMAP_SHIFT_MASK 0x1FU 13 #define STM32_REMAP_SHIFT_SHIFT 1U 14 #define STM32_REMAP_MASK_MASK 0x3U 15 #define STM32_REMAP_MASK_SHIFT 6U 16 #define STM32_REMAP_VAL_MASK 0x3U 17 #define STM32_REMAP_VAL_SHIFT 8U 18 19 /** 20 * @brief STM32F1 Remap configuration bit field. 21 * 22 * - reg (0/1) [ 0 : 0 ] 23 * - shift (0..31) [ 1 : 5 ] 24 * - mask (0x1, 0x3) [ 6 : 7 ] 25 * - val (0..3) [ 8 : 9 ] 26 * 27 * @param reg AFIO_MAPRx register (MAPR, MAPR2). 28 * @param shift Position within AFIO_MAPRx. 29 * @param mask Mask for the AFIO_MAPRx field. 30 * @param val Remap value (0, 1, 2 or 3). 31 */ 32 #define STM32_REMAP(val, mask, shift, reg) \ 33 ((((reg) & STM32_REMAP_REG_MASK) << STM32_REMAP_REG_SHIFT) | \ 34 (((shift) & STM32_REMAP_SHIFT_MASK) << STM32_REMAP_SHIFT_SHIFT) | \ 35 (((mask) & STM32_REMAP_MASK_MASK) << STM32_REMAP_MASK_SHIFT) | \ 36 (((val) & STM32_REMAP_VAL_MASK) << STM32_REMAP_VAL_SHIFT)) 37 38 39 /* Accessors for remap value */ 40 41 /** 42 * Obtain register field from remap configuration. 43 * 44 * @param remap Remap bit field value. 45 */ 46 #define STM32_REMAP_REG_GET(remap) \ 47 (((remap) >> STM32_REMAP_REG_SHIFT) & STM32_REMAP_REG_MASK) 48 49 /** 50 * Obtain position field from remap configuration. 51 * 52 * @param remap Remap bit field value. 53 */ 54 #define STM32_REMAP_SHIFT_GET(remap) \ 55 (((remap) >> STM32_REMAP_SHIFT_SHIFT) & STM32_REMAP_SHIFT_MASK) 56 57 /** 58 * Obtain mask field from remap configuration. 59 * 60 * @param remap Remap bit field value. 61 */ 62 #define STM32_REMAP_MASK_GET(remap) \ 63 (((remap) >> STM32_REMAP_MASK_SHIFT) & STM32_REMAP_MASK_MASK) 64 65 /** 66 * Obtain value field from remap configuration. 67 * 68 * @param remap Remap bit field value. 69 */ 70 #define STM32_REMAP_VAL_GET(remap) \ 71 (((remap) >> STM32_REMAP_VAL_SHIFT) & STM32_REMAP_VAL_MASK) 72 73 74 /* Remap values definitions, according to RM0008.pdf */ 75 76 #define STM32_AFIO_MAPR 0U 77 #define STM32_AFIO_MAPR2 1U 78 79 /** Device not remappable **/ 80 #define NO_REMAP 0 81 82 /** SPI1 (no remap) */ 83 #define SPI1_REMAP0 STM32_REMAP(0U, 0x1U, 0U, STM32_AFIO_MAPR) 84 /** SPI1 (remap) */ 85 #define SPI1_REMAP1 STM32_REMAP(1U, 0x1U, 0U, STM32_AFIO_MAPR) 86 87 /** I2C1 (no remap) */ 88 #define I2C1_REMAP0 STM32_REMAP(0U, 0x1U, 1U, STM32_AFIO_MAPR) 89 /** I2C1 (remap) */ 90 #define I2C1_REMAP1 STM32_REMAP(1U, 0x1U, 1U, STM32_AFIO_MAPR) 91 92 /** USART1 (no remap) */ 93 #define USART1_REMAP0 STM32_REMAP(0U, 0x1U, 2U, STM32_AFIO_MAPR) 94 /** USART1 (remap) */ 95 #define USART1_REMAP1 STM32_REMAP(1U, 0x1U, 2U, STM32_AFIO_MAPR) 96 97 /** USART2 (no remap) */ 98 #define USART2_REMAP0 STM32_REMAP(0U, 0x1U, 3U, STM32_AFIO_MAPR) 99 /** USART2 (remap) */ 100 #define USART2_REMAP1 STM32_REMAP(1U, 0x1U, 3U, STM32_AFIO_MAPR) 101 102 /** USART3 (no remap) */ 103 #define USART3_REMAP0 STM32_REMAP(0U, 0x3U, 4U, STM32_AFIO_MAPR) 104 /** USART3 (partial remap) */ 105 #define USART3_REMAP1 STM32_REMAP(1U, 0x3U, 4U, STM32_AFIO_MAPR) 106 /** USART3 (full remap) */ 107 #define USART3_REMAP2 STM32_REMAP(3U, 0x3U, 4U, STM32_AFIO_MAPR) 108 109 /** TIM1 (no remap) */ 110 #define TIM1_REMAP0 STM32_REMAP(0U, 0x3U, 6U, STM32_AFIO_MAPR) 111 /** TIM1 (partial remap) */ 112 #define TIM1_REMAP1 STM32_REMAP(1U, 0x3U, 6U, STM32_AFIO_MAPR) 113 /** TIM1 (full remap) */ 114 #define TIM1_REMAP2 STM32_REMAP(3U, 0x3U, 6U, STM32_AFIO_MAPR) 115 116 /** TIM2 (no remap) */ 117 #define TIM2_REMAP0 STM32_REMAP(0U, 0x3U, 8U, STM32_AFIO_MAPR) 118 /** TIM2 (partial remap 1) */ 119 #define TIM2_REMAP1 STM32_REMAP(1U, 0x3U, 8U, STM32_AFIO_MAPR) 120 /** TIM2 (partial remap 2) */ 121 #define TIM2_REMAP2 STM32_REMAP(2U, 0x3U, 8U, STM32_AFIO_MAPR) 122 /** TIM2 (full remap) */ 123 #define TIM2_REMAP3 STM32_REMAP(3U, 0x3U, 8U, STM32_AFIO_MAPR) 124 125 /** TIM3 (no remap) */ 126 #define TIM3_REMAP0 STM32_REMAP(0U, 0x3U, 10U, STM32_AFIO_MAPR) 127 /** TIM3 (partial remap 1) */ 128 #define TIM3_REMAP1 STM32_REMAP(1U, 0x3U, 10U, STM32_AFIO_MAPR) 129 /** TIM3 (partial remap 2) */ 130 #define TIM3_REMAP2 STM32_REMAP(2U, 0x3U, 10U, STM32_AFIO_MAPR) 131 /** TIM3 (full remap) */ 132 #define TIM3_REMAP3 STM32_REMAP(3U, 0x3U, 10U, STM32_AFIO_MAPR) 133 134 /** TIM4 (no remap) */ 135 #define TIM4_REMAP0 STM32_REMAP(0U, 0x1U, 12U, STM32_AFIO_MAPR) 136 /** TIM4 (remap) */ 137 #define TIM4_REMAP1 STM32_REMAP(1U, 0x1U, 12U, STM32_AFIO_MAPR) 138 139 /** CAN (no remap) */ 140 #define CAN_REMAP0 STM32_REMAP(0U, 0x3U, 13U, STM32_AFIO_MAPR) 141 /** CAN (partial remap) */ 142 #define CAN_REMAP1 STM32_REMAP(2U, 0x3U, 13U, STM32_AFIO_MAPR) 143 /** CAN (full remap) */ 144 #define CAN_REMAP2 STM32_REMAP(3U, 0x3U, 13U, STM32_AFIO_MAPR) 145 146 /** CAN1 alias */ 147 #define CAN1_REMAP0 CAN_REMAP0 148 #define CAN1_REMAP1 CAN_REMAP1 149 #define CAN1_REMAP2 CAN_REMAP2 150 151 /** ETH (no remap) */ 152 #define ETH_REMAP0 STM32_REMAP(0U, 0x1U, 21U, STM32_AFIO_MAPR) 153 /** ETH (remap) */ 154 #define ETH_REMAP1 STM32_REMAP(1U, 0x1U, 21U, STM32_AFIO_MAPR) 155 156 /** CAN2 (no remap) */ 157 #define CAN2_REMAP0 STM32_REMAP(0U, 0x1U, 22U, STM32_AFIO_MAPR) 158 /** CAN2 (remap) */ 159 #define CAN2_REMAP1 STM32_REMAP(1U, 0x1U, 22U, STM32_AFIO_MAPR) 160 161 /** SPI3 (no remap) */ 162 #define SPI3_REMAP0 STM32_REMAP(0U, 0x1U, 28U, STM32_AFIO_MAPR) 163 /** SPI3 (remap) */ 164 #define SPI3_REMAP1 STM32_REMAP(1U, 0x1U, 28U, STM32_AFIO_MAPR) 165 166 /** I2S3 (SPI3) (no remap) */ 167 #define I2S3_REMAP0 SPI3_REMAP0 168 /** I2S3 (SPI3) (remap) */ 169 #define I2S3_REMAP1 SPI3_REMAP1 170 171 /** TIM9 (no remap) */ 172 #define TIM9_REMAP0 STM32_REMAP(0U, 0x1U, 5U, STM32_AFIO_MAPR2) 173 /** TIM9 (remap) */ 174 #define TIM9_REMAP1 STM32_REMAP(1U, 0x1U, 5U, STM32_AFIO_MAPR2) 175 176 /** TIM10 (no remap) */ 177 #define TIM10_REMAP0 STM32_REMAP(0U, 0x1U, 6U, STM32_AFIO_MAPR2) 178 /** TIM10 (remap) */ 179 #define TIM10_REMAP1 STM32_REMAP(1U, 0x1U, 6U, STM32_AFIO_MAPR2) 180 181 /** TIM11 (no remap) */ 182 #define TIM11_REMAP0 STM32_REMAP(0U, 0x1U, 7U, STM32_AFIO_MAPR2) 183 /** TIM11 (remap) */ 184 #define TIM11_REMAP1 STM32_REMAP(1U, 0x1U, 7U, STM32_AFIO_MAPR2) 185 186 /** TIM13 (no remap) */ 187 #define TIM13_REMAP0 STM32_REMAP(0U, 0x1U, 8U, STM32_AFIO_MAPR2) 188 /** TIM13 (remap) */ 189 #define TIM13_REMAP1 STM32_REMAP(1U, 0x1U, 8U, STM32_AFIO_MAPR2) 190 191 /** TIM14 (no remap) */ 192 #define TIM14_REMAP0 STM32_REMAP(0U, 0x1U, 9U, STM32_AFIO_MAPR2) 193 /** TIM14 (remap) */ 194 #define TIM14_REMAP1 STM32_REMAP(1U, 0x1U, 9U, STM32_AFIO_MAPR2) 195 196 /** TIM15 (no remap) */ 197 #define TIM15_REMAP0 STM32_REMAP(0U, 0x1U, 0U, STM32_AFIO_MAPR2) 198 /** TIM15 (remap) */ 199 #define TIM15_REMAP1 STM32_REMAP(1U, 0x1U, 0U, STM32_AFIO_MAPR2) 200 201 /** TIM16 (no remap) */ 202 #define TIM16_REMAP0 STM32_REMAP(0U, 0x1U, 1U, STM32_AFIO_MAPR2) 203 /** TIM16 (remap) */ 204 #define TIM16_REMAP1 STM32_REMAP(1U, 0x1U, 1U, STM32_AFIO_MAPR2) 205 206 /** TIM17 (no remap) */ 207 #define TIM17_REMAP0 STM32_REMAP(0U, 0x1U, 2U, STM32_AFIO_MAPR2) 208 /** TIM17 (remap) */ 209 #define TIM17_REMAP1 STM32_REMAP(1U, 0x1U, 2U, STM32_AFIO_MAPR2) 210 211 #endif /* ZEPHYR_STM32_AFIO_H_ */ 212
