Home
last modified time | relevance | path

Searched refs:STM32_SRC_PLL2_P (Results 1 – 8 of 8) sorted by relevance

/Zephyr-Core-3.4.0/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/boards/
Dspi1_pll2p_1.overlay23 <&rcc STM32_SRC_PLL2_P SPI123_SEL(1)>;
/Zephyr-Core-3.4.0/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/src/
Dtest_stm32_clock_configuration.c69 } else if (pclken[1].bus == STM32_SRC_PLL2_P) { in ZTEST()
/Zephyr-Core-3.4.0/include/zephyr/dt-bindings/clock/
Dstm32h7_clock.h17 #define STM32_SRC_PLL2_P 0x004 macro
Dstm32u5_clock.h17 #define STM32_SRC_PLL2_P 0x004 macro
Dstm32h5_clock.h17 #define STM32_SRC_PLL2_P 0x004 macro
/Zephyr-Core-3.4.0/drivers/clock_control/
Dclock_stm32_ll_h5.c127 ((src_clk == STM32_SRC_PLL2_P) && IS_ENABLED(STM32_PLL2_P_ENABLED)) || in enabled_clock()
286 case STM32_SRC_PLL2_P: in stm32_clock_control_get_subsys_rate()
Dclock_stm32_ll_u5.c136 ((src_clk == STM32_SRC_PLL2_P) && IS_ENABLED(STM32_PLL2_P_ENABLED)) || in enabled_clock()
304 case STM32_SRC_PLL2_P: in stm32_clock_control_get_subsys_rate()
Dclock_stm32_ll_h7.c345 ((src_clk == STM32_SRC_PLL2_P) && IS_ENABLED(STM32_PLL2_P_ENABLED)) || in enabled_clock()
519 case STM32_SRC_PLL2_P: in stm32_clock_control_get_subsys_rate()