| /Zephyr-Core-3.4.0/include/zephyr/dt-bindings/clock/ |
| D | stm32l1_clock.h | 23 #define STM32_SRC_LSI 0x003 macro
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| D | stm32f1_clock.h | 23 #define STM32_SRC_LSI 0x004 macro
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| D | stm32f4_clock.h | 31 #define STM32_SRC_LSI 0x005 macro
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| D | stm32c0_clock.h | 25 #define STM32_SRC_LSI 0x004 macro
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| D | stm32f0_clock.h | 22 #define STM32_SRC_LSI 0x003 macro
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| D | stm32l0_clock.h | 24 #define STM32_SRC_LSI 0x003 macro
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| D | stm32wb_clock.h | 27 #define STM32_SRC_LSI 0x004 macro
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| D | stm32wl_clock.h | 27 #define STM32_SRC_LSI 0x003 macro
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| D | stm32f3_clock.h | 23 #define STM32_SRC_LSI 0x007 macro
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| D | stm32f7_clock.h | 31 #define STM32_SRC_LSI 0x005 macro
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| D | stm32g4_clock.h | 28 #define STM32_SRC_LSI 0x005 macro
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| D | stm32g0_clock.h | 27 #define STM32_SRC_LSI 0x006 macro
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| /Zephyr-Core-3.4.0/boards/arm/olimex_lora_stm32wl_devkit/ |
| D | olimex_lora_stm32wl_devkit.dts | 52 <&rcc STM32_SRC_LSI LPTIM1_SEL(1)>;
120 <&rcc STM32_SRC_LSI RTC_SEL(2)>;
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| /Zephyr-Core-3.4.0/drivers/timer/ |
| D | stm32_lptim_timer.c | 38 {.bus = STM32_SRC_LSI, .enr = LPTIM1_SEL(1)}
87 #if (((DT_CLOCKS_CELL_BY_IDX(DT_DRV_INST(0), 1, bus) == STM32_SRC_LSI) && \
371 if (lptim_clk[1].bus == STM32_SRC_LSI) { in sys_clock_driver_init()
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| /Zephyr-Core-3.4.0/boards/arm/nucleo_l476rg/ |
| D | nucleo_l476rg.dts | 81 <&rcc STM32_SRC_LSI LPTIM1_SEL(1)>;
164 <&rcc STM32_SRC_LSI RTC_SEL(2)>;
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| /Zephyr-Core-3.4.0/boards/arm/nucleo_g071rb/ |
| D | nucleo_g071rb.dts | 92 <&rcc STM32_SRC_LSI RTC_SEL(2)>;
175 <&rcc STM32_SRC_LSI LPTIM1_SEL(1)>;
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| /Zephyr-Core-3.4.0/drivers/clock_control/ |
| D | clock_stm32_ll_common.c | 134 #if defined(STM32_SRC_LSI) in enabled_clock()
135 case STM32_SRC_LSI: in enabled_clock()
389 #if defined(STM32_SRC_LSI) in stm32_clock_control_get_subsys_rate()
390 case STM32_SRC_LSI: in stm32_clock_control_get_subsys_rate()
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| /Zephyr-Core-3.4.0/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/src/ |
| D | test_stm32_clock_configuration_lptim.c | 55 } else if (pclken[1].bus == STM32_SRC_LSI) { in ZTEST()
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| /Zephyr-Core-3.4.0/boards/arm/segger_trb_stm32f407/ |
| D | segger_trb_stm32f407.dts | 72 <&rcc STM32_SRC_LSI RTC_SEL(2)>;
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| /Zephyr-Core-3.4.0/boards/arm/nucleo_g0b1re/ |
| D | nucleo_g0b1re.dts | 103 <&rcc STM32_SRC_LSI RTC_SEL(2)>;
218 <&rcc STM32_SRC_LSI LPTIM1_SEL(1)>;
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| /Zephyr-Core-3.4.0/boards/arm/nucleo_g474re/ |
| D | nucleo_g474re.dts | 161 <&rcc STM32_SRC_LSI LPTIM1_SEL(1)>;
167 <&rcc STM32_SRC_LSI RTC_SEL(2)>;
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| /Zephyr-Core-3.4.0/boards/arm/stm32373c_eval/ |
| D | stm32373c_eval.dts | 78 <&rcc STM32_SRC_LSI RTC_SEL(2)>;
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| /Zephyr-Core-3.4.0/drivers/counter/ |
| D | counter_ll_stm32_rtc.c | 470 {.bus = STM32_SRC_LSI, .enr = RTC_SEL(2)}
487 #if DT_INST_CLOCKS_CELL(1, bus) == STM32_SRC_LSI
497 #if DT_INST_CLOCKS_CELL(1, bus) == STM32_SRC_LSI
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| /Zephyr-Core-3.4.0/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/ |
| D | g0_i2c1_sysclk_lptim1_lsi.overlay | 75 <&rcc STM32_SRC_LSI LPTIM1_SEL(1)>;
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| /Zephyr-Core-3.4.0/boards/arm/steval_fcu001v1/ |
| D | steval_fcu001v1.dts | 94 <&rcc STM32_SRC_LSI RTC_SEL(2)>;
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