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Searched refs:STM32_CLOCK_BUS_APB1_2 (Results 1 – 25 of 38) sorted by relevance

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/Zephyr-Core-3.4.0/include/zephyr/dt-bindings/clock/
Dstm32c0_clock.h13 #define STM32_CLOCK_BUS_APB1_2 0x040 macro
16 #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1_2
Dstm32_clock.h14 #define STM32_CLOCK_BUS_APB1_2 4 macro
Dstm32g0_clock.h13 #define STM32_CLOCK_BUS_APB1_2 0x040 macro
16 #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1_2
Dstm32wb_clock.h14 #define STM32_CLOCK_BUS_APB1_2 0x05c macro
Dstm32wl_clock.h14 #define STM32_CLOCK_BUS_APB1_2 0x05c macro
Dstm32g4_clock.h14 #define STM32_CLOCK_BUS_APB1_2 0x05c macro
Dstm32l4_clock.h14 #define STM32_CLOCK_BUS_APB1_2 0x05c macro
Dstm32h7_clock.h45 #define STM32_CLOCK_BUS_APB1_2 0x0EC macro
Dstm32u5_clock.h42 #define STM32_CLOCK_BUS_APB1_2 0x0A0 macro
Dstm32h5_clock.h42 #define STM32_CLOCK_BUS_APB1_2 0x0A0 macro
/Zephyr-Core-3.4.0/dts/arm/st/u5/
Dstm32u595.dtsi42 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000040>;
54 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000080>;
/Zephyr-Core-3.4.0/samples/boards/stm32/power_mgmt/serial_wakeup/boards/
Dnucleo_wl55jc.overlay14 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000001>,
Dstm32l562e_dk.overlay23 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000001>,
/Zephyr-Core-3.4.0/dts/arm/st/c0/
Dstm32c0.dtsi177 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00004000>;
195 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000800>;
229 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00008000>;
246 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00020000>;
263 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00040000>;
292 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00100000>;
/Zephyr-Core-3.4.0/dts/arm/st/g0/
Dstm32g0.dtsi211 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00004000>;
240 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000800>;
284 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00008000>;
306 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00020000>;
328 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00040000>;
376 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00001000>;
394 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00100000>;
Dstm32g070.dtsi35 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00010000>;
Dstm32g051.dtsi47 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00010000>;
/Zephyr-Core-3.4.0/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/
Dg0_i2c1_hsi_lptim1_lse_adc1_pllp.overlay80 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00100000>,
/Zephyr-Core-3.4.0/dts/arm/st/l4/
Dstm32l496.dtsi33 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000002>;
Dstm32l452.dtsi77 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000002>;
/Zephyr-Core-3.4.0/dts/arm/st/h5/
Dstm32h562.dtsi78 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000001>;
96 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000002>;
303 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000200>;
/Zephyr-Core-3.4.0/dts/arm/st/g4/
Dstm32g473.dtsi91 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000002>;
/Zephyr-Core-3.4.0/boards/arm/nucleo_u575zi_q/
Dnucleo_u575zi_q-common.dtsi169 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000200>,
/Zephyr-Core-3.4.0/drivers/clock_control/
Dclock_stm32_ll_common.c321 #if defined(STM32_CLOCK_BUS_APB1_2) in stm32_clock_control_get_subsys_rate()
322 case STM32_CLOCK_BUS_APB1_2: in stm32_clock_control_get_subsys_rate()
/Zephyr-Core-3.4.0/boards/arm/stm32h573i_dk/
Dstm32h573i_dk.dts204 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000200>,

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