| /Zephyr-Core-3.4.0/tests/drivers/memc/ram/src/ |
| D | main.c | 49 #define RAM_SIZE DT_REG_SIZE(DT_NODELABEL(ram0)) macro
67 test_ram_rw(buf_ram0, RAM_SIZE); in ZTEST()
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| /Zephyr-Core-3.4.0/soc/xtensa/intel_adsp/cavs/include/intel_tgl_adsp/ |
| D | adsp_memory.h | 23 #define RAM_SIZE (L2_SRAM_SIZE - CONFIG_HP_SRAM_RESERVE - VECTOR_TBL_SIZE) macro
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| /Zephyr-Core-3.4.0/include/zephyr/arch/arm/aarch32/cortex_a_r/scripts/ |
| D | linker.ld | 43 #define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K) macro
45 (CONFIG_SRAM_SIZE * 1K - RAM_SIZE))
47 #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K) macro
51 #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K) macro
81 RAM (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE
340 __kernel_ram_end = RAM_ADDR + RAM_SIZE;
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| /Zephyr-Core-3.4.0/cmake/linker_script/arm/ |
| D | linker.cmake | 25 math(EXPR RAM_SIZE "(${CONFIG_SRAM_SIZE} + 0) * 1024" OUTPUT_FORMAT HEXADECIMAL)
26 math(EXPR IDT_ADDR "${RAM_ADDR} + ${RAM_SIZE}" OUTPUT_FORMAT HEXADECIMAL)
34 zephyr_linker_memory(NAME RAM FLAGS wx START ${RAM_ADDR} SIZE ${RAM_SIZE})
139 zephyr_linker_symbol(OBJECT REGION_RAM SYMBOL __kernel_ram_end EXPR "(${RAM_ADDR} + ${RAM_SIZE})")
142 zephyr_linker_symbol(OBJECT REGION_RAM SYMBOL ARM_LIB_STACKHEAP EXPR "(${RAM_ADDR} + ${RAM_SIZE})" …
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| /Zephyr-Core-3.4.0/include/zephyr/arch/arm/aarch32/cortex_m/scripts/ |
| D | linker.ld | 43 #define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K) macro
45 (CONFIG_SRAM_SIZE * 1K - RAM_SIZE))
47 #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K) macro
51 #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K) macro
81 RAM (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE
367 __kernel_ram_end = RAM_ADDR + RAM_SIZE;
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| /Zephyr-Core-3.4.0/soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/ |
| D | adsp_memory.h | 28 #define RAM_SIZE (L2_SRAM_SIZE - CONFIG_HP_SRAM_RESERVE - VECTOR_TBL_SIZE) macro
|
| /Zephyr-Core-3.4.0/soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/ |
| D | adsp_memory.h | 28 #define RAM_SIZE (L2_SRAM_SIZE - CONFIG_HP_SRAM_RESERVE - VECTOR_TBL_SIZE) macro
|
| /Zephyr-Core-3.4.0/include/zephyr/arch/arm64/scripts/ |
| D | linker.ld | 40 #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K) macro
62 RAM (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE
303 __kernel_ram_end = RAM_ADDR + RAM_SIZE;
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| /Zephyr-Core-3.4.0/soc/arm64/nxp_imx/mimx9/ |
| D | linker.ld | 40 #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K) macro
62 RAM (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE
320 __kernel_ram_end = RAM_ADDR + RAM_SIZE;
|
| /Zephyr-Core-3.4.0/soc/riscv/openisa_rv32m1/ |
| D | linker.ld | 59 #define RAM_SIZE KB(CONFIG_SRAM_SIZE) macro
75 RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE
|
| /Zephyr-Core-3.4.0/soc/arm/nuvoton_npcx/common/ecst/ |
| D | ecst_args.py | 61 RAM_SIZE = 0x01 variable
|
| /Zephyr-Core-3.4.0/soc/riscv/riscv-privileged/andes_v5/ae350/ |
| D | linker.ld | 58 #define RAM_SIZE KB(CONFIG_SRAM_SIZE) macro
86 RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE
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| /Zephyr-Core-3.4.0/include/zephyr/arch/riscv/common/ |
| D | linker.ld | 57 #define RAM_SIZE KB(CONFIG_SRAM_SIZE) macro
80 RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE
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| /Zephyr-Core-3.4.0/soc/riscv/riscv-ite/it8xxx2/ |
| D | linker.ld | 50 #define RAM_SIZE KB(CONFIG_SRAM_SIZE) macro
77 RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE
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| /Zephyr-Core-3.4.0/soc/xtensa/intel_adsp/ace/ |
| D | ace-link.ld | 110 len = RAM_SIZE
114 len = RAM_SIZE
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| /Zephyr-Core-3.4.0/soc/xtensa/intel_adsp/cavs/include/ |
| D | xtensa-cavs-linker.ld | 122 len = RAM_SIZE
126 len = RAM_SIZE
|
