1 /* 2 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MEC172X_GPIO_H 8 #define _MEC172X_GPIO_H 9 10 #include <stdint.h> 11 #include <stddef.h> 12 13 #define NUM_MCHP_GPIO_PORTS 6u 14 #define MAX_NUM_MCHP_GPIO (NUM_MCHP_GPIO_PORTS * 32u) 15 16 #define MCHP_GPIO_CTRL_OFS 0u 17 #define MCHP_GPIO_PARIN_OFS 0x0300u 18 #define MCHP_GPIO_PAROUT_OFS 0x0380u 19 #define MCHP_GPIO_LOCK_OFS 0x03e8u 20 #define MCHP_GPIO_CTRL2_OFS 0x0500u 21 22 /* MEC172XH-B0-SZ (144-pin) */ 23 #define MCHP_GPIO_PORT_A_BITMAP 0x7FFFFF9Du /* GPIO_0000 - 0036 GIRQ11 */ 24 #define MCHP_GPIO_PORT_B_BITMAP 0x7FFFFFFDu /* GPIO_0040 - 0076 GIRQ10 */ 25 #define MCHP_GPIO_PORT_C_BITMAP 0x07FFFCF7u /* GPIO_0100 - 0136 GIRQ09 */ 26 #define MCHP_GPIO_PORT_D_BITMAP 0x272EFFFFu /* GPIO_0140 - 0176 GIRQ08 */ 27 #define MCHP_GPIO_PORT_E_BITMAP 0x00DE00FFu /* GPIO_0200 - 0236 GIRQ12 */ 28 #define MCHP_GPIO_PORT_F_BITMAP 0x0000397Fu /* GPIO_0240 - 0276 GIRQ26 */ 29 30 #define MCHP_GPIO_PORT_A_DRVSTR_BITMAP 0x7FFFFF9Du 31 #define MCHP_GPIO_PORT_B_DRVSTR_BITMAP 0x7FFFFFFDu 32 #define MCHP_GPIO_PORT_C_DRVSTR_BITMAP 0x07FFFCF7u 33 #define MCHP_GPIO_PORT_D_DRVSTR_BITMAP 0x272EFFFFu 34 #define MCHP_GPIO_PORT_E_DRVSTR_BITMAP 0x00DE00FFu 35 #define MCHP_GPIO_PORT_F_DRVSTR_BITMAP 0x0000397Fu 36 37 /* 32-bit Control register */ 38 #define MCHP_GPIO_CTRL_MASK 0x0101ffffu 39 /* bits[15:0] of Control register */ 40 #define MCHP_GPIO_CTRL_CFG_MASK 0xffffu 41 42 /* Disable interrupt detect and pad */ 43 #define MCHP_GPIO_CTRL_DIS_PIN 0x8040u 44 45 #define MCHP_GPIO_CTRL_DFLT 0x8040u 46 #define MCHP_GPIO_CTRL_DFLT_MASK 0xffffu 47 48 #define GPIO000_CTRL_DFLT 0x1040u 49 #define GPIO062_CTRL_DFLT 0x8240u 50 #define GPIO116_CTRL_DFLT 0x0041u 51 #define GPIO161_CTRL_DFLT 0x1040u 52 #define GPIO162_CTRL_DFLT 0x1040u 53 #define GPIO170_CTRL_DFLT 0x0041u 54 #define GPIO234_CTRL_DFLT 0x1040u 55 56 /* GPIO Control register field definitions. */ 57 58 /* bits[1:0] internal pull up/down selection */ 59 #define MCHP_GPIO_CTRL_PUD_POS 0 60 #define MCHP_GPIO_CTRL_PUD_MASK0 0x03u 61 #define MCHP_GPIO_CTRL_PUD_MASK 0x03u 62 #define MCHP_GPIO_CTRL_PUD_NONE 0x00u 63 #define MCHP_GPIO_CTRL_PUD_PU 0x01u 64 #define MCHP_GPIO_CTRL_PUD_PD 0x02u 65 /* Repeater(keeper) mode */ 66 #define MCHP_GPIO_CTRL_PUD_RPT 0x03u 67 68 /* bits[3:2] power gating */ 69 #define MCHP_GPIO_CTRL_PWRG_POS 2 70 #define MCHP_GPIO_CTRL_PWRG_MASK0 0x03u 71 #define MCHP_GPIO_CTRL_PWRG_VTR_IO 0 72 #define MCHP_GPIO_CTRL_PWRG_VCC_IO SHLU32(1, MCHP_GPIO_CTRL_PWRG_POS) 73 #define MCHP_GPIO_CTRL_PWRG_OFF SHLU32(2, MCHP_GPIO_CTRL_PWRG_POS) 74 #define MCHP_GPIO_CTRL_PWRG_RSVD SHLU32(3, MCHP_GPIO_CTRL_PWRG_POS) 75 #define MCHP_GPIO_CTRL_PWRG_MASK SHLU32(3, MCHP_GPIO_CTRL_PWRG_POS) 76 77 /* bits[7:4] interrupt detection mode */ 78 #define MCHP_GPIO_CTRL_IDET_POS 4 79 #define MCHP_GPIO_CTRL_IDET_MASK0 0x0fu 80 #define MCHP_GPIO_CTRL_IDET_LVL_LO 0 81 #define MCHP_GPIO_CTRL_IDET_LVL_HI SHLU32(1, MCHP_GPIO_CTRL_IDET_POS) 82 #define MCHP_GPIO_CTRL_IDET_DISABLE SHLU32(4, MCHP_GPIO_CTRL_IDET_POS) 83 #define MCHP_GPIO_CTRL_IDET_REDGE SHLU32(0xd, MCHP_GPIO_CTRL_IDET_POS) 84 #define MCHP_GPIO_CTRL_IDET_FEDGE SHLU32(0xe, MCHP_GPIO_CTRL_IDET_POS) 85 #define MCHP_GPIO_CTRL_IDET_BEDGE SHLU32(0xf, MCHP_GPIO_CTRL_IDET_POS) 86 #define MCHP_GPIO_CTRL_IDET_MASK SHLU32(0xf, MCHP_GPIO_CTRL_IDET_POS) 87 88 /* bit[8] output buffer type: push-pull or open-drain */ 89 #define MCHP_GPIO_CTRL_BUFT_POS 8 90 #define MCHP_GPIO_CTRL_BUFT_MASK BIT(MCHP_GPIO_CTRL_BUFT_POS) 91 #define MCHP_GPIO_CTRL_BUFT_OPENDRAIN BIT(MCHP_GPIO_CTRL_BUFT_POS) 92 #define MCHP_GPIO_CTRL_BUFT_PUSHPULL 0 93 94 /* bit[9] direction */ 95 #define MCHP_GPIO_CTRL_DIR_POS 9 96 #define MCHP_GPIO_CTRL_DIR_MASK BIT(MCHP_GPIO_CTRL_DIR_POS) 97 #define MCHP_GPIO_CTRL_DIR_OUTPUT BIT(MCHP_GPIO_CTRL_DIR_POS) 98 #define MCHP_GPIO_CTRL_DIR_INPUT 0 99 100 /* 101 * bit[10] Alternate output disable. Default==0(alternate output enabled) 102 * GPIO output value is controlled by bit[16] of this register. 103 * Set bit[10]=1 if you wish to control pin output using the parallel 104 * GPIO output register bit for this pin. 105 */ 106 #define MCHP_GPIO_CTRL_AOD_POS 10 107 #define MCHP_GPIO_CTRL_AOD_MASK BIT(MCHP_GPIO_CTRL_AOD_POS) 108 #define MCHP_GPIO_CTRL_AOD_DIS BIT(MCHP_GPIO_CTRL_AOD_POS) 109 110 /* bit[11] GPIO function output polarity */ 111 #define MCHP_GPIO_CTRL_POL_POS 11 112 #define MCHP_GPIO_CTRL_POL_INVERT BIT(MCHP_GPIO_CTRL_POL_POS) 113 114 /* bits[14:12] pin mux (function) */ 115 #define MCHP_GPIO_CTRL_MUX_POS 12 116 #define MCHP_GPIO_CTRL_MUX_MASK0 0x07u 117 #define MCHP_GPIO_CTRL_MUX_MASK SHLU32(7, MCHP_GPIO_CTRL_MUX_POS) 118 #define MCHP_GPIO_CTRL_MUX_F0 0 119 #define MCHP_GPIO_CTRL_MUX_GPIO MCHP_GPIO_CTRL_MUX_F0 120 #define MCHP_GPIO_CTRL_MUX_F1 SHLU32(1, MCHP_GPIO_CTRL_MUX_POS) 121 #define MCHP_GPIO_CTRL_MUX_F2 SHLU32(2, MCHP_GPIO_CTRL_MUX_POS) 122 #define MCHP_GPIO_CTRL_MUX_F3 SHLU32(3, MCHP_GPIO_CTRL_MUX_POS) 123 #define MCHP_GPIO_CTRL_MUX_F4 SHLU32(4, MCHP_GPIO_CTRL_MUX_POS) 124 #define MCHP_GPIO_CTRL_MUX_F5 SHLU32(5, MCHP_GPIO_CTRL_MUX_POS) 125 #define MCHP_GPIO_CTRL_MUX_F6 SHLU32(6, MCHP_GPIO_CTRL_MUX_POS) 126 #define MCHP_GPIO_CTRL_MUX_F7 SHLU32(7, MCHP_GPIO_CTRL_MUX_POS) 127 #define MCHP_GPIO_CTRL_MUX(n) SHLU32(((n) & 0x7u), MCHP_GPIO_CTRL_MUX_POS) 128 129 /* 130 * bit[15] Disables input pad leaving output pad enabled 131 * Useful for reducing power consumption of output only pins. 132 */ 133 #define MCHP_GPIO_CTRL_INPAD_DIS_POS 15 134 #define MCHP_GPIO_CTRL_INPAD_DIS_MASK BIT(MCHP_GPIO_CTRL_INPAD_DIS_POS) 135 #define MCHP_GPIO_CTRL_INPAD_DIS BIT(MCHP_GPIO_CTRL_INPAD_DIS_POS) 136 137 /* bit[16]: Alternate output pin value. Enabled when bit[10]==0(default) */ 138 #define MCHP_GPIO_CTRL_OUTVAL_POS 16 139 #define MCHP_GPIO_CTRL_OUTV_HI BIT(MCHP_GPIO_CTRL_OUTVAL_POS) 140 141 /* bit[24] Input pad value. Always live unless input pad is powered down */ 142 #define MCHP_GPIO_CTRL_INPAD_VAL_POS 24 143 #define MCHP_GPIO_CTRL_INPAD_VAL_HI BIT(MCHP_GPIO_CTRL_INPAD_VAL_POS) 144 145 #define MCHP_GPIO_CTRL_DRIVE_OD_HI \ 146 (MCHP_GPIO_CTRL_BUFT_OPENDRAIN + MCHP_GPIO_CTRL_DIR_OUTPUT + \ 147 MCHP_GPIO_CTRL_MUX_GPIO + MCHP_GPIO_CTRL_OUTV_HI) 148 149 /* 150 * Each GPIO pin implements a second control register. 151 * GPIO Control 2 register selects pin drive strength and slew rate. 152 * bit[0] = slew rate: 0=slow, 1=fast 153 * bits[5:4] = drive strength 154 * 00b = 2mA (default) 155 * 01b = 4mA 156 * 10b = 8mA 157 * 11b = 12mA 158 */ 159 #define MCHP_GPIO_CTRL2_OFFSET 0x0500u 160 #define MCHP_GPIO_CTRL2_SLEW_POS 0 161 #define MCHP_GPIO_CTRL2_SLEW_MASK 0x01u 162 #define MCHP_GPIO_CTRL2_SLEW_SLOW 0 163 #define MCHP_GPIO_CTRL2_SLEW_FAST BIT(MCHP_GPIO_CTRL2_SLEW_POS) 164 #define MCHP_GPIO_CTRL2_DRV_STR_POS 4 165 #define MCHP_GPIO_CTRL2_DRV_STR_MASK 0x30u 166 #define MCHP_GPIO_CTRL2_DRV_STR_2MA 0 167 #define MCHP_GPIO_CTRL2_DRV_STR_4MA 0x10u 168 #define MCHP_GPIO_CTRL2_DRV_STR_8MA 0x20u 169 #define MCHP_GPIO_CTRL2_DRV_STR_12MA 0x30u 170 171 /* Interfaces to any C modules */ 172 #ifdef __cplusplus 173 extern "C" { 174 #endif 175 176 /* GPIO pin numbers SZ (144-pin) package */ 177 enum mec_gpio_idx { 178 MCHP_GPIO_0000_ID = 0, 179 MCHP_GPIO_0002_ID = 2, 180 MCHP_GPIO_0003_ID, 181 MCHP_GPIO_0004_ID, 182 MCHP_GPIO_0007_ID = 7, 183 MCHP_GPIO_0010_ID, 184 MCHP_GPIO_0011_ID, 185 MCHP_GPIO_0012_ID, 186 MCHP_GPIO_0013_ID, 187 MCHP_GPIO_0014_ID, 188 MCHP_GPIO_0015_ID, 189 MCHP_GPIO_0016_ID, 190 MCHP_GPIO_0017_ID, 191 MCHP_GPIO_0020_ID, 192 MCHP_GPIO_0021_ID, 193 MCHP_GPIO_0022_ID, 194 MCHP_GPIO_0023_ID, 195 MCHP_GPIO_0024_ID, 196 MCHP_GPIO_0025_ID, 197 MCHP_GPIO_0026_ID, 198 MCHP_GPIO_0027_ID, 199 MCHP_GPIO_0030_ID, 200 MCHP_GPIO_0031_ID, 201 MCHP_GPIO_0032_ID, 202 MCHP_GPIO_0033_ID, 203 MCHP_GPIO_0034_ID, 204 MCHP_GPIO_0035_ID, 205 MCHP_GPIO_0036_ID, 206 MCHP_GPIO_0040_ID = 32, 207 MCHP_GPIO_0042_ID = 34, 208 MCHP_GPIO_0043_ID, 209 MCHP_GPIO_0044_ID, 210 MCHP_GPIO_0045_ID, 211 MCHP_GPIO_0046_ID, 212 MCHP_GPIO_0047_ID, 213 MCHP_GPIO_0050_ID, 214 MCHP_GPIO_0051_ID, 215 MCHP_GPIO_0052_ID, 216 MCHP_GPIO_0053_ID, 217 MCHP_GPIO_0054_ID, 218 MCHP_GPIO_0055_ID, 219 MCHP_GPIO_0056_ID, 220 MCHP_GPIO_0057_ID, 221 MCHP_GPIO_0060_ID, 222 MCHP_GPIO_0061_ID, 223 MCHP_GPIO_0062_ID, 224 MCHP_GPIO_0063_ID, 225 MCHP_GPIO_0064_ID, 226 MCHP_GPIO_0065_ID, 227 MCHP_GPIO_0066_ID, 228 MCHP_GPIO_0067_ID, 229 MCHP_GPIO_0070_ID, 230 MCHP_GPIO_0071_ID, 231 MCHP_GPIO_0072_ID, 232 MCHP_GPIO_0073_ID, 233 MCHP_GPIO_0074_ID, 234 MCHP_GPIO_0075_ID, 235 MCHP_GPIO_0076_ID, 236 MCHP_GPIO_0100_ID = 64, 237 MCHP_GPIO_0101_ID, 238 MCHP_GPIO_0102_ID, 239 MCHP_GPIO_0104_ID = 68, 240 MCHP_GPIO_0105_ID, 241 MCHP_GPIO_0106_ID, 242 MCHP_GPIO_0107_ID, 243 MCHP_GPIO_0112_ID = 74, 244 MCHP_GPIO_0113_ID, 245 MCHP_GPIO_0114_ID, 246 MCHP_GPIO_0115_ID, 247 MCHP_GPIO_0116_ID, 248 MCHP_GPIO_0117_ID, 249 MCHP_GPIO_0120_ID = 80, 250 MCHP_GPIO_0121_ID, 251 MCHP_GPIO_0122_ID, 252 MCHP_GPIO_0123_ID, 253 MCHP_GPIO_0124_ID, 254 MCHP_GPIO_0125_ID, 255 MCHP_GPIO_0126_ID, 256 MCHP_GPIO_0127_ID, 257 MCHP_GPIO_0130_ID, 258 MCHP_GPIO_0131_ID, 259 MCHP_GPIO_0132_ID, 260 MCHP_GPIO_0140_ID = 96, 261 MCHP_GPIO_0141_ID, 262 MCHP_GPIO_0142_ID, 263 MCHP_GPIO_0143_ID, 264 MCHP_GPIO_0144_ID, 265 MCHP_GPIO_0145_ID, 266 MCHP_GPIO_0146_ID, 267 MCHP_GPIO_0147_ID, 268 MCHP_GPIO_0150_ID, 269 MCHP_GPIO_0151_ID, 270 MCHP_GPIO_0152_ID, 271 MCHP_GPIO_0153_ID, 272 MCHP_GPIO_0154_ID, 273 MCHP_GPIO_0155_ID, 274 MCHP_GPIO_0156_ID, 275 MCHP_GPIO_0157_ID, 276 MCHP_GPIO_0161_ID = 113, 277 MCHP_GPIO_0162_ID, 278 MCHP_GPIO_0165_ID = 117, 279 MCHP_GPIO_0170_ID = 120, 280 MCHP_GPIO_0171_ID, 281 MCHP_GPIO_0175_ID = 125, 282 MCHP_GPIO_0200_ID = 128, 283 MCHP_GPIO_0201_ID, 284 MCHP_GPIO_0202_ID, 285 MCHP_GPIO_0203_ID, 286 MCHP_GPIO_0204_ID, 287 MCHP_GPIO_0205_ID, 288 MCHP_GPIO_0206_ID, 289 MCHP_GPIO_0207_ID, 290 MCHP_GPIO_0221_ID = 145, 291 MCHP_GPIO_0222_ID, 292 MCHP_GPIO_0223_ID, 293 MCHP_GPIO_0224_ID, 294 MCHP_GPIO_0226_ID = 150, 295 MCHP_GPIO_0227_ID, 296 MCHP_GPIO_0240_ID = 160, 297 MCHP_GPIO_0241_ID, 298 MCHP_GPIO_0242_ID, 299 MCHP_GPIO_0243_ID, 300 MCHP_GPIO_0244_ID, 301 MCHP_GPIO_0245_ID, 302 MCHP_GPIO_0246_ID, 303 MCHP_GPIO_0254_ID = 172, 304 MCHP_GPIO_0255_ID, 305 MCHP_GPIO_MAX_ID 306 }; 307 308 #define MCHP_GPIO_PIN2PORT(pin_id) ((uint32_t)(pin_id) >> 5) 309 310 #define MAX_MCHP_GPIO_BANK 6u 311 #define MCHP_GPIO_LOCK5_IDX 0u 312 #define MCHP_GPIO_LOCK4_IDX 1u 313 #define MCHP_GPIO_LOCK3_IDX 2u 314 #define MCHP_GPIO_LOCK2_IDX 3u 315 #define MCHP_GPIO_LOCK1_IDX 4u 316 #define MCHP_GPIO_LOCK0_IDX 5u 317 #define MCHP_GPIO_LOCK_MAX_IDX 6u 318 319 /* Helper functions */ 320 enum mchp_gpio_pud { 321 MCHP_GPIO_NO_PUD = 0, 322 MCHP_GPIO_PU_EN, 323 MCHP_GPIO_PD_EN, 324 MCHP_GPIO_RPT_EN, 325 }; 326 327 enum mchp_gpio_pwrgate { 328 MCHP_GPIO_PWRGT_VTR = 0, 329 MCHP_GPIO_PWRGT_VCC, 330 MCHP_GPIO_PWRGD_OFF, 331 }; 332 333 enum mchp_gpio_idet { 334 MCHP_GPIO_IDET_LO_LVL = 0u, 335 MCHP_GPIO_IDET_HI_LVL = 0x01u, 336 MCHP_GPIO_IDET_DIS = 0x04u, 337 MCHP_GPIO_IDET_RISING_EDGE = 0x0du, 338 MCHP_GPIO_IDET_FALLING_EDGE = 0x0eu, 339 MCHP_GPIO_IDET_BOTH_EDGES = 0x0fu 340 }; 341 342 enum mchp_gpio_outbuf { 343 MCHP_GPIO_PUSH_PULL = 0, 344 MCHP_GPIO_OPEN_DRAIN, 345 }; 346 347 enum mchp_gpio_dir { 348 MCHP_GPIO_DIR_IN = 0, 349 MCHP_GPIO_DIR_OUT, 350 }; 351 352 enum mchp_gpio_parout_en { 353 MCHP_GPIO_PAROUT_DIS = 0, 354 MCHP_GPIO_PAROUT_EN, 355 }; 356 357 enum mchp_gpio_pol { 358 MCHP_GPIO_POL_NORM = 0, 359 MCHP_GPIO_POL_INV, 360 }; 361 362 enum mchp_gpio_mux { 363 MCHP_GPIO_MUX_GPIO = 0u, 364 MCHP_GPIO_MUX_FUNC1, 365 MCHP_GPIO_MUX_FUNC2, 366 MCHP_GPIO_MUX_FUNC3, 367 MCHP_GPIO_MUX_FUNC4, 368 MCHP_GPIO_MUX_FUNC5, 369 MCHP_GPIO_MUX_FUNC6, 370 MCHP_GPIO_MUX_FUNC7, 371 MCHP_GPIO_MUX_MAX 372 }; 373 374 enum mchp_gpio_inpad_ctrl { 375 MCHP_GPIO_INPAD_CTRL_EN = 0, 376 MCHP_GPIO_INPAD_CTRL_DIS, 377 }; 378 379 enum mchp_gpio_alt_out { 380 MCHP_GPIO_ALT_OUT_LO = 0, 381 MCHP_GPIO_ALT_OUT_HI, 382 }; 383 384 enum mchp_gpio_slew { 385 MCHP_GPIO_SLEW_SLOW = 0, 386 MCHP_GPIO_SLEW_FAST, 387 }; 388 389 enum mchp_gpio_drv_str { 390 MCHP_GPIO_DRV_STR_2MA = 0, 391 MCHP_GPIO_DRV_STR_4MA, 392 MCHP_GPIO_DRV_STR_8MA, 393 MCHP_GPIO_DRV_STR_12MA, 394 }; 395 396 /** @brief GPIO control registers by pin name */ 397 struct gpio_ctrl_regs { 398 volatile uint32_t CTRL_0000; 399 uint32_t RSVD1[1]; 400 volatile uint32_t CTRL_0002; 401 volatile uint32_t CTRL_0003; 402 volatile uint32_t CTRL_0004; 403 uint32_t RSVD2[2]; 404 volatile uint32_t CTRL_0007; 405 volatile uint32_t CTRL_0010; 406 volatile uint32_t CTRL_0011; 407 volatile uint32_t CTRL_0012; 408 volatile uint32_t CTRL_0013; 409 volatile uint32_t CTRL_0014; 410 volatile uint32_t CTRL_0015; 411 volatile uint32_t CTRL_0016; 412 volatile uint32_t CTRL_0017; 413 volatile uint32_t CTRL_0020; 414 volatile uint32_t CTRL_0021; 415 volatile uint32_t CTRL_0022; 416 volatile uint32_t CTRL_0023; 417 volatile uint32_t CTRL_0024; 418 volatile uint32_t CTRL_0025; 419 volatile uint32_t CTRL_0026; 420 volatile uint32_t CTRL_0027; 421 volatile uint32_t CTRL_0030; 422 volatile uint32_t CTRL_0031; 423 volatile uint32_t CTRL_0032; 424 volatile uint32_t CTRL_0033; 425 volatile uint32_t CTRL_0034; 426 volatile uint32_t CTRL_0035; 427 volatile uint32_t CTRL_0036; 428 uint32_t RSVD3[1]; 429 volatile uint32_t CTRL_0040; 430 uint32_t RSVD4[1]; 431 volatile uint32_t CTRL_0042; 432 volatile uint32_t CTRL_0043; 433 volatile uint32_t CTRL_0044; 434 volatile uint32_t CTRL_0045; 435 volatile uint32_t CTRL_0046; 436 volatile uint32_t CTRL_0047; 437 volatile uint32_t CTRL_0050; 438 volatile uint32_t CTRL_0051; 439 volatile uint32_t CTRL_0052; 440 volatile uint32_t CTRL_0053; 441 volatile uint32_t CTRL_0054; 442 volatile uint32_t CTRL_0055; 443 volatile uint32_t CTRL_0056; 444 volatile uint32_t CTRL_0057; 445 volatile uint32_t CTRL_0060; 446 volatile uint32_t CTRL_0061; 447 volatile uint32_t CTRL_0062; 448 volatile uint32_t CTRL_0063; 449 volatile uint32_t CTRL_0064; 450 volatile uint32_t CTRL_0065; 451 volatile uint32_t CTRL_0066; 452 volatile uint32_t CTRL_0067; 453 volatile uint32_t CTRL_0070; 454 volatile uint32_t CTRL_0071; 455 volatile uint32_t CTRL_0072; 456 volatile uint32_t CTRL_0073; 457 volatile uint32_t CTRL_0074; 458 volatile uint32_t CTRL_0075; 459 volatile uint32_t CTRL_0076; 460 uint32_t RSVD5[1]; 461 volatile uint32_t CTRL_0100; 462 volatile uint32_t CTRL_0101; 463 volatile uint32_t CTRL_0102; 464 uint32_t RSVD6[1]; 465 volatile uint32_t CTRL_0104; 466 volatile uint32_t CTRL_0105; 467 volatile uint32_t CTRL_0106; 468 volatile uint32_t CTRL_0107; 469 uint32_t RSVD7[2]; 470 volatile uint32_t CTRL_0112; 471 volatile uint32_t CTRL_0113; 472 volatile uint32_t CTRL_0114; 473 volatile uint32_t CTRL_0115; 474 volatile uint32_t CTRL_0116; 475 volatile uint32_t CTRL_0117; 476 volatile uint32_t CTRL_0120; 477 volatile uint32_t CTRL_0121; 478 volatile uint32_t CTRL_0122; 479 volatile uint32_t CTRL_0123; 480 volatile uint32_t CTRL_0124; 481 volatile uint32_t CTRL_0125; 482 volatile uint32_t CTRL_0126; 483 volatile uint32_t CTRL_0127; 484 volatile uint32_t CTRL_0130; 485 volatile uint32_t CTRL_0131; 486 volatile uint32_t CTRL_0132; 487 uint32_t RSVD9[5]; 488 volatile uint32_t CTRL_0140; 489 volatile uint32_t CTRL_0141; 490 volatile uint32_t CTRL_0142; 491 volatile uint32_t CTRL_0143; 492 volatile uint32_t CTRL_0144; 493 volatile uint32_t CTRL_0145; 494 volatile uint32_t CTRL_0146; 495 volatile uint32_t CTRL_0147; 496 volatile uint32_t CTRL_0150; 497 volatile uint32_t CTRL_0151; 498 volatile uint32_t CTRL_0152; 499 volatile uint32_t CTRL_0153; 500 volatile uint32_t CTRL_0154; 501 volatile uint32_t CTRL_0155; 502 volatile uint32_t CTRL_0156; 503 volatile uint32_t CTRL_0157; 504 uint32_t RSVD10[1]; 505 volatile uint32_t CTRL_0161; 506 volatile uint32_t CTRL_0162; 507 uint32_t RSVD11[2]; 508 volatile uint32_t CTRL_0165; 509 uint32_t RSVD12[2]; 510 volatile uint32_t CTRL_0170; 511 volatile uint32_t CTRL_0171; 512 uint32_t RSVD13[3]; 513 volatile uint32_t CTRL_0175; 514 uint32_t RSVD14[2]; 515 volatile uint32_t CTRL_0200; 516 volatile uint32_t CTRL_0201; 517 volatile uint32_t CTRL_0202; 518 volatile uint32_t CTRL_0203; 519 volatile uint32_t CTRL_0204; 520 volatile uint32_t CTRL_0205; 521 volatile uint32_t CTRL_0206; 522 volatile uint32_t CTRL_0207; 523 uint32_t RSVD15[9]; 524 volatile uint32_t CTRL_0221; 525 volatile uint32_t CTRL_0222; 526 volatile uint32_t CTRL_0223; 527 volatile uint32_t CTRL_0224; 528 uint32_t RSVD16[1]; 529 volatile uint32_t CTRL_0226; 530 volatile uint32_t CTRL_0227; 531 uint32_t RSVD17[8]; 532 volatile uint32_t CTRL_0240; 533 volatile uint32_t CTRL_0241; 534 volatile uint32_t CTRL_0242; 535 volatile uint32_t CTRL_0243; 536 volatile uint32_t CTRL_0244; 537 volatile uint32_t CTRL_0245; 538 volatile uint32_t CTRL_0246; 539 uint32_t RSVD18[5]; 540 volatile uint32_t CTRL_0254; 541 volatile uint32_t CTRL_0255; 542 }; 543 544 /** @brief GPIO Control 2 registers by pin name */ 545 struct gpio_ctrl2_regs { 546 volatile uint32_t CTRL2_0000; 547 uint32_t RSVD1[1]; 548 volatile uint32_t CTRL2_0002; 549 volatile uint32_t CTRL2_0003; 550 volatile uint32_t CTRL2_0004; 551 uint32_t RSVD2[2]; 552 volatile uint32_t CTRL2_0007; 553 volatile uint32_t CTRL2_0010; 554 volatile uint32_t CTRL2_0011; 555 volatile uint32_t CTRL2_0012; 556 volatile uint32_t CTRL2_0013; 557 volatile uint32_t CTRL2_0014; 558 volatile uint32_t CTRL2_0015; 559 volatile uint32_t CTRL2_0016; 560 volatile uint32_t CTRL2_0017; 561 volatile uint32_t CTRL2_0020; 562 volatile uint32_t CTRL2_0021; 563 volatile uint32_t CTRL2_0022; 564 volatile uint32_t CTRL2_0023; 565 volatile uint32_t CTRL2_0024; 566 volatile uint32_t CTRL2_0025; 567 volatile uint32_t CTRL2_0026; 568 volatile uint32_t CTRL2_0027; 569 volatile uint32_t CTRL2_0030; 570 volatile uint32_t CTRL2_0031; 571 volatile uint32_t CTRL2_0032; 572 volatile uint32_t CTRL2_0033; 573 volatile uint32_t CTRL2_0034; 574 volatile uint32_t CTRL2_0035; 575 volatile uint32_t CTRL2_0036; 576 uint32_t RSVD3[1]; 577 volatile uint32_t CTRL2_0040; 578 uint32_t RSVD4[1]; 579 volatile uint32_t CTRL2_0042; 580 volatile uint32_t CTRL2_0043; 581 volatile uint32_t CTRL2_0044; 582 volatile uint32_t CTRL2_0045; 583 volatile uint32_t CTRL2_0046; 584 volatile uint32_t CTRL2_0047; 585 volatile uint32_t CTRL2_0050; 586 volatile uint32_t CTRL2_0051; 587 volatile uint32_t CTRL2_0052; 588 volatile uint32_t CTRL2_0053; 589 volatile uint32_t CTRL2_0054; 590 volatile uint32_t CTRL2_0055; 591 volatile uint32_t CTRL2_0056; 592 volatile uint32_t CTRL2_0057; 593 volatile uint32_t CTRL2_0060; 594 volatile uint32_t CTRL2_0061; 595 volatile uint32_t CTRL2_0062; 596 volatile uint32_t CTRL2_0063; 597 volatile uint32_t CTRL2_0064; 598 volatile uint32_t CTRL2_0065; 599 volatile uint32_t CTRL2_0066; 600 volatile uint32_t CTRL2_0067; 601 volatile uint32_t CTRL2_0070; 602 volatile uint32_t CTRL2_0071; 603 volatile uint32_t CTRL2_0072; 604 volatile uint32_t CTRL2_0073; 605 volatile uint32_t CTRL2_0074; 606 volatile uint32_t CTRL2_0075; 607 volatile uint32_t CTRL2_0076; 608 uint32_t RSVD5[1]; 609 volatile uint32_t CTRL2_0100; 610 volatile uint32_t CTRL2_0101; 611 volatile uint32_t CTRL2_0102; 612 uint32_t RSVD6[1]; 613 volatile uint32_t CTRL2_0104; 614 volatile uint32_t CTRL2_0105; 615 volatile uint32_t CTRL2_0106; 616 volatile uint32_t CTRL2_0107; 617 uint32_t RSVD7[2]; 618 volatile uint32_t CTRL2_0112; 619 volatile uint32_t CTRL2_0113; 620 volatile uint32_t CTRL2_0114; 621 volatile uint32_t CTRL2_0115; 622 volatile uint32_t CTRL2_0116; 623 volatile uint32_t CTRL2_0117; 624 volatile uint32_t CTRL2_0120; 625 volatile uint32_t CTRL2_0121; 626 volatile uint32_t CTRL2_0122; 627 volatile uint32_t CTRL2_0123; 628 volatile uint32_t CTRL2_0124; 629 volatile uint32_t CTRL2_0125; 630 volatile uint32_t CTRL2_0126; 631 volatile uint32_t CTRL2_0127; 632 volatile uint32_t CTRL2_0130; 633 volatile uint32_t CTRL2_0131; 634 volatile uint32_t CTRL2_0132; 635 uint32_t RSVD9[5]; 636 volatile uint32_t CTRL2_0140; 637 volatile uint32_t CTRL2_0141; 638 volatile uint32_t CTRL2_0142; 639 volatile uint32_t CTRL2_0143; 640 volatile uint32_t CTRL2_0144; 641 volatile uint32_t CTRL2_0145; 642 volatile uint32_t CTRL2_0146; 643 volatile uint32_t CTRL2_0147; 644 volatile uint32_t CTRL2_0150; 645 volatile uint32_t CTRL2_0151; 646 volatile uint32_t CTRL2_0152; 647 volatile uint32_t CTRL2_0153; 648 volatile uint32_t CTRL2_0154; 649 volatile uint32_t CTRL2_0155; 650 volatile uint32_t CTRL2_0156; 651 volatile uint32_t CTRL2_0157; 652 uint32_t RSVD10[1]; 653 volatile uint32_t CTRL2_0161; 654 volatile uint32_t CTRL2_0162; 655 uint32_t RSVD11[2]; 656 volatile uint32_t CTRL2_0165; 657 uint32_t RSVD12[2]; 658 volatile uint32_t CTRL2_0170; 659 volatile uint32_t CTRL2_0171; 660 uint32_t RSVD13[3]; 661 volatile uint32_t CTRL2_0175; 662 uint32_t RSVD14[2]; 663 volatile uint32_t CTRL2_0200; 664 volatile uint32_t CTRL2_0201; 665 volatile uint32_t CTRL2_0202; 666 volatile uint32_t CTRL2_0203; 667 volatile uint32_t CTRL2_0204; 668 volatile uint32_t CTRL2_0205; 669 volatile uint32_t CTRL2_0206; 670 volatile uint32_t CTRL2_0207; 671 uint32_t RSVD15[9]; 672 volatile uint32_t CTRL2_0221; 673 volatile uint32_t CTRL2_0222; 674 volatile uint32_t CTRL2_0223; 675 volatile uint32_t CTRL2_0224; 676 uint32_t RSVD16[1]; 677 volatile uint32_t CTRL2_0226; 678 volatile uint32_t CTRL2_0227; 679 uint32_t RSVD17[8]; 680 volatile uint32_t CTRL2_0240; 681 volatile uint32_t CTRL2_0241; 682 volatile uint32_t CTRL2_0242; 683 volatile uint32_t CTRL2_0243; 684 volatile uint32_t CTRL2_0244; 685 volatile uint32_t CTRL2_0245; 686 volatile uint32_t CTRL2_0246; 687 uint32_t RSVD18[5]; 688 volatile uint32_t CTRL2_0254; 689 volatile uint32_t CTRL2_0255; 690 }; 691 692 /** @brief GPIO Parallel Input register. 32 GPIO pins per bank */ 693 struct gpio_parin_regs { 694 volatile uint32_t PARIN0; 695 volatile uint32_t PARIN1; 696 volatile uint32_t PARIN2; 697 volatile uint32_t PARIN3; 698 volatile uint32_t PARIN4; 699 volatile uint32_t PARIN5; 700 }; 701 702 /** @brief GPIO Parallel Output register. 32 GPIO pins per bank */ 703 struct gpio_parout_regs { 704 volatile uint32_t PAROUT0; 705 volatile uint32_t PAROUT1; 706 volatile uint32_t PAROUT2; 707 volatile uint32_t PAROUT3; 708 volatile uint32_t PAROUT4; 709 volatile uint32_t PAROUT5; 710 }; 711 712 /** @brief GPIO Lock registers. 32 GPIO pins per bank. Write-once bits */ 713 struct gpio_lock_regs { 714 volatile uint32_t LOCK5; 715 volatile uint32_t LOCK4; 716 volatile uint32_t LOCK3; 717 volatile uint32_t LOCK2; 718 volatile uint32_t LOCK1; 719 volatile uint32_t LOCK0; 720 }; 721 722 #ifdef __cplusplus 723 } 724 #endif 725 726 #endif /* #ifndef _MEC172X_GPIO_H */ 727
