1 /*
2 * Copyright (c) 2020 Nuvoton Technology Corporation.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #ifndef _NUVOTON_NPCX_REG_DEF_H
8 #define _NUVOTON_NPCX_REG_DEF_H
9
10 #include <stdint.h>
11
12 #include <zephyr/devicetree.h>
13 #include <zephyr/sys/__assert.h>
14 #include <zephyr/sys/util_macro.h>
15 #include <zephyr/toolchain.h>
16
17 /*
18 * NPCX register structure size/offset checking macro function to mitigate
19 * the risk of unexpected compiling results. All addresses of NPCX registers
20 * must meet the alignment requirement of cortex-m4.
21 * DO NOT use 'packed' attribute if module contains different length ie.
22 * 8/16/32 bits registers.
23 */
24 #define NPCX_REG_SIZE_CHECK(reg_def, size) \
25 BUILD_ASSERT(sizeof(struct reg_def) == size, \
26 "Failed in size check of register structure!")
27 #define NPCX_REG_OFFSET_CHECK(reg_def, member, offset) \
28 BUILD_ASSERT(offsetof(struct reg_def, member) == offset, \
29 "Failed in offset check of register structure member!")
30
31 /*
32 * NPCX register access checking via structure macro function to mitigate the
33 * risk of unexpected compiling results if module contains different length
34 * registers. For example, a word register access might break into two byte
35 * register accesses by adding 'packed' attribute.
36 *
37 * For example, add this macro for word register 'PRSC' of PWM module in its
38 * device init function for checking violation. Once it occurred, core will be
39 * stalled forever and easy to find out what happens.
40 */
41 #define NPCX_REG_WORD_ACCESS_CHECK(reg, val) { \
42 uint16_t placeholder = reg; \
43 reg = val; \
44 __ASSERT(reg == val, "16-bit reg access failed!"); \
45 reg = placeholder; \
46 }
47 #define NPCX_REG_DWORD_ACCESS_CHECK(reg, val) { \
48 uint32_t placeholder = reg; \
49 reg = val; \
50 __ASSERT(reg == val, "32-bit reg access failed!"); \
51 reg = placeholder; \
52 }
53 /*
54 * Core Domain Clock Generator (CDCG) device registers
55 */
56 struct cdcg_reg {
57 /* High Frequency Clock Generator (HFCG) registers */
58 /* 0x000: HFCG Control */
59 volatile uint8_t HFCGCTRL;
60 volatile uint8_t reserved1;
61 /* 0x002: HFCG M Low Byte Value */
62 volatile uint8_t HFCGML;
63 volatile uint8_t reserved2;
64 /* 0x004: HFCG M High Byte Value */
65 volatile uint8_t HFCGMH;
66 volatile uint8_t reserved3;
67 /* 0x006: HFCG N Value */
68 volatile uint8_t HFCGN;
69 volatile uint8_t reserved4;
70 /* 0x008: HFCG Prescaler */
71 volatile uint8_t HFCGP;
72 volatile uint8_t reserved5[7];
73 /* 0x010: HFCG Bus Clock Dividers */
74 volatile uint8_t HFCBCD;
75 volatile uint8_t reserved6;
76 /* 0x012: HFCG Bus Clock Dividers */
77 volatile uint8_t HFCBCD1;
78 volatile uint8_t reserved7;
79 /* 0x014: HFCG Bus Clock Dividers */
80 volatile uint8_t HFCBCD2;
81 volatile uint8_t reserved8[235];
82
83 /* Low Frequency Clock Generator (LFCG) registers */
84 /* 0x100: LFCG Control */
85 volatile uint8_t LFCGCTL;
86 volatile uint8_t reserved9;
87 /* 0x102: High-Frequency Reference Divisor I */
88 volatile uint16_t HFRDI;
89 /* 0x104: High-Frequency Reference Divisor F */
90 volatile uint16_t HFRDF;
91 /* 0x106: FRCLK Clock Divisor */
92 volatile uint16_t FRCDIV;
93 /* 0x108: Divisor Correction Value 1 */
94 volatile uint16_t DIVCOR1;
95 /* 0x10A: Divisor Correction Value 2 */
96 volatile uint16_t DIVCOR2;
97 volatile uint8_t reserved10[8];
98 /* 0x114: LFCG Control 2 */
99 volatile uint8_t LFCGCTL2;
100 volatile uint8_t reserved11;
101 };
102
103 /* CDCG register fields */
104 #define NPCX_HFCGCTRL_LOAD 0
105 #define NPCX_HFCGCTRL_LOCK 2
106 #define NPCX_HFCGCTRL_CLK_CHNG 7
107
108 #define NPCX_LFCGCTL2_XT_OSC_SL_EN 6
109
110 /*
111 * Power Management Controller (PMC) device registers
112 */
113 struct pmc_reg {
114 /* 0x000: Power Management Controller */
115 volatile uint8_t PMCSR;
116 volatile uint8_t reserved1[2];
117 /* 0x003: Enable in Sleep Control */
118 volatile uint8_t ENIDL_CTL;
119 /* 0x004: Disable in Idle Control */
120 volatile uint8_t DISIDL_CTL;
121 /* 0x005: Disable in Idle Control 1 */
122 volatile uint8_t DISIDL_CTL1;
123 volatile uint8_t reserved2[2];
124 /* 0x008 - 0D: Power-Down Control 1 - 6 */
125 volatile uint8_t PWDWN_CTL1[6];
126 volatile uint8_t reserved3[18];
127 /* 0x020 - 21: Power-Down Control 1 - 2 */
128 volatile uint8_t RAM_PD[2];
129 volatile uint8_t reserved4[2];
130 /* 0x024: Power-Down Control 7 */
131 volatile uint8_t PWDWN_CTL7[1];
132 };
133
134 /* PMC internal inline functions for multi-registers */
npcx_pwdwn_ctl_offset(uint32_t ctl_no)135 static inline uint32_t npcx_pwdwn_ctl_offset(uint32_t ctl_no)
136 {
137 if (ctl_no < 6) {
138 return 0x008 + ctl_no;
139 } else {
140 return 0x024 + ctl_no - 6;
141 }
142 }
143
144 /* Macro functions for PMC multi-registers */
145 #define NPCX_PWDWN_CTL(base, n) (*(volatile uint8_t *)(base + \
146 npcx_pwdwn_ctl_offset(n)))
147
148 /* PMC register fields */
149 #define NPCX_PMCSR_DI_INSTW 0
150 #define NPCX_PMCSR_DHF 1
151 #define NPCX_PMCSR_IDLE 2
152 #define NPCX_PMCSR_NWBI 3
153 #define NPCX_PMCSR_OHFC 6
154 #define NPCX_PMCSR_OLFC 7
155 #define NPCX_DISIDL_CTL_RAM_DID 5
156 #define NPCX_ENIDL_CTL_ADC_LFSL 7
157 #define NPCX_ENIDL_CTL_LP_WK_CTL 6
158 #define NPCX_ENIDL_CTL_PECI_ENI 2
159 #define NPCX_ENIDL_CTL_ADC_ACC_DIS 1
160
161 /*
162 * System Configuration (SCFG) device registers
163 */
164 struct scfg_reg {
165 /* 0x000: Device Control */
166 volatile uint8_t DEVCNT;
167 /* 0x001: Straps Status */
168 volatile uint8_t STRPST;
169 /* 0x002: Reset Control and Status */
170 volatile uint8_t RSTCTL;
171 volatile uint8_t reserved1[3];
172 /* 0x006: Device Control 4 */
173 volatile uint8_t DEV_CTL4;
174 volatile uint8_t reserved2[9];
175 /* 0x010 - 1F: Device Alternate Function 0 - F */
176 volatile uint8_t DEVALT0[16];
177 volatile uint8_t reserved3[6];
178 /* 0x026: Low-Voltage GPIO Pins Control 5 */
179 volatile uint8_t LV_GPIO_CTL5[1];
180 volatile uint8_t reserved4;
181 /* 0x028: Pull-Up/Pull-Down Enable 0 */
182 volatile uint8_t PUPD_EN0;
183 /* 0x029: Pull-Up/Pull-Down Enable 1 */
184 volatile uint8_t PUPD_EN1;
185 /* 0x02A - 2E: Low-Voltage GPIO Pins Control 0 - 4 */
186 volatile uint8_t LV_GPIO_CTL0[5];
187 };
188
189 /* SCFG internal inline functions for multi-registers */
npcx_devalt_offset(uint32_t alt_no)190 static inline uint32_t npcx_devalt_offset(uint32_t alt_no)
191 {
192 return 0x010 + alt_no;
193 }
194
npcx_devalt_lk_offset(uint32_t alt_lk_no)195 static inline uint32_t npcx_devalt_lk_offset(uint32_t alt_lk_no)
196 {
197 return 0x210 + alt_lk_no;
198 }
199
npcx_pupd_en_offset(uint32_t pupd_en_no)200 static inline uint32_t npcx_pupd_en_offset(uint32_t pupd_en_no)
201 {
202 return 0x28 + pupd_en_no;
203 }
204
npcx_lv_gpio_ctl_offset(uint32_t ctl_no)205 static inline uint32_t npcx_lv_gpio_ctl_offset(uint32_t ctl_no)
206 {
207 if (ctl_no < 5) {
208 return 0x02a + ctl_no;
209 } else {
210 return 0x026 + ctl_no - 5;
211 }
212 }
213
214 /* Macro functions for SCFG multi-registers */
215 #define NPCX_DEVALT(base, n) (*(volatile uint8_t *)(base + \
216 npcx_devalt_offset(n)))
217 #define NPCX_DEVALT_LK(base, n) (*(volatile uint8_t *)(base + \
218 npcx_devalt_lk_offset(n)))
219 #define NPCX_PUPD_EN(base, n) (*(volatile uint8_t *)(base + \
220 npcx_pupd_en_offset(n)))
221 #define NPCX_LV_GPIO_CTL(base, n) (*(volatile uint8_t *)(base + \
222 npcx_lv_gpio_ctl_offset(n)))
223
224 /* SCFG register fields */
225 #define NPCX_DEVCNT_F_SPI_TRIS 6
226 #define NPCX_DEVCNT_HIF_TYP_SEL_FIELD FIELD(2, 2)
227 #define NPCX_DEVCNT_JEN1_HEN 5
228 #define NPCX_DEVCNT_JEN0_HEN 4
229 #define NPCX_STRPST_TRIST 1
230 #define NPCX_STRPST_TEST 2
231 #define NPCX_STRPST_JEN1 4
232 #define NPCX_STRPST_JEN0 5
233 #define NPCX_STRPST_SPI_COMP 7
234 #define NPCX_RSTCTL_VCC1_RST_STS 0
235 #define NPCX_RSTCTL_DBGRST_STS 1
236 #define NPCX_RSTCTL_VCC1_RST_SCRATCH 3
237 #define NPCX_RSTCTL_LRESET_PLTRST_MODE 5
238 #define NPCX_RSTCTL_HIPRST_MODE 6
239 #define NPCX_DEV_CTL4_F_SPI_SLLK 2
240 #define NPCX_DEV_CTL4_SPI_SP_SEL 4
241 #define NPCX_DEV_CTL4_WP_IF 5
242 #define NPCX_DEV_CTL4_VCC1_RST_LK 6
243 #define NPCX_DEVPU0_I2C0_0_PUE 0
244 #define NPCX_DEVPU0_I2C0_1_PUE 1
245 #define NPCX_DEVPU0_I2C1_0_PUE 2
246 #define NPCX_DEVPU0_I2C2_0_PUE 4
247 #define NPCX_DEVPU0_I2C3_0_PUE 6
248 #define NPCX_DEVPU1_F_SPI_PUD_EN 7
249
250 /* Supported host interface type for HIF_TYP_SEL FILED in DEVCNT register. */
251 enum npcx_hif_type {
252 NPCX_HIF_TYPE_NONE,
253 NPCX_HIF_TYPE_LPC,
254 NPCX_HIF_TYPE_ESPI_SHI,
255 };
256
257 /*
258 * System Glue (GLUE) device registers
259 */
260 struct glue_reg {
261 volatile uint8_t reserved1[2];
262 /* 0x002: SMBus Start Bit Detection */
263 volatile uint8_t SMB_SBD;
264 /* 0x003: SMBus Event Enable */
265 volatile uint8_t SMB_EEN;
266 volatile uint8_t reserved2[12];
267 /* 0x010: Simple Debug Port Data 0 */
268 volatile uint8_t SDPD0;
269 volatile uint8_t reserved3;
270 /* 0x012: Simple Debug Port Data 1 */
271 volatile uint8_t SDPD1;
272 volatile uint8_t reserved4;
273 /* 0x014: Simple Debug Port Control and Status */
274 volatile uint8_t SDP_CTS;
275 volatile uint8_t reserved5[12];
276 /* 0x021: SMBus Bus Select */
277 volatile uint8_t SMB_SEL;
278 volatile uint8_t reserved6[5];
279 /* 0x027: PSL Control and Status */
280 volatile uint8_t PSL_CTS;
281 };
282
283 /* GLUE register fields */
284 /* PSL input detection mode is configured by bits 7:4 of PSL_CTS */
285 #define NPCX_PSL_CTS_MODE_BIT(bit) BIT(bit + 4)
286 /* PSL input assertion events are reported by bits 3:0 of PSL_CTS */
287 #define NPCX_PSL_CTS_EVENT_BIT(bit) BIT(bit)
288
289 /*
290 * Universal Asynchronous Receiver-Transmitter (UART) device registers
291 */
292 struct uart_reg {
293 /* 0x000: Transmit Data Buffer */
294 volatile uint8_t UTBUF;
295 volatile uint8_t reserved1;
296 /* 0x002: Receive Data Buffer */
297 volatile uint8_t URBUF;
298 volatile uint8_t reserved2;
299 /* 0x004: Interrupt Control */
300 volatile uint8_t UICTRL;
301 volatile uint8_t reserved3;
302 /* 0x006: Status */
303 volatile uint8_t USTAT;
304 volatile uint8_t reserved4;
305 /* 0x008: Frame Select */
306 volatile uint8_t UFRS;
307 volatile uint8_t reserved5;
308 /* 0x00A: Mode Select */
309 volatile uint8_t UMDSL;
310 volatile uint8_t reserved6;
311 /* 0x00C: Baud Rate Divisor */
312 volatile uint8_t UBAUD;
313 volatile uint8_t reserved7;
314 /* 0x00E: Baud Rate Prescaler */
315 volatile uint8_t UPSR;
316 volatile uint8_t reserved8[17];
317 /* 0x020: FIFO Mode Transmit Status */
318 volatile uint8_t UFTSTS;
319 volatile uint8_t reserved9;
320 /* 0x022: FIFO Mode Receive Status */
321 volatile uint8_t UFRSTS;
322 volatile uint8_t reserved10;
323 /* 0x024: FIFO Mode Transmit Control */
324 volatile uint8_t UFTCTL;
325 volatile uint8_t reserved11;
326 /* 0x026: FIFO Mode Receive Control */
327 volatile uint8_t UFRCTL;
328 };
329
330 /* UART register fields */
331 #define NPCX_UICTRL_TBE 0
332 #define NPCX_UICTRL_RBF 1
333 #define NPCX_UICTRL_ETI 5
334 #define NPCX_UICTRL_ERI 6
335 #define NPCX_UICTRL_EEI 7
336 #define NPCX_USTAT_PE 0
337 #define NPCX_USTAT_FE 1
338 #define NPCX_USTAT_DOE 2
339 #define NPCX_USTAT_ERR 3
340 #define NPCX_USTAT_BKD 4
341 #define NPCX_USTAT_RB9 5
342 #define NPCX_USTAT_XMIP 6
343 #define NPCX_UFRS_CHAR_FIELD FIELD(0, 2)
344 #define NPCX_UFRS_STP 2
345 #define NPCX_UFRS_XB9 3
346 #define NPCX_UFRS_PSEL_FIELD FIELD(4, 2)
347 #define NPCX_UFRS_PEN 6
348 #define NPCX_UMDSL_FIFO_MD 0
349 #define NPCX_UFTSTS_TEMPTY_LVL FIELD(0, 5)
350 #define NPCX_UFTSTS_TEMPTY_LVL_STS 5
351 #define NPCX_UFTSTS_TFIFO_EMPTY_STS 6
352 #define NPCX_UFTSTS_NXMIP 7
353 #define NPCX_UFRSTS_RFULL_LVL_STS 5
354 #define NPCX_UFRSTS_RFIFO_NEMPTY_STS 6
355 #define NPCX_UFRSTS_ERR 7
356 #define NPCX_UFTCTL_TEMPTY_LVL_SEL FIELD(0, 5)
357 #define NPCX_UFTCTL_TEMPTY_LVL_EN 5
358 #define NPCX_UFTCTL_TEMPTY_EN 6
359 #define NPCX_UFTCTL_NXMIP_EN 7
360 #define NPCX_UFRCTL_RFULL_LVL_SEL FIELD(0, 5)
361 #define NPCX_UFRCTL_RFULL_LVL_EN 5
362 #define NPCX_UFRCTL_RNEMPTY_EN 6
363 #define NPCX_UFRCTL_ERR_EN 7
364
365 /*
366 * Multi-Input Wake-Up Unit (MIWU) device registers
367 */
368
369 /* MIWU internal inline functions for multi-registers */
npcx_wkedg_offset(uint32_t group)370 static inline uint32_t npcx_wkedg_offset(uint32_t group)
371 {
372 if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX7)) {
373 return 0x000 + (group * 2ul) + (group < 5 ? 0 : 0x1e);
374 } else { /* NPCX9 and later series */
375 return 0x000 + group * 0x10UL;
376 }
377 }
378
npcx_wkaedg_offset(uint32_t group)379 static inline uint32_t npcx_wkaedg_offset(uint32_t group)
380 {
381 if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX7)) {
382 return 0x001 + (group * 2ul) + (group < 5 ? 0 : 0x1e);
383 } else { /* NPCX9 and later series */
384 return 0x001 + group * 0x10ul;
385 }
386 }
387
npcx_wkmod_offset(uint32_t group)388 static inline uint32_t npcx_wkmod_offset(uint32_t group)
389 {
390 if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX7)) {
391 return 0x070 + group;
392 } else { /* NPCX9 and later series */
393 return 0x002 + group * 0x10ul;
394 }
395 }
396
npcx_wkpnd_offset(uint32_t group)397 static inline uint32_t npcx_wkpnd_offset(uint32_t group)
398 {
399 if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX7)) {
400 return 0x00a + (group * 4ul) + (group < 5 ? 0 : 0x10);
401 } else { /* NPCX9 and later series */
402 return 0x003 + group * 0x10ul;
403 }
404 }
405
npcx_wkpcl_offset(uint32_t group)406 static inline uint32_t npcx_wkpcl_offset(uint32_t group)
407 {
408 if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX7)) {
409 return 0x00c + (group * 4ul) + (group < 5 ? 0 : 0x10);
410 } else { /* NPCX9 and later series */
411 return 0x004 + group * 0x10ul;
412 }
413 }
414
npcx_wken_offset(uint32_t group)415 static inline uint32_t npcx_wken_offset(uint32_t group)
416 {
417 if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX7)) {
418 return 0x01e + (group * 2ul) + (group < 5 ? 0 : 0x12);
419 } else { /* NPCX9 and later series */
420 return 0x005 + group * 0x10ul;
421 }
422 }
423
npcx_wkst_offset(uint32_t group)424 static inline uint32_t npcx_wkst_offset(uint32_t group)
425 {
426 /* NPCX9 and later series only */
427 return 0x006 + group * 0x10ul;
428 }
429
npcx_wkinen_offset(uint32_t group)430 static inline uint32_t npcx_wkinen_offset(uint32_t group)
431 {
432 if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX7)) {
433 return 0x01f + (group * 2ul) + (group < 5 ? 0 : 0x12);
434 } else { /* NPCX9 and later series */
435 return 0x007 + group * 0x10ul;
436 }
437 }
438
439 /* Macro functions for MIWU multi-registers */
440 #define NPCX_WKEDG(base, group) \
441 (*(volatile uint8_t *)(base + npcx_wkedg_offset(group)))
442 #define NPCX_WKAEDG(base, group) \
443 (*(volatile uint8_t *)(base + npcx_wkaedg_offset(group)))
444 #define NPCX_WKPND(base, group) \
445 (*(volatile uint8_t *)(base + npcx_wkpnd_offset(group)))
446 #define NPCX_WKPCL(base, group) \
447 (*(volatile uint8_t *)(base + npcx_wkpcl_offset(group)))
448 #define NPCX_WKEN(base, group) \
449 (*(volatile uint8_t *)(base + npcx_wken_offset(group)))
450 #define NPCX_WKINEN(base, group) \
451 (*(volatile uint8_t *)(base + npcx_wkinen_offset(group)))
452 #define NPCX_WKMOD(base, group) \
453 (*(volatile uint8_t *)(base + npcx_wkmod_offset(group)))
454
455 /*
456 * General-Purpose I/O (GPIO) device registers
457 */
458 struct gpio_reg {
459 /* 0x000: Port GPIOx Data Out */
460 volatile uint8_t PDOUT;
461 /* 0x001: Port GPIOx Data In */
462 volatile uint8_t PDIN;
463 /* 0x002: Port GPIOx Direction */
464 volatile uint8_t PDIR;
465 /* 0x003: Port GPIOx Pull-Up or Pull-Down Enable */
466 volatile uint8_t PPULL;
467 /* 0x004: Port GPIOx Pull-Up/Down Selection */
468 volatile uint8_t PPUD;
469 /* 0x005: Port GPIOx Drive Enable by VDD Present */
470 volatile uint8_t PENVDD;
471 /* 0x006: Port GPIOx Output Type */
472 volatile uint8_t PTYPE;
473 /* 0x007: Port GPIOx Lock Control */
474 volatile uint8_t PLOCK_CTL;
475 };
476
477 /*
478 * Pulse Width Modulator (PWM) device registers
479 */
480 struct pwm_reg {
481 /* 0x000: Clock Prescaler */
482 volatile uint16_t PRSC;
483 /* 0x002: Cycle Time */
484 volatile uint16_t CTR;
485 /* 0x004: PWM Control */
486 volatile uint8_t PWMCTL;
487 volatile uint8_t reserved1;
488 /* 0x006: Duty Cycle */
489 volatile uint16_t DCR;
490 volatile uint8_t reserved2[4];
491 /* 0x00C: PWM Control Extended */
492 volatile uint8_t PWMCTLEX;
493 volatile uint8_t reserved3;
494 };
495
496 /* PWM register fields */
497 #define NPCX_PWMCTL_INVP 0
498 #define NPCX_PWMCTL_CKSEL 1
499 #define NPCX_PWMCTL_HB_DC_CTL_FIELD FIELD(2, 2)
500 #define NPCX_PWMCTL_PWR 7
501 #define NPCX_PWMCTLEX_FCK_SEL_FIELD FIELD(4, 2)
502 #define NPCX_PWMCTLEX_OD_OUT 7
503
504 /*
505 * Analog-To-Digital Converter (ADC) device registers
506 */
507 struct adc_reg {
508 /* 0x000: ADC Status */
509 volatile uint16_t ADCSTS;
510 /* 0x002: ADC Configuration */
511 volatile uint16_t ADCCNF;
512 /* 0x004: ADC Timing Control */
513 volatile uint16_t ATCTL;
514 /* 0x006: ADC Single Channel Address */
515 volatile uint16_t ASCADD;
516 /* 0x008: ADC Scan Channels Select */
517 volatile uint16_t ADCCS;
518 volatile uint8_t reserved1[16];
519 /* 0x01A: Threshold Status */
520 volatile uint16_t THRCTS;
521 volatile uint8_t reserved2[4];
522 /* 0x020: Internal register 1 for ADC Speed */
523 volatile uint16_t ADCCNF2;
524 /* 0x022: Internal register 2 for ADC Speed */
525 volatile uint16_t GENDLY;
526 volatile uint8_t reserved3[2];
527 /* 0x026: Internal register 3 for ADC Speed */
528 volatile uint16_t MEAST;
529 };
530
npcx_chndat_offset(uint32_t ch)531 static inline uint32_t npcx_chndat_offset(uint32_t ch)
532 {
533 return 0x40 + ch * 2;
534 }
535
536 #define CHNDAT(base, ch) (*(volatile uint16_t *)((base) + npcx_chndat_offset(ch)))
537
538 /* ADC register fields */
539 #define NPCX_ATCTL_SCLKDIV_FIELD FIELD(0, 6)
540 #define NPCX_ATCTL_DLY_FIELD FIELD(8, 3)
541 #define NPCX_ASCADD_SADDR_FIELD FIELD(0, 5)
542 #define NPCX_ADCSTS_EOCEV 0
543 #define NPCX_ADCSTS_EOCCEV 1
544 #define NPCX_ADCCNF_ADCEN 0
545 #define NPCX_ADCCNF_ADCMD_FIELD FIELD(1, 2)
546 #define NPCX_ADCCNF_ADCRPTC 3
547 #define NPCX_ADCCNF_START 4
548 #define NPCX_ADCCNF_ADCTTE 5
549 #define NPCX_ADCCNF_INTECEN 6
550 #define NPCX_ADCCNF_INTECCEN 7
551 #define NPCX_ADCCNF_INTETCEN 8
552 #define NPCX_ADCCNF_INTOVFEN 9
553 #define NPCX_ADCCNF_STOP 11
554 #define NPCX_CHNDAT_CHDAT_FIELD FIELD(0, 10)
555 #define NPCX_CHNDAT_NEW 15
556 #define NPCX_THRCTL_THEN 15
557 #define NPCX_THRCTL_L_H 14
558 #define NPCX_THRCTL_CHNSEL FIELD(10, 4)
559 #define NPCX_THRCTL_THRVAL FIELD(0, 10)
560 #define NPCX_THRCTS_ADC_WKEN 15
561 #define NPCX_THRCTS_THR3_IEN 10
562 #define NPCX_THRCTS_THR2_IEN 9
563 #define NPCX_THRCTS_THR1_IEN 8
564 #define NPCX_THRCTS_ADC_EVENT 7
565 #define NPCX_THRCTS_THR3_STS 2
566 #define NPCX_THRCTS_THR2_STS 1
567 #define NPCX_THRCTS_THR1_STS 0
568 #define NPCX_THR_DCTL_THRD_EN 15
569 #define NPCX_THR_DCTL_THR_DVAL FIELD(0, 10)
570
571 /*
572 * Timer Watchdog (TWD) device registers
573 */
574 struct twd_reg {
575 /* 0x000: Timer and Watchdog Configuration */
576 volatile uint8_t TWCFG;
577 volatile uint8_t reserved1;
578 /* 0x002: Timer and Watchdog Clock Prescaler */
579 volatile uint8_t TWCP;
580 volatile uint8_t reserved2;
581 /* 0x004: TWD Timer 0 */
582 volatile uint16_t TWDT0;
583 /* 0x006: TWDT0 Control and Status */
584 volatile uint8_t T0CSR;
585 volatile uint8_t reserved3;
586 /* 0x008: Watchdog Count */
587 volatile uint8_t WDCNT;
588 volatile uint8_t reserved4;
589 /* 0x00A: Watchdog Service Data Match */
590 volatile uint8_t WDSDM;
591 volatile uint8_t reserved5;
592 /* 0x00C: TWD Timer 0 Counter */
593 volatile uint16_t TWMT0;
594 /* 0x00E: Watchdog Counter */
595 volatile uint8_t TWMWD;
596 volatile uint8_t reserved6;
597 /* 0x010: Watchdog Clock Prescaler */
598 volatile uint8_t WDCP;
599 volatile uint8_t reserved7;
600 };
601
602 /* TWD register fields */
603 #define NPCX_TWCFG_LTWCFG 0
604 #define NPCX_TWCFG_LTWCP 1
605 #define NPCX_TWCFG_LTWDT0 2
606 #define NPCX_TWCFG_LWDCNT 3
607 #define NPCX_TWCFG_WDCT0I 4
608 #define NPCX_TWCFG_WDSDME 5
609 #define NPCX_T0CSR_RST 0
610 #define NPCX_T0CSR_TC 1
611 #define NPCX_T0CSR_WDLTD 3
612 #define NPCX_T0CSR_WDRST_STS 4
613 #define NPCX_T0CSR_WD_RUN 5
614 #define NPCX_T0CSR_TESDIS 7
615
616 /*
617 * Enhanced Serial Peripheral Interface (eSPI) device registers
618 */
619 struct espi_reg {
620 /* 0x000: eSPI Identification */
621 volatile uint32_t ESPIID;
622 /* 0x004: eSPI Configuration */
623 volatile uint32_t ESPICFG;
624 /* 0x008: eSPI Status */
625 volatile uint32_t ESPISTS;
626 /* 0x00C: eSPI Interrupt Enable */
627 volatile uint32_t ESPIIE;
628 /* 0x010: eSPI Wake-Up Enable */
629 volatile uint32_t ESPIWE;
630 /* 0x014: Virtual Wire Register Index */
631 volatile uint32_t VWREGIDX;
632 /* 0x018: Virtual Wire Register Data */
633 volatile uint32_t VWREGDATA;
634 /* 0x01C: OOB Receive Buffer Read Head */
635 volatile uint32_t OOBRXRDHEAD;
636 /* 0x020: OOB Transmit Buffer Write Head */
637 volatile uint32_t OOBTXWRHEAD;
638 /* 0x024: OOB Channel Control */
639 volatile uint32_t OOBCTL;
640 /* 0x028: Flash Receive Buffer Read Head */
641 volatile uint32_t FLASHRXRDHEAD;
642 /* 0x02C: Flash Transmit Buffer Write Head */
643 volatile uint32_t FLASHTXWRHEAD;
644 volatile uint32_t reserved1;
645 /* 0x034: Flash Channel Configuration */
646 volatile uint32_t FLASHCFG;
647 /* 0x038: Flash Channel Control */
648 volatile uint32_t FLASHCTL;
649 /* 0x03C: eSPI Error Status */
650 volatile uint32_t ESPIERR;
651 /* 0x040: Peripheral Bus Master Receive Buffer Read Head */
652 volatile uint32_t PBMRXRDHEAD;
653 /* 0x044: Peripheral Bus Master Transmit Buffer Write Head */
654 volatile uint32_t PBMTXWRHEAD;
655 /* 0x048: Peripheral Channel Configuration */
656 volatile uint32_t PERCFG;
657 /* 0x04C: Peripheral Channel Control */
658 volatile uint32_t PERCTL;
659 /* 0x050: Status Image Register */
660 volatile uint16_t STATUS_IMG;
661 volatile uint16_t reserved2[79];
662 /* 0x0F0: NPCX specific eSPI Register1 */
663 volatile uint8_t NPCX_ONLY_ESPI_REG1;
664 /* 0x0F1: NPCX specific eSPI Register2 */
665 volatile uint8_t NPCX_ONLY_ESPI_REG2;
666 volatile uint16_t reserved3[7];
667 /* 0x100 - 127: Virtual Wire Event Slave-to-Master 0 - 9 */
668 volatile uint32_t VWEVSM[10];
669 volatile uint32_t reserved4[6];
670 /* 0x140 - 16F: Virtual Wire Event Master-to-Slave 0 - 11 */
671 volatile uint32_t VWEVMS[12];
672 volatile uint32_t reserved5[4];
673 /* 0x180 - 1BF: Virtual Wire GPIO Event Master-to-Slave 0 - 15 */
674 volatile uint32_t VWGPSM[16];
675 volatile uint32_t reserved6[79];
676 /* 0x2FC: Virtual Wire Channel Control */
677 volatile uint32_t VWCTL;
678 /* 0x300 - 34F: OOB Receive Buffer 0 - 19 */
679 volatile uint32_t OOBRXBUF[20];
680 volatile uint32_t reserved7[12];
681 /* 0x380 - 3CF: OOB Transmit Buffer 0-19 */
682 volatile uint32_t OOBTXBUF[20];
683 volatile uint32_t reserved8[11];
684 /* 0x3FC: OOB Channel Control used in 'direct' mode */
685 volatile uint32_t OOBCTL_DIRECT;
686 /* 0x400 - 443: Flash Receive Buffer 0-16 */
687 volatile uint32_t FLASHRXBUF[17];
688 volatile uint32_t reserved9[15];
689 /* 0x480 - 497: Flash Transmit Buffer 0-5 */
690 volatile uint32_t FLASHTXBUF[6];
691 volatile uint32_t reserved10[25];
692 /* 0x4FC: Flash Channel Control used in 'direct' mode */
693 volatile uint32_t FLASHCTL_DIRECT;
694 };
695
696 /* eSPI register fields */
697 #define NPCX_ESPICFG_PCHANEN 0
698 #define NPCX_ESPICFG_VWCHANEN 1
699 #define NPCX_ESPICFG_OOBCHANEN 2
700 #define NPCX_ESPICFG_FLASHCHANEN 3
701 #define NPCX_ESPICFG_HPCHANEN 4
702 #define NPCX_ESPICFG_HVWCHANEN 5
703 #define NPCX_ESPICFG_HOOBCHANEN 6
704 #define NPCX_ESPICFG_HFLASHCHANEN 7
705 #define NPCX_ESPICFG_CHANS_FIELD FIELD(0, 4)
706 #define NPCX_ESPICFG_HCHANS_FIELD FIELD(4, 4)
707 #define NPCX_ESPICFG_IOMODE_FIELD FIELD(8, 2)
708 #define NPCX_ESPICFG_MAXFREQ_FIELD FIELD(10, 3)
709 #define NPCX_ESPICFG_PCCHN_SUPP 24
710 #define NPCX_ESPICFG_VWCHN_SUPP 25
711 #define NPCX_ESPICFG_OOBCHN_SUPP 26
712 #define NPCX_ESPICFG_FLASHCHN_SUPP 27
713 #define NPCX_ESPIIE_IBRSTIE 0
714 #define NPCX_ESPIIE_CFGUPDIE 1
715 #define NPCX_ESPIIE_BERRIE 2
716 #define NPCX_ESPIIE_OOBRXIE 3
717 #define NPCX_ESPIIE_FLASHRXIE 4
718 #define NPCX_ESPIIE_SFLASHRDIE 5
719 #define NPCX_ESPIIE_PERACCIE 6
720 #define NPCX_ESPIIE_DFRDIE 7
721 #define NPCX_ESPIIE_VWUPDIE 8
722 #define NPCX_ESPIIE_ESPIRSTIE 9
723 #define NPCX_ESPIIE_PLTRSTIE 10
724 #define NPCX_ESPIIE_AMERRIE 15
725 #define NPCX_ESPIIE_AMDONEIE 16
726 #define NPCX_ESPIIE_BMTXDONEIE 19
727 #define NPCX_ESPIIE_PBMRXIE 20
728 #define NPCX_ESPIIE_PMSGRXIE 21
729 #define NPCX_ESPIIE_BMBURSTERRIE 22
730 #define NPCX_ESPIIE_BMBURSTDONEIE 23
731 #define NPCX_ESPIWE_IBRSTWE 0
732 #define NPCX_ESPIWE_CFGUPDWE 1
733 #define NPCX_ESPIWE_BERRWE 2
734 #define NPCX_ESPIWE_OOBRXWE 3
735 #define NPCX_ESPIWE_FLASHRXWE 4
736 #define NPCX_ESPIWE_PERACCWE 6
737 #define NPCX_ESPIWE_DFRDWE 7
738 #define NPCX_ESPIWE_VWUPDWE 8
739 #define NPCX_ESPIWE_ESPIRSTWE 9
740 #define NPCX_ESPIWE_PBMRXWE 20
741 #define NPCX_ESPIWE_PMSGRXWE 21
742 #define NPCX_ESPISTS_IBRST 0
743 #define NPCX_ESPISTS_CFGUPD 1
744 #define NPCX_ESPISTS_BERR 2
745 #define NPCX_ESPISTS_OOBRX 3
746 #define NPCX_ESPISTS_FLASHRX 4
747 #define NPCX_ESPISTS_PERACC 6
748 #define NPCX_ESPISTS_DFRD 7
749 #define NPCX_ESPISTS_VWUPD 8
750 #define NPCX_ESPISTS_ESPIRST 9
751 #define NPCX_ESPISTS_PLTRST 10
752 #define NPCX_ESPISTS_AMERR 15
753 #define NPCX_ESPISTS_AMDONE 16
754 #define NPCX_ESPISTS_VWUPDW 17
755 #define NPCX_ESPISTS_BMTXDONE 19
756 #define NPCX_ESPISTS_PBMRX 20
757 #define NPCX_ESPISTS_PMSGRX 21
758 #define NPCX_ESPISTS_BMBURSTERR 22
759 #define NPCX_ESPISTS_BMBURSTDONE 23
760 #define NPCX_ESPISTS_ESPIRST_LVL 24
761 #define NPCX_VWEVMS_WIRE FIELD(0, 4)
762 #define NPCX_VWEVMS_VALID FIELD(4, 4)
763 #define NPCX_VWEVMS_IE 18
764 #define NPCX_VWEVMS_WE 20
765 #define NPCX_VWEVSM_WIRE FIELD(0, 4)
766 #define NPCX_VWEVSM_VALID FIELD(4, 4)
767 #define NPCX_VWEVSM_BIT_VALID(n) (4+n)
768 #define NPCX_VWEVSM_HW_WIRE FIELD(24, 4)
769 #define NPCX_VWGPSM_INDEX_EN 15
770 #define NPCX_OOBCTL_OOB_FREE 0
771 #define NPCX_OOBCTL_OOB_AVAIL 1
772 #define NPCX_OOBCTL_RSTBUFHEADS 2
773 #define NPCX_OOBCTL_OOBPLSIZE FIELD(10, 3)
774 #define NPCX_FLASHCFG_FLASHBLERSSIZE FIELD(7, 3)
775 #define NPCX_FLASHCFG_FLASHPLSIZE FIELD(10, 3)
776 #define NPCX_FLASHCFG_FLASHREQSIZE FIELD(13, 3)
777 #define NPCX_FLASHCTL_FLASH_NP_FREE 0
778 #define NPCX_FLASHCTL_FLASH_TX_AVAIL 1
779 #define NPCX_FLASHCTL_STRPHDR 2
780 #define NPCX_FLASHCTL_DMATHRESH FIELD(3, 2)
781 #define NPCX_FLASHCTL_AMTSIZE FIELD(5, 8)
782 #define NPCX_FLASHCTL_RSTBUFHEADS 13
783 #define NPCX_FLASHCTL_CRCEN 14
784 #define NPCX_FLASHCTL_CHKSUMSEL 15
785 #define NPCX_FLASHCTL_AMTEN 16
786
787 #define NPCX_ONLY_ESPI_REG1_UNLOCK_REG2 0x55
788 #define NPCX_ONLY_ESPI_REG1_LOCK_REG2 0
789 #define NPCX_ONLY_ESPI_REG2_TRANS_END_CONFIG 4
790 /*
791 * Mobile System Wake-Up Control (MSWC) device registers
792 */
793 struct mswc_reg {
794 /* 0x000: MSWC Control Status 1 */
795 volatile uint8_t MSWCTL1;
796 volatile uint8_t reserved1;
797 /* 0x002: MSWC Control Status 2 */
798 volatile uint8_t MSWCTL2;
799 volatile uint8_t reserved2[5];
800 /* 0x008: Host Configuration Base Address Low */
801 volatile uint8_t HCBAL;
802 volatile uint8_t reserved3;
803 /* 0x00A: Host Configuration Base Address High */
804 volatile uint8_t HCBAH;
805 volatile uint8_t reserved4;
806 /* 0X00C: MSWC INTERRUPT ENABLE 2 */
807 volatile uint8_t MSIEN2;
808 volatile uint8_t reserved5;
809 /* 0x00E: MSWC Host Event Status 0 */
810 volatile uint8_t MSHES0;
811 volatile uint8_t reserved6;
812 /* 0x010: MSWC Host Event Interrupt Enable */
813 volatile uint8_t MSHEIE0;
814 volatile uint8_t reserved7;
815 /* 0x012: Host Control */
816 volatile uint8_t HOST_CTL;
817 volatile uint8_t reserved8;
818 /* 0x014: SMI Pulse Length */
819 volatile uint8_t SMIP_LEN;
820 volatile uint8_t reserved9;
821 /* 0x016: SCI Pulse Length */
822 volatile uint8_t SCIP_LEN;
823 volatile uint8_t reserved10[5];
824 /* 0x01C: SRID Core Access */
825 volatile uint8_t SRID_CR;
826 volatile uint8_t reserved11[3];
827 /* 0x020: SID Core Access */
828 volatile uint8_t SID_CR;
829 volatile uint8_t reserved12;
830 /* 0x022: DEVICE_ID Core Access */
831 volatile uint8_t DEVICE_ID_CR;
832 volatile uint8_t reserved13[5];
833 /* 0x028: Chip Revision Core Access */
834 volatile uint8_t CHPREV_CR;
835 volatile uint8_t reserved14[5];
836 /* 0x02E: Virtual Wire Sleep States */
837 volatile uint8_t VW_SLPST1;
838 volatile uint8_t reserved15;
839 };
840
841 /* MSWC register fields */
842 #define NPCX_MSWCTL1_HRSTOB 0
843 #define NPCS_MSWCTL1_HWPRON 1
844 #define NPCX_MSWCTL1_PLTRST_ACT 2
845 #define NPCX_MSWCTL1_VHCFGA 3
846 #define NPCX_MSWCTL1_HCFGLK 4
847 #define NPCX_MSWCTL1_PWROFFB 6
848 #define NPCX_MSWCTL1_A20MB 7
849
850 /*
851 * Shared Memory (SHM) device registers
852 */
853 struct shm_reg {
854 /* 0x000: Shared Memory Core Status */
855 volatile uint8_t SMC_STS;
856 /* 0x001: Shared Memory Core Control */
857 volatile uint8_t SMC_CTL;
858 /* 0x002: Shared Memory Host Control */
859 volatile uint8_t SHM_CTL;
860 volatile uint8_t reserved1[2];
861 /* 0x005: Indirect Memory Access Window Size */
862 volatile uint8_t IMA_WIN_SIZE;
863 volatile uint8_t reserved2;
864 /* 0x007: Shared Access Windows Size */
865 volatile uint8_t WIN_SIZE;
866 /* 0x008: Shared Access Window 1, Semaphore */
867 volatile uint8_t SHAW1_SEM;
868 /* 0x009: Shared Access Window 2, Semaphore */
869 volatile uint8_t SHAW2_SEM;
870 volatile uint8_t reserved3;
871 /* 0x00B: Indirect Memory Access, Semaphore */
872 volatile uint8_t IMA_SEM;
873 volatile uint8_t reserved4[2];
874 /* 0x00E: Shared Memory Configuration */
875 volatile uint16_t SHCFG;
876 /* 0x010: Shared Access Window 1 Write Protect */
877 volatile uint8_t WIN1_WR_PROT;
878 /* 0x011: Shared Access Window 1 Read Protect */
879 volatile uint8_t WIN1_RD_PROT;
880 /* 0x012: Shared Access Window 2 Write Protect */
881 volatile uint8_t WIN2_WR_PROT;
882 /* 0x013: Shared Access Window 2 Read Protect */
883 volatile uint8_t WIN2_RD_PROT;
884 volatile uint8_t reserved5[2];
885 /* 0x016: Indirect Memory Access Write Protect */
886 volatile uint8_t IMA_WR_PROT;
887 /* 0x017: Indirect Memory Access Read Protect */
888 volatile uint8_t IMA_RD_PROT;
889 volatile uint8_t reserved6[8];
890 /* 0x020: Shared Access Window 1 Base */
891 volatile uint32_t WIN_BASE1;
892 /* 0x024: Shared Access Window 2 Base */
893 volatile uint32_t WIN_BASE2;
894 volatile uint32_t reserved7;
895 /* 0x02C: Indirect Memory Access Base */
896 volatile uint32_t IMA_BASE;
897 volatile uint8_t reserved8[10];
898 /* 0x03A: Reset Configuration */
899 volatile uint8_t RST_CFG;
900 volatile uint8_t reserved9[5];
901 /* 0x040: Debug Port 80 Buffered Data */
902 volatile uint16_t DP80BUF;
903 /* 0x042: Debug Port 80 Status */
904 volatile uint8_t DP80STS;
905 volatile uint8_t reserved10;
906 /* 0x044: Debug Port 80 Control */
907 volatile uint8_t DP80CTL;
908 volatile uint8_t reserved11[3];
909 /* 0x048: Host_Offset in Windows 1, 2 Status */
910 volatile uint8_t HOFS_STS;
911 /* 0x049: Host_Offset in Windows 1, 2 Control */
912 volatile uint8_t HOFS_CTL;
913 /* 0x04A: Core_Offset in Window 2 Address */
914 volatile uint16_t COFS2;
915 /* 0x04C: Core_Offset in Window 1 Address */
916 volatile uint16_t COFS1;
917 volatile uint16_t reserved12;
918 };
919
920 /* SHM register fields */
921 #define NPCX_SMC_STS_HRERR 0
922 #define NPCX_SMC_STS_HWERR 1
923 #define NPCX_SMC_STS_HSEM1W 4
924 #define NPCX_SMC_STS_HSEM2W 5
925 #define NPCX_SMC_STS_SHM_ACC 6
926 #define NPCX_SMC_CTL_HERR_IE 2
927 #define NPCX_SMC_CTL_HSEM1_IE 3
928 #define NPCX_SMC_CTL_HSEM2_IE 4
929 #define NPCX_SMC_CTL_ACC_IE 5
930 #define NPCX_SMC_CTL_PREF_EN 6
931 #define NPCX_SMC_CTL_HOSTWAIT 7
932 #define NPCX_FLASH_SIZE_STALL_HOST 6
933 #define NPCX_FLASH_SIZE_RD_BURST 7
934 #define NPCX_WIN_SIZE_RWIN1_SIZE_FIELD FIELD(0, 4)
935 #define NPCX_WIN_SIZE_RWIN2_SIZE_FIELD FIELD(4, 4)
936 #define NPCX_WIN_PROT_RW1L_RP 0
937 #define NPCX_WIN_PROT_RW1L_WP 1
938 #define NPCX_WIN_PROT_RW1H_RP 2
939 #define NPCX_WIN_PROT_RW1H_WP 3
940 #define NPCX_WIN_PROT_RW2L_RP 4
941 #define NPCX_WIN_PROT_RW2L_WP 5
942 #define NPCX_WIN_PROT_RW2H_RP 6
943 #define NPCX_WIN_PROT_RW2H_WP 7
944 #define NPCX_PWIN_SIZEI_RPROT 13
945 #define NPCX_PWIN_SIZEI_WPROT 14
946 #define NPCX_CSEM2 6
947 #define NPCX_CSEM3 7
948 #define NPCX_DP80STS_FWR 5
949 #define NPCX_DP80STS_FNE 6
950 #define NPCX_DP80STS_FOR 7
951 #define NPCX_DP80CTL_DP80EN 0
952 #define NPCX_DP80CTL_SYNCEN 1
953 #define NPCX_DP80CTL_ADV 2
954 #define NPCX_DP80CTL_RAA 3
955 #define NPCX_DP80CTL_RFIFO 4
956 #define NPCX_DP80CTL_CIEN 5
957 #define NPCX_DP80CTL_DP80_HF_CFG 7
958 #define NPCX_DP80BUF_OFFS_FIELD FIELD(8, 3)
959
960 /*
961 * Keyboard and Mouse Controller (KBC) device registers
962 */
963 struct kbc_reg {
964 /* 0x000h: Host Interface Control */
965 volatile uint8_t HICTRL;
966 volatile uint8_t reserved1;
967 /* 0x002h: Host Interface IRQ Control */
968 volatile uint8_t HIIRQC;
969 volatile uint8_t reserved2;
970 /* 0x004h: Host Interface Keyboard/Mouse Status */
971 volatile uint8_t HIKMST;
972 volatile uint8_t reserved3;
973 /* 0x006h: Host Interface Keyboard Data Out Buffer */
974 volatile uint8_t HIKDO;
975 volatile uint8_t reserved4;
976 /* 0x008h: Host Interface Mouse Data Out Buffer */
977 volatile uint8_t HIMDO;
978 volatile uint8_t reserved5;
979 /* 0x00Ah: Host Interface Keyboard/Mouse Data In Buffer */
980 volatile uint8_t HIKMDI;
981 /* 0x00Bh: Host Interface Keyboard/Mouse Shadow Data In Buffer */
982 volatile uint8_t SHIKMDI;
983 };
984
985 /* KBC register field */
986 #define NPCX_HICTRL_OBFKIE 0
987 #define NPCX_HICTRL_OBFMIE 1
988 #define NPCX_HICTRL_OBECIE 2
989 #define NPCX_HICTRL_IBFCIE 3
990 #define NPCX_HICTRL_PMIHIE 4
991 #define NPCX_HICTRL_PMIOCIE 5
992 #define NPCX_HICTRL_PMICIE 6
993 #define NPCX_HICTRL_FW_OBF 7
994 #define NPCX_HIKMST_OBF 0
995 #define NPCX_HIKMST_IBF 1
996 #define NPCX_HIKMST_F0 2
997 #define NPCX_HIKMST_A2 3
998 #define NPCX_HIKMST_ST0 4
999 #define NPCX_HIKMST_ST1 5
1000 #define NPCX_HIKMST_ST2 6
1001 #define NPCX_HIKMST_ST3 7
1002
1003 /*
1004 * Power Management Channel (PMCH) device registers
1005 */
1006
1007 struct pmch_reg {
1008 /* 0x000: Host Interface PM Status */
1009 volatile uint8_t HIPMST;
1010 volatile uint8_t reserved1;
1011 /* 0x002: Host Interface PM Data Out Buffer */
1012 volatile uint8_t HIPMDO;
1013 volatile uint8_t reserved2;
1014 /* 0x004: Host Interface PM Data In Buffer */
1015 volatile uint8_t HIPMDI;
1016 /* 0x005: Host Interface PM Shadow Data In Buffer */
1017 volatile uint8_t SHIPMDI;
1018 /* 0x006: Host Interface PM Data Out Buffer with SCI */
1019 volatile uint8_t HIPMDOC;
1020 volatile uint8_t reserved3;
1021 /* 0x008: Host Interface PM Data Out Buffer with SMI */
1022 volatile uint8_t HIPMDOM;
1023 volatile uint8_t reserved4;
1024 /* 0x00A: Host Interface PM Data In Buffer with SCI */
1025 volatile uint8_t HIPMDIC;
1026 volatile uint8_t reserved5;
1027 /* 0x00C: Host Interface PM Control */
1028 volatile uint8_t HIPMCTL;
1029 /* 0x00D: Host Interface PM Control 2 */
1030 volatile uint8_t HIPMCTL2;
1031 /* 0x00E: Host Interface PM Interrupt Control */
1032 volatile uint8_t HIPMIC;
1033 volatile uint8_t reserved6;
1034 /* 0x010: Host Interface PM Interrupt Enable */
1035 volatile uint8_t HIPMIE;
1036 volatile uint8_t reserved7;
1037 };
1038
1039 /* PMCH register field */
1040 #define NPCX_HIPMIE_SCIE 1
1041 #define NPCX_HIPMIE_SMIE 2
1042 #define NPCX_HIPMCTL_IBFIE 0
1043 #define NPCX_HIPMCTL_OBEIE 1
1044 #define NPCX_HIPMCTL_SCIPOL 6
1045 #define NPCX_HIPMST_OBF 0
1046 #define NPCX_HIPMST_IBF 1
1047 #define NPCX_HIPMST_F0 2
1048 #define NPCX_HIPMST_CMD 3
1049 #define NPCX_HIPMST_ST0 4
1050 #define NPCX_HIPMST_ST1 5
1051 #define NPCX_HIPMST_ST2 6
1052 #define NPCX_HIPMIC_SMIB 1
1053 #define NPCX_HIPMIC_SCIB 2
1054 #define NPCX_HIPMIC_SMIPOL 6
1055
1056 /*
1057 * Core Access to Host (C2H) device registers
1058 */
1059 struct c2h_reg {
1060 /* 0x000: Indirect Host I/O Address */
1061 volatile uint16_t IHIOA;
1062 /* 0x002: Indirect Host Data */
1063 volatile uint8_t IHD;
1064 volatile uint8_t reserved1;
1065 /* 0x004: Lock Host Access */
1066 volatile uint16_t LKSIOHA;
1067 /* 0x006: Access Lock Violation */
1068 volatile uint16_t SIOLV;
1069 /* 0x008: Core-to-Host Modules Access Enable */
1070 volatile uint16_t CRSMAE;
1071 /* 0x00A: Module Control */
1072 volatile uint8_t SIBCTRL;
1073 volatile uint8_t reserved3;
1074 };
1075
1076 /* C2H register fields */
1077 #define NPCX_LKSIOHA_LKCFG 0
1078 #define NPCX_LKSIOHA_LKSPHA 2
1079 #define NPCX_LKSIOHA_LKHIKBD 11
1080 #define NPCX_CRSMAE_CFGAE 0
1081 #define NPCX_CRSMAE_HIKBDAE 11
1082 #define NPCX_SIOLV_SPLV 2
1083 #define NPCX_SIBCTRL_CSAE 0
1084 #define NPCX_SIBCTRL_CSRD 1
1085 #define NPCX_SIBCTRL_CSWR 2
1086
1087 /*
1088 * SMBUS (SMB) device registers
1089 */
1090 struct smb_reg {
1091 /* 0x000: SMB Serial Data */
1092 volatile uint8_t SMBSDA;
1093 volatile uint8_t reserved1;
1094 /* 0x002: SMB Status */
1095 volatile uint8_t SMBST;
1096 volatile uint8_t reserved2;
1097 /* 0x004: SMB Control Status */
1098 volatile uint8_t SMBCST;
1099 volatile uint8_t reserved3;
1100 /* 0x006: SMB Control 1 */
1101 volatile uint8_t SMBCTL1;
1102 volatile uint8_t reserved4;
1103 /* 0x008: SMB Own Address */
1104 volatile uint8_t SMBADDR1;
1105 volatile uint8_t reserved5;
1106 /* 0x00A: SMB Control 2 */
1107 volatile uint8_t SMBCTL2;
1108 volatile uint8_t reserved6;
1109 /* 0x00C: SMB Own Address */
1110 volatile uint8_t SMBADDR2;
1111 volatile uint8_t reserved7;
1112 /* 0x00E: SMB Control 3 */
1113 volatile uint8_t SMBCTL3;
1114 /* 0x00F: SMB Bus Timeout */
1115 volatile uint8_t SMBT_OUT;
1116 union {
1117 /* Bank 0 */
1118 struct {
1119 /* 0x010: SMB Own Address 3 */
1120 volatile uint8_t SMBADDR3;
1121 /* 0x011: SMB Own Address 7 */
1122 volatile uint8_t SMBADDR7;
1123 /* 0x012: SMB Own Address 4 */
1124 volatile uint8_t SMBADDR4;
1125 /* 0x013: SMB Own Address 8 */
1126 volatile uint8_t SMBADDR8;
1127 /* 0x014: SMB Own Address 5 */
1128 volatile uint8_t SMBADDR5;
1129 volatile uint8_t reserved8;
1130 /* 0x016: SMB Own Address 6 */
1131 volatile uint8_t SMBADDR6;
1132 volatile uint8_t reserved9;
1133 /* 0x018: SMB Control Status 2 */
1134 volatile uint8_t SMBCST2;
1135 /* 0x019: SMB Control Status 3 */
1136 volatile uint8_t SMBCST3;
1137 /* 0x01A: SMB Control 4 */
1138 volatile uint8_t SMBCTL4;
1139 volatile uint8_t reserved10;
1140 /* 0x01C: SMB SCL Low Time */
1141 volatile uint8_t SMBSCLLT;
1142 /* 0x01D: SMB FIFO Control */
1143 volatile uint8_t SMBFIF_CTL;
1144 /* 0x01E: SMB SCL High Time */
1145 volatile uint8_t SMBSCLHT;
1146 volatile uint8_t reserved11;
1147 };
1148 /* Bank 1 */
1149 struct {
1150 /* 0x010: SMB FIFO Control */
1151 volatile uint8_t SMBFIF_CTS;
1152 volatile uint8_t reserved12;
1153 /* 0x012: SMB Tx-FIFO Control */
1154 volatile uint8_t SMBTXF_CTL;
1155 volatile uint8_t reserved13;
1156 /* 0x014: SMB Bus Timeout */
1157 volatile uint8_t SMB_T_OUT;
1158 volatile uint8_t reserved14[3];
1159 /* 0x018: SMB Control Status 2 (FIFO) */
1160 volatile uint8_t SMBCST2_FIFO;
1161 /* 0x019: SMB Control Status 3 (FIFO) */
1162 volatile uint8_t SMBCST3_FIFO;
1163 /* 0x01A: SMB Tx-FIFO Status */
1164 volatile uint8_t SMBTXF_STS;
1165 volatile uint8_t reserved15;
1166 /* 0x01C: SMB Rx-FIFO Status */
1167 volatile uint8_t SMBRXF_STS;
1168 volatile uint8_t reserved16;
1169 /* 0x01E: SMB Rx-FIFO Control */
1170 volatile uint8_t SMBRXF_CTL;
1171 volatile uint8_t reserved17[1];
1172 };
1173 };
1174 };
1175
1176 /* SMB register fields */
1177 #define NPCX_SMBST_XMIT 0
1178 #define NPCX_SMBST_MASTER 1
1179 #define NPCX_SMBST_NMATCH 2
1180 #define NPCX_SMBST_STASTR 3
1181 #define NPCX_SMBST_NEGACK 4
1182 #define NPCX_SMBST_BER 5
1183 #define NPCX_SMBST_SDAST 6
1184 #define NPCX_SMBST_SLVSTP 7
1185 #define NPCX_SMBCST_BUSY 0
1186 #define NPCX_SMBCST_BB 1
1187 #define NPCX_SMBCST_MATCH 2
1188 #define NPCX_SMBCST_GCMATCH 3
1189 #define NPCX_SMBCST_TSDA 4
1190 #define NPCX_SMBCST_TGSCL 5
1191 #define NPCX_SMBCST_MATCHAF 6
1192 #define NPCX_SMBCST_ARPMATCH 7
1193 #define NPCX_SMBCST2_MATCHA1F 0
1194 #define NPCX_SMBCST2_MATCHA2F 1
1195 #define NPCX_SMBCST2_MATCHA3F 2
1196 #define NPCX_SMBCST2_MATCHA4F 3
1197 #define NPCX_SMBCST2_MATCHA5F 4
1198 #define NPCX_SMBCST2_MATCHA6F 5
1199 #define NPCX_SMBCST2_MATCHA7F 6
1200 #define NPCX_SMBCST2_INTSTS 7
1201 #define NPCX_SMBCST3_MATCHA8F 0
1202 #define NPCX_SMBCST3_MATCHA9F 1
1203 #define NPCX_SMBCST3_MATCHA10F 2
1204 #define NPCX_SMBCTL1_START 0
1205 #define NPCX_SMBCTL1_STOP 1
1206 #define NPCX_SMBCTL1_INTEN 2
1207 #define NPCX_SMBCTL1_ACK 4
1208 #define NPCX_SMBCTL1_GCMEN 5
1209 #define NPCX_SMBCTL1_NMINTE 6
1210 #define NPCX_SMBCTL1_STASTRE 7
1211 #define NPCX_SMBCTL2_ENABLE 0
1212 #define NPCX_SMBCTL2_SCLFRQ0_6_FIELD FIELD(1, 7)
1213 #define NPCX_SMBCTL3_ARPMEN 2
1214 #define NPCX_SMBCTL3_SCLFRQ7_8_FIELD FIELD(0, 2)
1215 #define NPCX_SMBCTL3_IDL_START 3
1216 #define NPCX_SMBCTL3_400K 4
1217 #define NPCX_SMBCTL3_BNK_SEL 5
1218 #define NPCX_SMBCTL3_SDA_LVL 6
1219 #define NPCX_SMBCTL3_SCL_LVL 7
1220 #define NPCX_SMBCTL4_HLDT_FIELD FIELD(0, 6)
1221 #define NPCX_SMBCTL4_LVL_WE 7
1222 #define NPCX_SMBADDR1_SAEN 7
1223 #define NPCX_SMBADDR2_SAEN 7
1224 #define NPCX_SMBADDR3_SAEN 7
1225 #define NPCX_SMBADDR4_SAEN 7
1226 #define NPCX_SMBADDR5_SAEN 7
1227 #define NPCX_SMBADDR6_SAEN 7
1228 #define NPCX_SMBADDR7_SAEN 7
1229 #define NPCX_SMBADDR8_SAEN 7
1230 #define NPCX_SMBSEL_SMB4SEL 4
1231 #define NPCX_SMBSEL_SMB5SEL 5
1232 #define NPCX_SMBSEL_SMB6SEL 6
1233 #define NPCX_SMBFIF_CTS_RXF_TXE 1
1234 #define NPCX_SMBFIF_CTS_CLR_FIFO 6
1235 #define NPCX_SMBFIF_CTL_FIFO_EN 4
1236 #define NPCX_SMBRXF_STS_RX_THST 6
1237
1238 /* RX FIFO threshold */
1239 #define NPCX_SMBRXF_CTL_RX_THR FIELD(0, 6)
1240 #define NPCX_SMBRXF_CTL_LAST 7
1241
1242 /*
1243 * Internal 32-bit Timer (ITIM32) device registers
1244 */
1245 struct itim32_reg {
1246 volatile uint8_t reserved1;
1247 /* 0x001: Internal 32-bit Timer Prescaler */
1248 volatile uint8_t ITPRE32;
1249 volatile uint8_t reserved2[2];
1250 /* 0x004: Internal 32-bit Timer Control and Status */
1251 volatile uint8_t ITCTS32;
1252 volatile uint8_t reserved3[3];
1253 /* 0x008: Internal 32-Bit Timer Counter */
1254 volatile uint32_t ITCNT32;
1255 };
1256
1257 /*
1258 * Internal 64-bit Timer (ITIM54) device registers
1259 */
1260 struct itim64_reg {
1261 volatile uint8_t reserved1;
1262 /* 0x001: Internal 64-bit Timer Prescaler */
1263 volatile uint8_t ITPRE64;
1264 volatile uint8_t reserved2[2];
1265 /* 0x004: Internal 64-bit Timer Control and Status */
1266 volatile uint8_t ITCTS64;
1267 volatile uint8_t reserved3[3];
1268 /* 0x008: Internal 32-Bit Timer Counter */
1269 volatile uint32_t ITCNT64L;
1270 /* 0x00C: Internal 32-Bit Timer Counter */
1271 volatile uint32_t ITCNT64H;
1272 };
1273
1274 /* ITIM register fields */
1275 #define NPCX_ITCTSXX_TO_STS 0
1276 #define NPCX_ITCTSXX_TO_IE 2
1277 #define NPCX_ITCTSXX_TO_WUE 3
1278 #define NPCX_ITCTSXX_CKSEL 4
1279 #define NPCX_ITCTSXX_ITEN 7
1280
1281 /*
1282 * Tachometer (TACH) Sensor device registers
1283 */
1284 struct tach_reg {
1285 /* 0x000: Timer/Counter 1 */
1286 volatile uint16_t TCNT1;
1287 /* 0x002: Reload/Capture A */
1288 volatile uint16_t TCRA;
1289 /* 0x004: Reload/Capture B */
1290 volatile uint16_t TCRB;
1291 /* 0x006: Timer/Counter 2 */
1292 volatile uint16_t TCNT2;
1293 /* 0x008: Clock Prescaler */
1294 volatile uint8_t TPRSC;
1295 volatile uint8_t reserved1;
1296 /* 0x00A: Clock Unit Control */
1297 volatile uint8_t TCKC;
1298 volatile uint8_t reserved2;
1299 /* 0x00C: Timer Mode Control */
1300 volatile uint8_t TMCTRL;
1301 volatile uint8_t reserved3;
1302 /* 0x00E: Timer Event Control */
1303 volatile uint8_t TECTRL;
1304 volatile uint8_t reserved4;
1305 /* 0x010: Timer Event Clear */
1306 volatile uint8_t TECLR;
1307 volatile uint8_t reserved5;
1308 /* 0x012: Timer Interrupt Enable */
1309 volatile uint8_t TIEN;
1310 volatile uint8_t reserved6;
1311 /* 0x014: Compare A */
1312 volatile uint16_t TCPA;
1313 /* 0x016: Compare B */
1314 volatile uint16_t TCPB;
1315 /* 0x018: Compare Configuration */
1316 volatile uint8_t TCPCFG;
1317 volatile uint8_t reserved7;
1318 /* 0x01A: Timer Wake-Up Enable */
1319 volatile uint8_t TWUEN;
1320 volatile uint8_t reserved8;
1321 /* 0x01C: Timer Configuration */
1322 volatile uint8_t TCFG;
1323 volatile uint8_t reserved9;
1324 };
1325
1326 /* TACH register fields */
1327 #define NPCX_TCKC_LOW_PWR 7
1328 #define NPCX_TCKC_PLS_ACC_CLK 6
1329 #define NPCX_TCKC_C1CSEL_FIELD FIELD(0, 3)
1330 #define NPCX_TCKC_C2CSEL_FIELD FIELD(3, 3)
1331 #define NPCX_TMCTRL_MDSEL_FIELD FIELD(0, 3)
1332 #define NPCX_TMCTRL_TAEN 5
1333 #define NPCX_TMCTRL_TBEN 6
1334 #define NPCX_TMCTRL_TAEDG 3
1335 #define NPCX_TMCTRL_TBEDG 4
1336 #define NPCX_TCFG_TADBEN 6
1337 #define NPCX_TCFG_TBDBEN 7
1338 #define NPCX_TECTRL_TAPND 0
1339 #define NPCX_TECTRL_TBPND 1
1340 #define NPCX_TECTRL_TCPND 2
1341 #define NPCX_TECTRL_TDPND 3
1342 #define NPCX_TECLR_TACLR 0
1343 #define NPCX_TECLR_TBCLR 1
1344 #define NPCX_TECLR_TCCLR 2
1345 #define NPCX_TECLR_TDCLR 3
1346 #define NPCX_TIEN_TAIEN 0
1347 #define NPCX_TIEN_TBIEN 1
1348 #define NPCX_TIEN_TCIEN 2
1349 #define NPCX_TIEN_TDIEN 3
1350 #define NPCX_TWUEN_TAWEN 0
1351 #define NPCX_TWUEN_TBWEN 1
1352 #define NPCX_TWUEN_TCWEN 2
1353 #define NPCX_TWUEN_TDWEN 3
1354
1355 /* Debug Interface registers */
1356 struct dbg_reg {
1357 /* 0x000: Debug Control */
1358 volatile uint8_t DBGCTRL;
1359 volatile uint8_t reserved1;
1360 /* 0x002: Debug Freeze Enable 1 */
1361 volatile uint8_t DBGFRZEN1;
1362 /* 0x003: Debug Freeze Enable 2 */
1363 volatile uint8_t DBGFRZEN2;
1364 /* 0x004: Debug Freeze Enable 3 */
1365 volatile uint8_t DBGFRZEN3;
1366 /* 0x005: Debug Freeze Enable 4 */
1367 volatile uint8_t DBGFRZEN4;
1368 };
1369 /* Debug Interface registers fields */
1370 #define NPCX_DBGFRZEN3_GLBL_FRZ_DIS 7
1371
1372 /* PS/2 Interface registers */
1373 struct ps2_reg {
1374 /* 0x000: PS/2 Data */
1375 volatile uint8_t PSDAT;
1376 volatile uint8_t reserved1;
1377 /* 0x002: PS/2 Status */
1378 volatile uint8_t PSTAT;
1379 volatile uint8_t reserved2;
1380 /* 0x004: PS/2 Control */
1381 volatile uint8_t PSCON;
1382 volatile uint8_t reserved3;
1383 /* 0x006: PS/2 Output Signal */
1384 volatile uint8_t PSOSIG;
1385 volatile uint8_t reserved4;
1386 /* 0x008: PS/2 Input Signal */
1387 volatile uint8_t PSISIG;
1388 volatile uint8_t reserved5;
1389 /* 0x00A: PS/2 Interrupt Enable */
1390 volatile uint8_t PSIEN;
1391 volatile uint8_t reserved6;
1392 };
1393
1394 /* PS/2 Interface registers fields */
1395 #define NPCX_PSTAT_SOT 0
1396 #define NPCX_PSTAT_EOT 1
1397 #define NPCX_PSTAT_PERR 2
1398 #define NPCX_PSTAT_ACH FIELD(3, 3)
1399 #define NPCX_PSTAT_RFERR 6
1400
1401 #define NPCX_PSCON_EN 0
1402 #define NPCX_PSCON_XMT 1
1403 #define NPCX_PSCON_HDRV FIELD(2, 2)
1404 #define NPCX_PSCON_IDB FIELD(4, 3)
1405 #define NPCX_PSCON_WPUED 7
1406
1407 #define NPCX_PSOSIG_WDAT0 0
1408 #define NPCX_PSOSIG_WDAT1 1
1409 #define NPCX_PSOSIG_WDAT2 2
1410 #define NPCX_PSOSIG_CLK0 3
1411 #define NPCX_PSOSIG_CLK1 4
1412 #define NPCX_PSOSIG_CLK2 5
1413 #define NPCX_PSOSIG_WDAT3 6
1414 #define NPCX_PSOSIG_CLK3 7
1415 #define NPCX_PSOSIG_CLK(n) (((n) < 3) ? ((n) + 3) : 7)
1416 #define NPCX_PSOSIG_WDAT(n) (((n) < 3) ? ((n) + 0) : 6)
1417 #define NPCX_PSOSIG_CLK_MASK_ALL \
1418 (BIT(NPCX_PSOSIG_CLK0) | \
1419 BIT(NPCX_PSOSIG_CLK1) | \
1420 BIT(NPCX_PSOSIG_CLK2) | \
1421 BIT(NPCX_PSOSIG_CLK3))
1422
1423 #define NPCX_PSIEN_SOTIE 0
1424 #define NPCX_PSIEN_EOTIE 1
1425 #define NPCX_PSIEN_PS2_WUE 4
1426 #define NPCX_PSIEN_PS2_CLK_SEL 7
1427
1428 /* Flash Interface Unit (FIU) device registers */
1429 struct fiu_reg {
1430 volatile uint8_t reserved1;
1431 /* 0x001: Burst Configuration */
1432 volatile uint8_t BURST_CFG;
1433 /* 0x002: FIU Response Configuration */
1434 volatile uint8_t RESP_CFG;
1435 volatile uint8_t reserved2[17];
1436 /* 0x014: SPI Flash Configuration */
1437 volatile uint8_t SPI_FL_CFG;
1438 volatile uint8_t reserved3;
1439 /* 0x016: UMA Code Byte */
1440 volatile uint8_t UMA_CODE;
1441 /* 0x017: UMA Address Byte 0 */
1442 volatile uint8_t UMA_AB0;
1443 /* 0x018: UMA Address Byte 1 */
1444 volatile uint8_t UMA_AB1;
1445 /* 0x019: UMA Address Byte 2 */
1446 volatile uint8_t UMA_AB2;
1447 /* 0x01A: UMA Data Byte 0 */
1448 volatile uint8_t UMA_DB0;
1449 /* 0x01B: UMA Data Byte 1 */
1450 volatile uint8_t UMA_DB1;
1451 /* 0x01C: UMA Data Byte 2 */
1452 volatile uint8_t UMA_DB2;
1453 /* 0x01D: UMA Data Byte 3 */
1454 volatile uint8_t UMA_DB3;
1455 /* 0x01E: UMA Control and Status */
1456 volatile uint8_t UMA_CTS;
1457 /* 0x01F: UMA Extended Control and Status */
1458 volatile uint8_t UMA_ECTS;
1459 /* 0x020: UMA Data Bytes 0-3 */
1460 volatile uint32_t UMA_DB0_3;
1461 volatile uint8_t reserved4[2];
1462 /* 0x026: CRC Control Register */
1463 volatile uint8_t CRCCON;
1464 /* 0x027: CRC Entry Register */
1465 volatile uint8_t CRCENT;
1466 /* 0x028: CRC Initialization and Result Register */
1467 volatile uint32_t CRCRSLT;
1468 volatile uint8_t reserved5[4];
1469 /* 0x030: FIU Read Command */
1470 volatile uint8_t FIU_RD_CMD;
1471 volatile uint8_t reserved6;
1472 /* 0x032: FIU Dummy Cycles */
1473 volatile uint8_t FIU_DMM_CYC;
1474 /* 0x033: FIU Extended Configuration */
1475 volatile uint8_t FIU_EXT_CFG;
1476 };
1477
1478 /* FIU register fields */
1479 #define NPCX_RESP_CFG_IAD_EN 0
1480 #define NPCX_RESP_CFG_DEV_SIZE_EX 2
1481 #define NPCX_UMA_CTS_A_SIZE 3
1482 #define NPCX_UMA_CTS_C_SIZE 4
1483 #define NPCX_UMA_CTS_RD_WR 5
1484 #define NPCX_UMA_CTS_DEV_NUM 6
1485 #define NPCX_UMA_CTS_EXEC_DONE 7
1486 #define NPCX_UMA_ECTS_SW_CS0 0
1487 #define NPCX_UMA_ECTS_SW_CS1 1
1488 #define NPCX_UMA_ECTS_SEC_CS 2
1489 #define NPCX_UMA_ECTS_UMA_LOCK 3
1490
1491 /* UMA fields selections */
1492 #define UMA_FLD_ADDR BIT(NPCX_UMA_CTS_A_SIZE) /* 3-bytes ADR field */
1493 #define UMA_FLD_NO_CMD BIT(NPCX_UMA_CTS_C_SIZE) /* No 1-Byte CMD field */
1494 #define UMA_FLD_WRITE BIT(NPCX_UMA_CTS_RD_WR) /* Write transaction */
1495 #define UMA_FLD_SHD_SL BIT(NPCX_UMA_CTS_DEV_NUM) /* Shared flash selected */
1496 #define UMA_FLD_EXEC BIT(NPCX_UMA_CTS_EXEC_DONE)
1497
1498 #define UMA_FIELD_DATA_1 0x01
1499 #define UMA_FIELD_DATA_2 0x02
1500 #define UMA_FIELD_DATA_3 0x03
1501 #define UMA_FIELD_DATA_4 0x04
1502
1503 /* UMA code for transaction */
1504 #define UMA_CODE_CMD_ONLY (UMA_FLD_EXEC | UMA_FLD_SHD_SL)
1505 #define UMA_CODE_CMD_ADR (UMA_FLD_EXEC | UMA_FLD_ADDR | \
1506 UMA_FLD_SHD_SL)
1507 #define UMA_CODE_CMD_RD_BYTE(n) (UMA_FLD_EXEC | UMA_FIELD_DATA_##n | \
1508 UMA_FLD_SHD_SL)
1509 #define UMA_CODE_RD_BYTE(n) (UMA_FLD_EXEC | UMA_FLD_NO_CMD | \
1510 UMA_FIELD_DATA_##n | UMA_FLD_SHD_SL)
1511 #define UMA_CODE_CMD_WR_ONLY (UMA_FLD_EXEC | UMA_FLD_WRITE | \
1512 UMA_FLD_SHD_SL)
1513 #define UMA_CODE_CMD_WR_BYTE(n) (UMA_FLD_EXEC | UMA_FLD_WRITE | \
1514 UMA_FIELD_DATA_##n | UMA_FLD_SHD_SL)
1515 #define UMA_CODE_CMD_WR_ADR (UMA_FLD_EXEC | UMA_FLD_WRITE | UMA_FLD_ADDR | \
1516 UMA_FLD_SHD_SL)
1517
1518 #define UMA_CODE_CMD_ADR_WR_BYTE(n) (UMA_FLD_EXEC | UMA_FLD_WRITE | \
1519 UMA_FLD_ADDR | UMA_FIELD_DATA_##n | \
1520 UMA_FLD_SHD_SL)
1521
1522 /* Platform Environment Control Interface (PECI) device registers */
1523 struct peci_reg {
1524 /* 0x000: PECI Control Status */
1525 volatile uint8_t PECI_CTL_STS;
1526 /* 0x001: PECI Read Length */
1527 volatile uint8_t PECI_RD_LENGTH;
1528 /* 0x002: PECI Address */
1529 volatile uint8_t PECI_ADDR;
1530 /* 0x003: PECI Command */
1531 volatile uint8_t PECI_CMD;
1532 /* 0x004: PECI Control 2 */
1533 volatile uint8_t PECI_CTL2;
1534 /* 0x005: PECI Index */
1535 volatile uint8_t PECI_INDEX;
1536 /* 0x006: PECI Index Data */
1537 volatile uint8_t PECI_IDATA;
1538 /* 0x007: PECI Write Length */
1539 volatile uint8_t PECI_WR_LENGTH;
1540 volatile uint8_t reserved1[3];
1541 /* 0x00B: PECI Write FCS */
1542 volatile uint8_t PECI_WR_FCS;
1543 /* 0x00C: PECI Read FCS */
1544 volatile uint8_t PECI_RD_FCS;
1545 /* 0x00D: PECI Assured Write FCS */
1546 volatile uint8_t PECI_AW_FCS;
1547 volatile uint8_t reserved2;
1548 /* 0x00F: PECI Transfer Rate */
1549 volatile uint8_t PECI_RATE;
1550 /* 0x010 - 0x04F: PECI Data In/Out */
1551 union {
1552 volatile uint8_t PECI_DATA_IN[64];
1553 volatile uint8_t PECI_DATA_OUT[64];
1554 };
1555 };
1556
1557 /* PECI register fields */
1558 #define NPCX_PECI_CTL_STS_START_BUSY 0
1559 #define NPCX_PECI_CTL_STS_DONE 1
1560 #define NPCX_PECI_CTL_STS_CRC_ERR 3
1561 #define NPCX_PECI_CTL_STS_ABRT_ERR 4
1562 #define NPCX_PECI_CTL_STS_AWFCS_EB 5
1563 #define NPCX_PECI_CTL_STS_DONE_EN 6
1564 #define NPCX_PECI_RATE_MAX_BIT_RATE FIELD(0, 5)
1565 #define NPCX_PECI_RATE_MAX_BIT_RATE_MASK 0x1F
1566 /* The minimal valid value of NPCX_PECI_RATE_MAX_BIT_RATE field */
1567 #define PECI_MAX_BIT_RATE_VALID_MIN 0x05
1568 #define PECI_HIGH_SPEED_MIN_VAL 0x07
1569
1570 #define NPCX_PECI_RATE_EHSP 6
1571
1572 /* KBS (Keyboard Scan) device registers */
1573 struct kbs_reg {
1574 volatile uint8_t reserved1[4];
1575 /* 0x004: Keyboard Scan In */
1576 volatile uint8_t KBSIN;
1577 /* 0x005: Keyboard Scan In Pull-Up Enable */
1578 volatile uint8_t KBSINPU;
1579 /* 0x006: Keyboard Scan Out 0 */
1580 volatile uint16_t KBSOUT0;
1581 /* 0x008: Keyboard Scan Out 1 */
1582 volatile uint16_t KBSOUT1;
1583 /* 0x00A: Keyboard Scan Buffer Index */
1584 volatile uint8_t KBS_BUF_INDX;
1585 /* 0x00B: Keyboard Scan Buffer Data */
1586 volatile uint8_t KBS_BUF_DATA;
1587 /* 0x00C: Keyboard Scan Event */
1588 volatile uint8_t KBSEVT;
1589 /* 0x00D: Keyboard Scan Control */
1590 volatile uint8_t KBSCTL;
1591 /* 0x00E: Keyboard Scan Configuration Index */
1592 volatile uint8_t KBS_CFG_INDX;
1593 /* 0x00F: Keyboard Scan Configuration Data */
1594 volatile uint8_t KBS_CFG_DATA;
1595 };
1596
1597 /* KBS register fields */
1598 #define NPCX_KBSBUFINDX 0
1599 #define NPCX_KBSEVT_KBSDONE 0
1600 #define NPCX_KBSEVT_KBSERR 1
1601 #define NPCX_KBSCTL_START 0
1602 #define NPCX_KBSCTL_KBSMODE 1
1603 #define NPCX_KBSCTL_KBSIEN 2
1604 #define NPCX_KBSCTL_KBSINC 3
1605 #define NPCX_KBSCTL_KBHDRV_FIELD FIELD(6, 2)
1606 #define NPCX_KBSCFGINDX 0
1607 /* Index of 'Automatic Scan' configuration register */
1608 #define KBS_CFG_INDX_DLY1 0 /* Keyboard Scan Delay T1 Byte */
1609 #define KBS_CFG_INDX_DLY2 1 /* Keyboard Scan Delay T2 Byte */
1610 #define KBS_CFG_INDX_RTYTO 2 /* Keyboard Scan Retry Timeout */
1611 #define KBS_CFG_INDX_CNUM 3 /* Keyboard Scan Columns Number */
1612 #define KBS_CFG_INDX_CDIV 4 /* Keyboard Scan Clock Divisor */
1613
1614 /* SHI (Serial Host Interface) registers */
1615 struct shi_reg {
1616 volatile uint8_t reserved1;
1617 /* 0x001: SHI Configuration 1 */
1618 volatile uint8_t SHICFG1;
1619 /* 0x002: SHI Configuration 2 */
1620 volatile uint8_t SHICFG2;
1621 volatile uint8_t reserved2[2];
1622 /* 0x005: Event Enable */
1623 volatile uint8_t EVENABLE;
1624 /* 0x006: Event Status */
1625 volatile uint8_t EVSTAT;
1626 /* 0x007: SHI Capabilities */
1627 volatile uint8_t CAPABILITY;
1628 /* 0x008: Status */
1629 volatile uint8_t STATUS;
1630 volatile uint8_t reserved3;
1631 /* 0x00A: Input Buffer Status */
1632 volatile uint8_t IBUFSTAT;
1633 /* 0x00B: Output Buffer Status */
1634 volatile uint8_t OBUFSTAT;
1635 /* 0x00C: SHI Configuration 3 */
1636 volatile uint8_t SHICFG3;
1637 /* 0x00D: SHI Configuration 4 */
1638 volatile uint8_t SHICFG4;
1639 /* 0x00E: SHI Configuration 5 */
1640 volatile uint8_t SHICFG5;
1641 /* 0x00F: Event Status 2 */
1642 volatile uint8_t EVSTAT2;
1643 /* 0x010: Event Enable 2 */
1644 volatile uint8_t EVENABLE2;
1645 volatile uint8_t reserved4[15];
1646 /* 0x20~0x9F: Output Buffer */
1647 volatile uint8_t OBUF[128];
1648 /* 0xA0~0x11F: Input Buffer */
1649 volatile uint8_t IBUF[128];
1650 };
1651
1652 /* SHI register fields */
1653 #define NPCX_SHICFG1_EN 0
1654 #define NPCX_SHICFG1_MODE 1
1655 #define NPCX_SHICFG1_WEN 2
1656 #define NPCX_SHICFG1_AUTIBF 3
1657 #define NPCX_SHICFG1_AUTOBE 4
1658 #define NPCX_SHICFG1_DAS 5
1659 #define NPCX_SHICFG1_CPOL 6
1660 #define NPCX_SHICFG1_IWRAP 7
1661 #define NPCX_SHICFG2_SIMUL 0
1662 #define NPCX_SHICFG2_BUSY 1
1663 #define NPCX_SHICFG2_ONESHOT 2
1664 #define NPCX_SHICFG2_SLWU 3
1665 #define NPCX_SHICFG2_REEN 4
1666 #define NPCX_SHICFG2_RESTART 5
1667 #define NPCX_SHICFG2_REEVEN 6
1668 #define NPCX_EVENABLE_OBEEN 0
1669 #define NPCX_EVENABLE_OBHEEN 1
1670 #define NPCX_EVENABLE_IBFEN 2
1671 #define NPCX_EVENABLE_IBHFEN 3
1672 #define NPCX_EVENABLE_EOREN 4
1673 #define NPCX_EVENABLE_EOWEN 5
1674 #define NPCX_EVENABLE_STSREN 6
1675 #define NPCX_EVENABLE_IBOREN 7
1676 #define NPCX_EVSTAT_OBE 0
1677 #define NPCX_EVSTAT_OBHE 1
1678 #define NPCX_EVSTAT_IBF 2
1679 #define NPCX_EVSTAT_IBHF 3
1680 #define NPCX_EVSTAT_EOR 4
1681 #define NPCX_EVSTAT_EOW 5
1682 #define NPCX_EVSTAT_STSR 6
1683 #define NPCX_EVSTAT_IBOR 7
1684 #define NPCX_STATUS_OBES 6
1685 #define NPCX_STATUS_IBFS 7
1686 #define NPCX_SHICFG3_OBUFLVLDIS 7
1687 #define NPCX_SHICFG4_IBUFLVLDIS 7
1688 #define NPCX_SHICFG5_IBUFLVL2 FIELD(0, 6)
1689 #define NPCX_SHICFG5_IBUFLVL2DIS 7
1690 #define NPCX_EVSTAT2_IBHF2 0
1691 #define NPCX_EVSTAT2_CSNRE 1
1692 #define NPCX_EVSTAT2_CSNFE 2
1693 #define NPCX_EVENABLE2_IBHF2EN 0
1694 #define NPCX_EVENABLE2_CSNREEN 1
1695 #define NPCX_EVENABLE2_CSNFEEN 2
1696
1697 #endif /* _NUVOTON_NPCX_REG_DEF_H */
1698
