1 /* ieee802154_mcr20a_regs.h - Registers definition for NXP MCR20A */ 2 3 /* 4 * Copyright (c) 2017 PHYTEC Messtechnik GmbH 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * 8 * This file is based on MCR20reg.h, it was modified to meet the 9 * coding style and restructured to make it easier to read. 10 * Additional identifiers was inserted (_MASK and _SHIFT endings), 11 * which are used in the macros for the bit field manipulation. 12 * 13 * This file are derived from material that is 14 * Copyright (c) 2015, Freescale Semiconductor, Inc. 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are met: 19 * 20 * o Redistributions of source code must retain the above copyright notice, 21 * this list of conditions and the following disclaimer. 22 * 23 * o Redistributions in binary form must reproduce the above copyright notice, 24 * this list of conditions and the following disclaimer in the documentation 25 * and/or other materials provided with the distribution. 26 * 27 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its 28 * contributors may be used to endorse or promote products derived from this 29 * software without specific prior written permission. 30 * 31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 32 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 34 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 35 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 36 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 37 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 38 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 39 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 40 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 41 * POSSIBILITY OF SUCH DAMAGE. 42 */ 43 44 #ifndef ZEPHYR_DRIVERS_IEEE802154_IEEE802154_MCR20A_REGS_H_ 45 #define ZEPHYR_DRIVERS_IEEE802154_IEEE802154_MCR20A_REGS_H_ 46 47 #define MCR20A_REG_READ (BIT(7)) 48 #define MCR20A_BUF_READ (BIT(7) | BIT(6)) 49 #define MCR20A_BUF_BYTE_READ (BIT(7) | BIT(6) | BIT(5)) 50 #define MCR20A_REG_WRITE (0) 51 #define MCR20A_BUF_WRITE (BIT(6)) 52 #define MCR20A_BUF_BYTE_WRITE (BIT(6) | BIT(5)) 53 54 #define MCR20A_IRQSTS1 (0x0) 55 #define MCR20A_IRQSTS2 (0x1) 56 #define MCR20A_IRQSTS3 (0x2) 57 #define MCR20A_PHY_CTRL1 (0x3) 58 #define MCR20A_PHY_CTRL2 (0x4) 59 #define MCR20A_PHY_CTRL3 (0x5) 60 #define MCR20A_RX_FRM_LEN (0x6) 61 #define MCR20A_PHY_CTRL4 (0x7) 62 #define MCR20A_SRC_CTRL (0x8) 63 #define MCR20A_SRC_ADDRS_SUM_LSB (0x9) 64 #define MCR20A_SRC_ADDRS_SUM_MSB (0xa) 65 #define MCR20A_CCA1_ED_FNL (0xb) 66 #define MCR20A_EVENT_TIMER_LSB (0xc) 67 #define MCR20A_EVENT_TIMER_MSB (0xd) 68 #define MCR20A_EVENT_TIMER_USB (0xe) 69 #define MCR20A_TIMESTAMP_LSB (0xf) 70 #define MCR20A_TIMESTAMP_MSB (0x10) 71 #define MCR20A_TIMESTAMP_USB (0x11) 72 #define MCR20A_T3CMP_LSB (0x12) 73 #define MCR20A_T3CMP_MSB (0x13) 74 #define MCR20A_T3CMP_USB (0x14) 75 #define MCR20A_T2PRIMECMP_LSB (0x15) 76 #define MCR20A_T2PRIMECMP_MSB (0x16) 77 #define MCR20A_T1CMP_LSB (0x17) 78 #define MCR20A_T1CMP_MSB (0x18) 79 #define MCR20A_T1CMP_USB (0x19) 80 #define MCR20A_T2CMP_LSB (0x1a) 81 #define MCR20A_T2CMP_MSB (0x1b) 82 #define MCR20A_T2CMP_USB (0x1c) 83 #define MCR20A_T4CMP_LSB (0x1d) 84 #define MCR20A_T4CMP_MSB (0x1e) 85 #define MCR20A_T4CMP_USB (0x1f) 86 #define MCR20A_PLL_INT0 (0x20) 87 #define MCR20A_PLL_FRAC0_LSB (0x21) 88 #define MCR20A_PLL_FRAC0_MSB (0x22) 89 #define MCR20A_PA_PWR (0x23) 90 #define MCR20A_SEQ_STATE (0x24) 91 #define MCR20A_LQI_VALUE (0x25) 92 #define MCR20A_RSSI_CCA_CNT (0x26) 93 /* ---------------- (0x27) */ 94 #define MCR20A_ASM_CTRL1 (0x28) 95 #define MCR20A_ASM_CTRL2 (0x29) 96 #define MCR20A_ASM_DATA_0 (0x2a) 97 #define MCR20A_ASM_DATA_1 (0x2b) 98 #define MCR20A_ASM_DATA_2 (0x2c) 99 #define MCR20A_ASM_DATA_3 (0x2d) 100 #define MCR20A_ASM_DATA_4 (0x2e) 101 #define MCR20A_ASM_DATA_5 (0x2f) 102 #define MCR20A_ASM_DATA_6 (0x30) 103 #define MCR20A_ASM_DATA_7 (0x31) 104 #define MCR20A_ASM_DATA_8 (0x32) 105 #define MCR20A_ASM_DATA_9 (0x33) 106 #define MCR20A_ASM_DATA_A (0x34) 107 #define MCR20A_ASM_DATA_B (0x35) 108 #define MCR20A_ASM_DATA_C (0x36) 109 #define MCR20A_ASM_DATA_D (0x37) 110 #define MCR20A_ASM_DATA_E (0x38) 111 #define MCR20A_ASM_DATA_F (0x39) 112 /* ---------------- (0x3a) */ 113 #define MCR20A_OVERWRITE_VER (0x3b) 114 #define MCR20A_CLK_OUT_CTRL (0x3c) 115 #define MCR20A_PWR_MODES (0x3d) 116 #define MCR20A_IAR_INDEX (0x3e) 117 #define MCR20A_IAR_DATA (0x3f) 118 119 #define MCR20A_IRQSTS1_RX_FRM_PEND BIT(7) 120 #define MCR20A_IRQSTS1_PLL_UNLOCK_IRQ BIT(6) 121 #define MCR20A_IRQSTS1_FILTERFAIL_IRQ BIT(5) 122 #define MCR20A_IRQSTS1_RXWTRMRKIRQ BIT(4) 123 #define MCR20A_IRQSTS1_CCAIRQ BIT(3) 124 #define MCR20A_IRQSTS1_RXIRQ BIT(2) 125 #define MCR20A_IRQSTS1_TXIRQ BIT(1) 126 #define MCR20A_IRQSTS1_SEQIRQ BIT(0) 127 #define MCR20A_IRQSTS1_IRQ_MASK (0x7f) 128 129 #define MCR20A_IRQSTS2_CRCVALID BIT(7) 130 #define MCR20A_IRQSTS2_CCA BIT(6) 131 #define MCR20A_IRQSTS2_SRCADDR BIT(5) 132 #define MCR20A_IRQSTS2_PI BIT(4) 133 #define MCR20A_IRQSTS2_TMRSTATUS BIT(3) 134 #define MCR20A_IRQSTS2_ASM_IRQ BIT(2) 135 #define MCR20A_IRQSTS2_PB_ERR_IRQ BIT(1) 136 #define MCR20A_IRQSTS2_WAKE_IRQ BIT(0) 137 #define MCR20A_IRQSTS2_IRQ_MASK (0x7) 138 139 #define MCR20A_IRQSTS3_TMR4MSK BIT(7) 140 #define MCR20A_IRQSTS3_TMR3MSK BIT(6) 141 #define MCR20A_IRQSTS3_TMR2MSK BIT(5) 142 #define MCR20A_IRQSTS3_TMR1MSK BIT(4) 143 #define MCR20A_IRQSTS3_TMR_MASK (0xf0) 144 #define MCR20A_IRQSTS3_TMR4IRQ BIT(3) 145 #define MCR20A_IRQSTS3_TMR3IRQ BIT(2) 146 #define MCR20A_IRQSTS3_TMR2IRQ BIT(1) 147 #define MCR20A_IRQSTS3_TMR1IRQ BIT(0) 148 #define MCR20A_IRQSTS3_IRQ_MASK (0xf) 149 #define MCR20A_IRQSTS3_IRQ_SHIFT (0) 150 151 #define MCR20A_PHY_CTRL1_TMRTRIGEN BIT(7) 152 #define MCR20A_PHY_CTRL1_SLOTTED BIT(6) 153 #define MCR20A_PHY_CTRL1_CCABFRTX BIT(5) 154 #define MCR20A_PHY_CTRL1_RXACKRQD BIT(4) 155 #define MCR20A_PHY_CTRL1_AUTOACK BIT(3) 156 #define MCR20A_PHY_CTRL1_XCVSEQ_MASK (0x7) 157 #define MCR20A_PHY_CTRL1_XCVSEQ_SHIFT (0) 158 159 #define MCR20A_XCVSEQ_IDLE (0) 160 #define MCR20A_XCVSEQ_RECEIVE (1) 161 #define MCR20A_XCVSEQ_TX (2) 162 #define MCR20A_XCVSEQ_CCA (3) 163 #define MCR20A_XCVSEQ_TX_RX (4) 164 #define MCR20A_XCVSEQ_CONTINUOUS_CCA (5) 165 166 #define MCR20A_PHY_CTRL2_CRC_MSK BIT(7) 167 #define MCR20A_PHY_CTRL2_PLL_UNLOCK_MSK BIT(6) 168 #define MCR20A_PHY_CTRL2_FILTERFAIL_MSK BIT(5) 169 #define MCR20A_PHY_CTRL2_RX_WMRK_MSK BIT(4) 170 #define MCR20A_PHY_CTRL2_CCAMSK BIT(3) 171 #define MCR20A_PHY_CTRL2_RXMSK BIT(2) 172 #define MCR20A_PHY_CTRL2_TXMSK BIT(1) 173 #define MCR20A_PHY_CTRL2_SEQMSK BIT(0) 174 175 #define MCR20A_PHY_CTRL3_TMR4CMP_EN BIT(7) 176 #define MCR20A_PHY_CTRL3_TMR3CMP_EN BIT(6) 177 #define MCR20A_PHY_CTRL3_TMR2CMP_EN BIT(5) 178 #define MCR20A_PHY_CTRL3_TMR1CMP_EN BIT(4) 179 #define MCR20A_PHY_CTRL3_ASM_MSK BIT(2) 180 #define MCR20A_PHY_CTRL3_PB_ERR_MSK BIT(1) 181 #define MCR20A_PHY_CTRL3_WAKE_MSK BIT(0) 182 183 #define MCR20A_RX_FRM_LENGTH_MASK (0x7f) 184 185 #define MCR20A_PHY_CTRL4_TRCV_MSK BIT(7) 186 #define MCR20A_PHY_CTRL4_TC3TMOUT BIT(6) 187 #define MCR20A_PHY_CTRL4_PANCORDNTR0 BIT(5) 188 #define MCR20A_PHY_CTRL4_CCATYPE_MASK (0x18) 189 #define MCR20A_PHY_CTRL4_CCATYPE_SHIFT (3) 190 #define MCR20A_PHY_CTRL4_TMRLOAD BIT(2) 191 #define MCR20A_PHY_CTRL4_PROMISCUOUS BIT(1) 192 #define MCR20A_PHY_CTRL4_TC2PRIME_EN BIT(0) 193 194 #define MCR20A_SRC_CTRL_INDEX_MASK (0xf0) 195 #define MCR20A_SRC_CTRL_INDEX_SHIFT (4) 196 #define MCR20A_SRC_CTRL_ACK_FRM_PND BIT(3) 197 #define MCR20A_SRC_CTRL_SRCADDR_EN BIT(2) 198 #define MCR20A_SRC_CTRL_INDEX_EN BIT(1) 199 #define MCR20A_SRC_CTRL_INDEX_DISABLE BIT(0) 200 201 #define MCR20A_PLL_INT0_VAL_MASK (0x1f) 202 #define MCR20A_PLL_INT0_VAL_SHIFT (0) 203 204 #define MCR20A_PA_PWR_VAL_MASK (0x1f) 205 #define MCR20A_PA_PWR_VAL_SHIFT (0) 206 207 #define MCR20A_SEQ_STATE_MASK (0x1f) 208 209 #define MCR20A_ASM_CTRL1_CLEAR BIT(7) 210 #define MCR20A_ASM_CTRL1_START BIT(6) 211 #define MCR20A_ASM_CTRL1_SELFTST BIT(5) 212 #define MCR20A_ASM_CTRL1_CTR BIT(4) 213 #define MCR20A_ASM_CTRL1_CBC BIT(3) 214 #define MCR20A_ASM_CTRL1_AES BIT(2) 215 #define MCR20A_ASM_CTRL1_LOAD_MAC BIT(1) 216 217 #define MCR20A_ASM_CTRL2_DATA_REG_TYPE_SELECT_MASK (0x7) 218 #define MCR20A_ASM_CTRL2_DATA_REG_TYPE_SELECT_SHIFT (5) 219 #define MCR20A_ASM_CTRL2_TSTPAS BIT(1) 220 221 #define MCR20A_CLK_OUT_EXTEND BIT(7) 222 #define MCR20A_CLK_OUT_HIZ BIT(6) 223 #define MCR20A_CLK_OUT_SR BIT(5) 224 #define MCR20A_CLK_OUT_DS BIT(4) 225 #define MCR20A_CLK_OUT_EN BIT(3) 226 #define MCR20A_CLK_OUT_DIV_MASK (0x07) 227 #define MCR20A_CLK_OUT_DIV_SHIFT (0) 228 229 #define MCR20A_PWR_MODES_XTAL_READY BIT(5) 230 #define MCR20A_PWR_MODES_XTALEN BIT(4) 231 #define MCR20A_PWR_MODES_ASM_CLK_EN BIT(3) 232 #define MCR20A_PWR_MODES_AUTODOZE BIT(1) 233 #define MCR20A_PWR_MODES_PMC_MODE BIT(0) 234 235 #define MCR20A_PART_ID (0x00) 236 #define MCR20A_XTAL_TRIM (0x01) 237 #define MCR20A_PMC_LP_TRIM (0x02) 238 #define MCR20A_MACPANID0_LSB (0x03) 239 #define MCR20A_MACPANID0_MSB (0x04) 240 #define MCR20A_MACSHORTADDRS0_LSB (0x05) 241 #define MCR20A_MACSHORTADDRS0_MSB (0x06) 242 #define MCR20A_MACLONGADDRS0_0 (0x07) 243 #define MCR20A_MACLONGADDRS0_1 (0x08) 244 #define MCR20A_MACLONGADDRS0_2 (0x09) 245 #define MCR20A_MACLONGADDRS0_3 (0x0a) 246 #define MCR20A_MACLONGADDRS0_4 (0x0b) 247 #define MCR20A_MACLONGADDRS0_5 (0x0c) 248 #define MCR20A_MACLONGADDRS0_6 (0x0d) 249 #define MCR20A_MACLONGADDRS0_7 (0x0e) 250 #define MCR20A_RX_FRAME_FILTER (0x0f) 251 #define MCR20A_PLL_INT1 (0x10) 252 #define MCR20A_PLL_FRAC1_LSB (0x11) 253 #define MCR20A_PLL_FRAC1_MSB (0x12) 254 #define MCR20A_MACPANID1_LSB (0x13) 255 #define MCR20A_MACPANID1_MSB (0x14) 256 #define MCR20A_MACSHORTADDRS1_LSB (0x15) 257 #define MCR20A_MACSHORTADDRS1_MSB (0x16) 258 #define MCR20A_MACLONGADDRS1_0 (0x17) 259 #define MCR20A_MACLONGADDRS1_1 (0x18) 260 #define MCR20A_MACLONGADDRS1_2 (0x19) 261 #define MCR20A_MACLONGADDRS1_3 (0x1a) 262 #define MCR20A_MACLONGADDRS1_4 (0x1b) 263 #define MCR20A_MACLONGADDRS1_5 (0x1c) 264 #define MCR20A_MACLONGADDRS1_6 (0x1d) 265 #define MCR20A_MACLONGADDRS1_7 (0x1e) 266 #define MCR20A_DUAL_PAN_CTRL (0x1f) 267 #define MCR20A_DUAL_PAN_DWELL (0x20) 268 #define MCR20A_DUAL_PAN_STS (0x21) 269 #define MCR20A_CCA1_THRESH (0x22) 270 #define MCR20A_CCA1_ED_OFFSET_COMP (0x23) 271 #define MCR20A_LQI_OFFSET_COMP (0x24) 272 #define MCR20A_CCA_CTRL (0x25) 273 #define MCR20A_CCA2_CORR_PEAKS (0x26) 274 #define MCR20A_CCA2_THRESH (0x27) 275 #define MCR20A_TMR_PRESCALE (0x28) 276 /* ---------------- (0x29) */ 277 #define MCR20A_GPIO_DATA (0x2a) 278 #define MCR20A_GPIO_DIR (0x2b) 279 #define MCR20A_GPIO_PUL_EN (0x2c) 280 #define MCR20A_GPIO_SEL (0x2d) 281 #define MCR20A_GPIO_DS (0x2e) 282 /* ---------------- (0x2f) */ 283 #define MCR20A_ANT_PAD_CTRL (0x30) 284 #define MCR20A_MISC_PAD_CTRL (0x31) 285 #define MCR20A_BSM_CTRL (0x32) 286 /* ---------------- (0x33) */ 287 #define MCR20A_RNG (0x34) 288 #define MCR20A_RX_BYTE_COUNT (0x35) 289 #define MCR20A_RX_WTR_MARK (0x36) 290 #define MCR20A_SOFT_RESET (0x37) 291 #define MCR20A_TXDELAY (0x38) 292 #define MCR20A_ACKDELAY (0x39) 293 #define MCR20A_SEQ_MGR_CTRL (0x3a) 294 #define MCR20A_SEQ_MGR_STS (0x3b) 295 #define MCR20A_SEQ_T_STS (0x3c) 296 #define MCR20A_ABORT_STS (0x3d) 297 #define MCR20A_CCCA_BUSY_CNT (0x3e) 298 #define MCR20A_SRC_ADDR_CHECKSUM1 (0x3f) 299 #define MCR20A_SRC_ADDR_CHECKSUM2 (0x40) 300 #define MCR20A_SRC_TBL_VALID1 (0x41) 301 #define MCR20A_SRC_TBL_VALID2 (0x42) 302 #define MCR20A_FILTERFAIL_CODE1 (0x43) 303 #define MCR20A_FILTERFAIL_CODE2 (0x44) 304 #define MCR20A_SLOT_PRELOAD (0x45) 305 /* ---------------- (0x46) */ 306 #define MCR20A_CORR_VT (0x47) 307 #define MCR20A_SYNC_CTRL (0x48) 308 #define MCR20A_PN_LSB_0 (0x49) 309 #define MCR20A_PN_LSB_1 (0x4a) 310 #define MCR20A_PN_MSB_0 (0x4b) 311 #define MCR20A_PN_MSB_1 (0x4c) 312 #define MCR20A_CORR_NVAL (0x4d) 313 #define MCR20A_TX_MODE_CTRL (0x4e) 314 #define MCR20A_SNF_THR (0x4f) 315 #define MCR20A_FAD_THR (0x50) 316 #define MCR20A_ANT_AGC_CTRL (0x51) 317 #define MCR20A_AGC_THR1 (0x52) 318 #define MCR20A_AGC_THR2 (0x53) 319 #define MCR20A_AGC_HYS (0x54) 320 #define MCR20A_AFC (0x55) 321 #define MCR20A_LPPS_CTRL (0x56) 322 /* ---------------- (0x57) */ 323 #define MCR20A_PHY_STS (0x58) 324 #define MCR20A_RX_MAX_CORR (0x59) 325 #define MCR20A_RX_MAX_PREAMBLE (0x5a) 326 #define MCR20A_RSSI (0x5b) 327 /* ---------------- (0x5c) */ 328 /* ---------------- (0x5d) */ 329 #define MCR20A_PLL_DIG_CTRL (0x5e) 330 #define MCR20A_VCO_CAL (0x5f) 331 #define MCR20A_VCO_BEST_DIFF (0x60) 332 #define MCR20A_VCO_BIAS (0x61) 333 #define MCR20A_KMOD_CTRL (0x62) 334 #define MCR20A_KMOD_CAL (0x63) 335 #define MCR20A_PA_CAL (0x64) 336 #define MCR20A_PA_PWRCAL (0x65) 337 #define MCR20A_ATT_RSSI1 (0x66) 338 #define MCR20A_ATT_RSSI2 (0x67) 339 #define MCR20A_RSSI_OFFSET (0x68) 340 #define MCR20A_RSSI_SLOPE (0x69) 341 #define MCR20A_RSSI_CAL1 (0x6a) 342 #define MCR20A_RSSI_CAL2 (0x6b) 343 /* ---------------- (0x6c) */ 344 /* ---------------- (0x6d) */ 345 #define MCR20A_XTAL_CTRL (0x6e) 346 #define MCR20A_XTAL_COMP_MIN (0x6f) 347 #define MCR20A_XTAL_COMP_MAX (0x70) 348 #define MCR20A_XTAL_GM (0x71) 349 /* ---------------- (0x72) */ 350 /* ---------------- (0x73) */ 351 #define MCR20A_LNA_TUNE (0x74) 352 #define MCR20A_LNA_AGCGAIN (0x75) 353 /* ---------------- (0x76) */ 354 /* ---------------- (0x77) */ 355 #define MCR20A_CHF_PMA_GAIN (0x78) 356 #define MCR20A_CHF_IBUF (0x79) 357 #define MCR20A_CHF_QBUF (0x7a) 358 #define MCR20A_CHF_IRIN (0x7b) 359 #define MCR20A_CHF_QRIN (0x7c) 360 #define MCR20A_CHF_IL (0x7d) 361 #define MCR20A_CHF_QL (0x7e) 362 #define MCR20A_CHF_CC1 (0x7f) 363 #define MCR20A_CHF_CCL (0x80) 364 #define MCR20A_CHF_CC2 (0x81) 365 #define MCR20A_CHF_IROUT (0x82) 366 #define MCR20A_CHF_QROUT (0x83) 367 /* ---------------- (0x84) */ 368 /* ---------------- (0x85) */ 369 #define MCR20A_RSSI_CTRL (0x86) 370 /* ---------------- (0x87) */ 371 /* ---------------- (0x88) */ 372 #define MCR20A_PA_BIAS (0x89) 373 #define MCR20A_PA_TUNING (0x8a) 374 /* ---------------- (0x8b) */ 375 /* ---------------- (0x8c) */ 376 #define MCR20A_PMC_HP_TRIM (0x8d) 377 #define MCR20A_VREGA_TRIM (0x8e) 378 /* ---------------- (0x8f) */ 379 /* ---------------- (0x90) */ 380 #define MCR20A_VCO_CTRL1 (0x91) 381 #define MCR20A_VCO_CTRL2 (0x92) 382 /* ---------------- (0x93) */ 383 /* ---------------- (0x94) */ 384 #define MCR20A_ANA_SPARE_OUT1 (0x95) 385 #define MCR20A_ANA_SPARE_OUT2 (0x96) 386 #define MCR20A_ANA_SPARE_IN (0x97) 387 #define MCR20A_MISCELLANEOUS (0x98) 388 /* ---------------- (0x99) */ 389 #define MCR20A_SEQ_MGR_OVRD0 (0x9a) 390 #define MCR20A_SEQ_MGR_OVRD1 (0x9b) 391 #define MCR20A_SEQ_MGR_OVRD2 (0x9c) 392 #define MCR20A_SEQ_MGR_OVRD3 (0x9d) 393 #define MCR20A_SEQ_MGR_OVRD4 (0x9e) 394 #define MCR20A_SEQ_MGR_OVRD5 (0x9f) 395 #define MCR20A_SEQ_MGR_OVRD6 (0xa0) 396 #define MCR20A_SEQ_MGR_OVRD7 (0xa1) 397 /* ---------------- (0xa2) */ 398 #define MCR20A_TESTMODE_CTRL (0xa3) 399 #define MCR20A_DTM_CTRL1 (0xa4) 400 #define MCR20A_DTM_CTRL2 (0xa5) 401 #define MCR20A_ATM_CTRL1 (0xa6) 402 #define MCR20A_ATM_CTRL2 (0xa7) 403 #define MCR20A_ATM_CTRL3 (0xa8) 404 /* ---------------- (0xa9) */ 405 #define MCR20A_LIM_FE_TEST_CTRL (0xaa) 406 #define MCR20A_CHF_TEST_CTRL (0xab) 407 #define MCR20A_VCO_TEST_CTRL (0xac) 408 #define MCR20A_PLL_TEST_CTRL (0xad) 409 #define MCR20A_PA_TEST_CTRL (0xae) 410 #define MCR20A_PMC_TEST_CTRL (0xaf) 411 412 #define MCR20A_SCAN_DTM_PROTECT_1 (0xfe) 413 #define MCR20A_SCAN_DTM_PROTECT_0 (0xff) 414 415 #define MCR20A_RX_FRAME_FILTER_FRM_VER_MASK (0xc0) 416 #define MCR20A_RX_FRAME_FILTER_FRM_VER_SHIFT (6) 417 #define MCR20A_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS BIT(5) 418 #define MCR20A_RX_FRAME_FILTER_NS_FT BIT(4) 419 #define MCR20A_RX_FRAME_FILTER_CMD_FT BIT(3) 420 #define MCR20A_RX_FRAME_FILTER_ACK_FT BIT(2) 421 #define MCR20A_RX_FRAME_FILTER_DATA_FT BIT(1) 422 #define MCR20A_RX_FRAME_FILTER_BEACON_FT BIT(0) 423 424 #define MCR20A_PLL_INT1_MASK (0x1f) 425 426 #define MCR20A_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_MASK (0xf0) 427 #define MCR20A_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_SHIFT (4) 428 #define MCR20A_DUAL_PAN_CTRL_CURRENT_NETWORK BIT(3) 429 #define MCR20A_DUAL_PAN_CTRL_PANCORDNTR1 BIT(2) 430 #define MCR20A_DUAL_PAN_CTRL_DUAL_PAN_AUTO BIT(1) 431 #define MCR20A_DUAL_PAN_CTRL_ACTIVE_NETWORK BIT(0) 432 433 #define MCR20A_DUAL_PAN_STS_RECD_ON_PAN1 BIT(7) 434 #define MCR20A_DUAL_PAN_STS_RECD_ON_PAN0 BIT(6) 435 #define MCR20A_DUAL_PAN_STS_DUAL_PAN_REMAIN_MASK (0x3f) 436 437 #define MCR20A_CCA_CTRL_AGC_FRZ_EN BIT(6) 438 #define MCR20A_CCA_CTRL_CONT_RSSI_EN BIT(5) 439 #define MCR20A_CCA_CTRL_QI_RSSI_NOT_CORR BIT(4) 440 #define MCR20A_CCA_CTRL_CCA3_AND_NOT_OR BIT(3) 441 #define MCR20A_CCA_CTRL_OWER_COMP_EN_LQI BIT(2) 442 #define MCR20A_CCA_CTRL_OWER_COMP_EN_ED BIT(1) 443 #define MCR20A_CCA_CTRL_OWER_COMP_EN_CCA1 BIT(0) 444 445 #define MCR20A_CCA2_CORR_PEAKS_CCA2_MIN_NUM_CORR_TH_MASK (0x70) 446 #define MCR20A_CCA2_CORR_PEAKS_CCA2_MIN_NUM_CORR_TH_SHIFT (4) 447 #define MCR20A_CCA2_CORR_PEAKS_CCA2_NUM_CORR_PEAKS_MASK (0x0f) 448 449 #define MCR20A_TMR_PRESCALE_VAL_MASK (0x7) 450 #define MCR20A_TMR_PRESCALE_VAL_SHIFT (0) 451 452 #define MCR20A_TIMEBASE_500000HZ (2) 453 #define MCR20A_TIMEBASE_250000HZ (3) 454 #define MCR20A_TIMEBASE_125000HZ (4) 455 #define MCR20A_TIMEBASE_62500HZ (5) 456 #define MCR20A_TIMEBASE_31250HZ (6) 457 #define MCR20A_TIMEBASE_15625HZ (7) 458 459 #define MCR20A_GPIO_DATA8 BIT(7) 460 #define MCR20A_GPIO_DATA7 BIT(6) 461 #define MCR20A_GPIO_DATA6 BIT(5) 462 #define MCR20A_GPIO_DATA5 BIT(4) 463 #define MCR20A_GPIO_DATA4 BIT(3) 464 #define MCR20A_GPIO_DATA3 BIT(2) 465 #define MCR20A_GPIO_DATA2 BIT(1) 466 #define MCR20A_GPIO_DATA1 BIT(0) 467 468 #define MCR20A_GPIO_DIR8 BIT(7) 469 #define MCR20A_GPIO_DIR7 BIT(6) 470 #define MCR20A_GPIO_DIR6 BIT(5) 471 #define MCR20A_GPIO_DIR5 BIT(4) 472 #define MCR20A_GPIO_DIR4 BIT(3) 473 #define MCR20A_GPIO_DIR3 BIT(2) 474 #define MCR20A_GPIO_DIR2 BIT(1) 475 #define MCR20A_GPIO_DIR1 BIT(0) 476 477 #define MCR20A_GPIO_PUL_EN8 BIT(7) 478 #define MCR20A_GPIO_PUL_EN7 BIT(6) 479 #define MCR20A_GPIO_PUL_EN6 BIT(5) 480 #define MCR20A_GPIO_PUL_EN5 BIT(4) 481 #define MCR20A_GPIO_PUL_EN4 BIT(3) 482 #define MCR20A_GPIO_PUL_EN3 BIT(2) 483 #define MCR20A_GPIO_PUL_EN2 BIT(1) 484 #define MCR20A_GPIO_PUL_EN1 BIT(0) 485 486 #define MCR20A_GPIO_PUL_SEL8 BIT(7) 487 #define MCR20A_GPIO_PUL_SEL7 BIT(6) 488 #define MCR20A_GPIO_PUL_SEL6 BIT(5) 489 #define MCR20A_GPIO_PUL_SEL5 BIT(4) 490 #define MCR20A_GPIO_PUL_SEL4 BIT(3) 491 #define MCR20A_GPIO_PUL_SEL3 BIT(2) 492 #define MCR20A_GPIO_PUL_SEL2 BIT(1) 493 #define MCR20A_GPIO_PUL_SEL1 BIT(0) 494 495 #define MCR20A_GPIO_DS8 BIT(7) 496 #define MCR20A_GPIO_DS7 BIT(6) 497 #define MCR20A_GPIO_DS6 BIT(5) 498 #define MCR20A_GPIO_DS5 BIT(4) 499 #define MCR20A_GPIO_DS4 BIT(3) 500 #define MCR20A_GPIO_DS3 BIT(2) 501 #define MCR20A_GPIO_DS2 BIT(1) 502 #define MCR20A_GPIO_DS1 BIT(0) 503 504 #define MCR20A_ANT_PAD_CTRL_ANTX_POL3 BIT(7) 505 #define MCR20A_ANT_PAD_CTRL_ANTX_POL2 BIT(6) 506 #define MCR20A_ANT_PAD_CTRL_ANTX_POL1 BIT(5) 507 #define MCR20A_ANT_PAD_CTRL_ANTX_POL0 BIT(4) 508 #define MCR20A_ANT_PAD_CTRL_ANTX_CTRLMODE BIT(3) 509 #define MCR20A_ANT_PAD_CTRL_ANTX_HZ BIT(2) 510 #define MCR20A_ANT_PAD_CTRL_ANTX_EN_MASK (0x03) 511 #define MCR20A_ANT_PAD_CTRL_ANTX_EN_SHIFT (0) 512 513 #define MCR20A_MISC_PAD_CTRL_MISO_HIZ_EN BIT(3) 514 #define MCR20A_MISC_PAD_CTRL_IRQ_B_OD BIT(2) 515 #define MCR20A_MISC_PAD_CTRL_NON_GPIO_DS BIT(1) 516 #define MCR20A_MISC_PAD_CTRL_ANTX_CURR BIT(0) 517 518 #define MCR20A_ANT_AGC_CTRL_SNF_EN BIT(7) 519 #define MCR20A_ANT_AGC_CTRL_AGC_EN BIT(6) 520 #define MCR20A_ANT_AGC_CTRL_AGC_LEVEL_MASK (0x30) 521 #define MCR20A_ANT_AGC_CTRL_AGC_LEVEL_SHIFT (4) 522 #define MCR20A_ANT_AGC_CTRL_ANTX BIT(1) 523 #define MCR20A_ANT_AGC_CTRL_AD_EN BIT(0) 524 525 #define MCR20A_LPPS_BUFMIX_EN BIT(4) 526 #define MCR20A_LPPS_LIM_EN BIT(3) 527 #define MCR20A_LPPS_RSSI_EN BIT(2) 528 #define MCR20A_LPPS_LNA_EN BIT(1) 529 #define MCR20A_LPPS_CTRL_LPPS_EN BIT(0) 530 531 /* Undocumented part copied from MCR20reg.h */ 532 #define MCR20A_SOFT_RESET_SOG_RST BIT(7) 533 #define MCR20A_SOFT_RESET_REGS_RST BIT(4) 534 #define MCR20A_SOFT_RESET_PLL_RST BIT(3) 535 #define MCR20A_SOFT_RESET_TX_RST BIT(2) 536 #define MCR20A_SOFT_RESET_RX_RST BIT(1) 537 #define MCR20A_SOFT_RESET_SEQ_MGR_RST BIT(0) 538 539 #define MCR20A_SEQ_MGR_CTRL_SEQ_STATE_CTRL_MASK (0x3) 540 #define MCR20A_SEQ_MGR_CTRL_SEQ_STATE_CTRL_SHIFT (6) 541 #define MCR20A_SEQ_MGR_CTRL_NO_RX_RECYCLE BIT(5) 542 #define MCR20A_SEQ_MGR_CTRL_LATCH_PREAMBLE BIT(4) 543 #define MCR20A_SEQ_MGR_CTRL_EVENT_TMR_DO_NOT_LATCH BIT(3) 544 #define MCR20A_SEQ_MGR_CTRL_CLR_NEW_SEQ_INHIBIT BIT(2) 545 #define MCR20A_SEQ_MGR_CTRL_PSM_LOCK_DIS BIT(1) 546 #define MCR20A_SEQ_MGR_CTRL_PLL_ABORT_OVRD BIT(0) 547 548 #define MCR20A_SEQ_MGR_STS_TMR2_SEQ_TRIG_ARMED BIT(7) 549 #define MCR20A_SEQ_MGR_STS_RX_MODE BIT(6) 550 #define MCR20A_SEQ_MGR_STS_RX_TIMEOUT_PENDING BIT(5) 551 #define MCR20A_SEQ_MGR_STS_NEW_SEQ_INHIBIT BIT(4) 552 #define MCR20A_SEQ_MGR_STS_SEQ_IDLE BIT(3) 553 #define MCR20A_SEQ_MGR_STS_XCVSEQ_ACTUAL_MASK (0x7) 554 #define MCR20A_SEQ_MGR_STS_XCVSEQ_ACTUAL_SHIFT (0) 555 556 #define MCR20A_ABORT_STS_PLL_ABORTED BIT(2) 557 #define MCR20A_ABORT_STS_TC3_ABORTED BIT(1) 558 #define MCR20A_ABORT_STS_SW_ABORTED BIT(0) 559 560 #define MCR20A_PHY_STS_PLL_UNLOCK BIT(7) 561 #define MCR20A_PHY_STS_PLL_LOCK_ERR BIT(6) 562 #define MCR20A_PHY_STS_PLL_LOCK BIT(5) 563 #define MCR20A_PHY_STS_CRCVALID BIT(3) 564 #define MCR20A_PHY_STS_FILTERFAIL_FLAG_SEL BIT(2) 565 #define MCR20A_PHY_STS_SFD_DET BIT(1) 566 #define MCR20A_PHY_STS_PREAMBLE_DET BIT(0) 567 568 #define MCR20A_TESTMODE_CTRL_HOT_ANT BIT(4) 569 #define MCR20A_TESTMODE_CTRL_IDEAL_RSSI_EN BIT(3) 570 #define MCR20A_TESTMODE_CTRL_IDEAL_PFC_EN BIT(2) 571 #define MCR20A_TESTMODE_CTRL_CONTINUOUS_EN BIT(1) 572 #define MCR20A_TESTMODE_CTRL_FPGA_EN BIT(0) 573 574 #define MCR20A_DTM_CTRL1_ATM_LOCKED BIT(7) 575 #define MCR20A_DTM_CTRL1_DTM_EN BIT(6) 576 #define MCR20A_DTM_CTRL1_PAGE5 BIT(5) 577 #define MCR20A_DTM_CTRL1_PAGE4 BIT(4) 578 #define MCR20A_DTM_CTRL1_PAGE3 BIT(3) 579 #define MCR20A_DTM_CTRL1_PAGE2 BIT(2) 580 #define MCR20A_DTM_CTRL1_PAGE1 BIT(1) 581 #define MCR20A_DTM_CTRL1_PAGE0 BIT(0) 582 583 #define MCR20A_TX_MODE_CTRL_TX_INV BIT(4) 584 #define MCR20A_TX_MODE_CTRL_BT_EN BIT(3) 585 #define MCR20A_TX_MODE_CTRL_DTS2 BIT(2) 586 #define MCR20A_TX_MODE_CTRL_DTS1 BIT(1) 587 #define MCR20A_TX_MODE_CTRL_DTS0 BIT(0) 588 #define MCR20A_TX_MODE_CTRL_DTS_MASK (7) 589 590 #endif /* ZEPHYR_DRIVERS_IEEE802154_IEEE802154_MCR20A_REGS_H_ */ 591
