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Searched refs:DT_INST_PARENT (Results 1 – 25 of 43) sorted by relevance

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/Zephyr-Core-3.4.0/drivers/pwm/
Dpwm_gd32.c195 .reg = DT_REG_ADDR(DT_INST_PARENT(i)), \
196 .clkid = DT_CLOCKS_CELL(DT_INST_PARENT(i), id), \
197 .reset = RESET_DT_SPEC_GET(DT_INST_PARENT(i)), \
198 .prescaler = DT_PROP(DT_INST_PARENT(i), prescaler), \
199 .channels = DT_PROP(DT_INST_PARENT(i), channels), \
200 .is_32bit = DT_PROP(DT_INST_PARENT(i), is_32bit), \
201 .is_advanced = DT_PROP(DT_INST_PARENT(i), is_advanced), \
Dpwm_stm32.c720 IRQ_CONNECT(DT_IRQ_BY_NAME(DT_INST_PARENT(index), name, irq), \
721 DT_IRQ_BY_NAME(DT_INST_PARENT(index), name, priority), \
723 irq_enable(DT_IRQ_BY_NAME(DT_INST_PARENT(index), name, irq)); \
728 IRQ_CONNECT(DT_IRQN(DT_INST_PARENT(index)), \
729 DT_IRQ(DT_INST_PARENT(index), priority), \
731 irq_enable(DT_IRQN(DT_INST_PARENT(index))); \
737 COND_CODE_1(DT_IRQ_HAS_NAME(DT_INST_PARENT(index), cc), \
751 .bus = DT_CLOCKS_CELL(DT_INST_PARENT(index), bus), \
752 .enr = DT_CLOCKS_CELL(DT_INST_PARENT(index), bits) \
762 .timer = (TIM_TypeDef *)DT_REG_ADDR(DT_INST_PARENT(index)), \
[all …]
Dpwm_gecko.c102 .timer = (TIMER_TypeDef *)DT_REG_ADDR(DT_INST_PARENT(index)), \
/Zephyr-Core-3.4.0/drivers/sensor/qdec_stm32/
Dqdec_stm32.c145 .timer_inst = ((TIM_TypeDef *)DT_REG_ADDR(DT_INST_PARENT(n))), \
147 .bus = DT_CLOCKS_CELL(DT_INST_PARENT(n), bus), \
148 .enr = DT_CLOCKS_CELL(DT_INST_PARENT(n), bits) \
/Zephyr-Core-3.4.0/drivers/gpio/
Dgpio_emul_sdl.c87 BUILD_ASSERT(DT_NODE_HAS_COMPAT_STATUS(DT_INST_PARENT(inst), \
95 .emul = DEVICE_DT_GET(DT_INST_PARENT(inst)), \
Dgpio_npm6001.c236 .bus = I2C_DT_SPEC_GET(DT_INST_PARENT(n))}; \
Dgpio_npm1300.c233 .bus = I2C_DT_SPEC_GET(DT_INST_PARENT(n))}; \
Dgpio_sc18im704.c282 DT_FOREACH_CHILD_STATUS_OKAY(DT_INST_PARENT(n), CHECK_COMPAT)
/Zephyr-Core-3.4.0/drivers/kscan/
Dkscan_input.c108 INPUT_LISTENER_CB_DEFINE(DEVICE_DT_GET(DT_INST_PARENT(index)), \
111 .input_dev = DEVICE_DT_GET(DT_INST_PARENT(index)), \
/Zephyr-Core-3.4.0/drivers/bbram/
Dbbram_stm32.c100 .parent = DEVICE_DT_GET(DT_INST_PARENT(inst)), \
101 .base_addr = DT_REG_ADDR(DT_INST_PARENT(inst)) + STM32_BKP_REG_OFFSET, \
/Zephyr-Core-3.4.0/drivers/w1/
Dw1_ds2482-800_channel.c165 .parent = DEVICE_DT_GET(DT_INST_PARENT(inst)), \
166 .i2c_spec = I2C_DT_SPEC_GET(DT_INST_PARENT(inst)), \
/Zephyr-Core-3.4.0/drivers/i2c/
Di2c_sc18im704.c332 .bus = DEVICE_DT_GET(DT_BUS(DT_INST_PARENT(n))), \
333 .bus_speed = DT_PROP_OR(DT_INST_PARENT(n), target_speed, 9600), \
334 .reset_gpios = GPIO_DT_SPEC_GET_OR(DT_INST_PARENT(n), reset_gpios, {0}), \
/Zephyr-Core-3.4.0/drivers/memc/
Dmemc_stm32_nor_psram.c168 .nor_psram = (FMC_NORSRAM_TypeDef *)(DT_REG_ADDR(DT_INST_PARENT(0)) + SRAM_OFFSET),
169 .extended = (FMC_NORSRAM_EXTENDED_TypeDef *)(DT_REG_ADDR(DT_INST_PARENT(0))
Dmemc_stm32_sdram.c123 .sdram = (FMC_SDRAM_TypeDef *)(DT_REG_ADDR(DT_INST_PARENT(0)) +
/Zephyr-Core-3.4.0/drivers/reset/
Dreset_gd32.c70 .base = DT_REG_ADDR(DT_INST_PARENT(0)),
Dreset_stm32.c74 .base = DT_REG_ADDR(DT_INST_PARENT(0)),
/Zephyr-Core-3.4.0/drivers/dma/
Ddma_intel_lpss.c85 .parent = DEVICE_DT_GET(DT_INST_PARENT(n)), \
/Zephyr-Core-3.4.0/drivers/counter/
Dcounter_mcux_qtmr.c308 .base = (void *)DT_REG_ADDR(DT_INST_PARENT(n)), \
309 .clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_INST_PARENT(n))), \
311 (clock_control_subsys_t)DT_CLOCKS_CELL(DT_INST_PARENT(n), name), \
/Zephyr-Core-3.4.0/drivers/ps2/
Dps2_npcx_channel.c114 .ps2_ctrl = DEVICE_DT_GET(DT_INST_PARENT(inst)), \
/Zephyr-Core-3.4.0/drivers/disk/
Dmmc_subsys.c117 .host_controller = DEVICE_DT_GET(DT_INST_PARENT(n)), \
Dsdmmc_subsys.c125 .host_controller = DEVICE_DT_GET(DT_INST_PARENT(n)), \
/Zephyr-Core-3.4.0/drivers/mdio/
Dmdio_sam.c135 .regs = (Gmac *)DT_REG_ADDR(DT_INST_PARENT(n)), \
/Zephyr-Core-3.4.0/drivers/watchdog/
Dwdt_npm6001.c180 .bus = I2C_DT_SPEC_GET(DT_INST_PARENT(n)), \
/Zephyr-Core-3.4.0/drivers/clock_control/
Dclock_control_gd32.c209 .base = DT_REG_ADDR(DT_INST_PARENT(0)),
/Zephyr-Core-3.4.0/drivers/serial/
Duart_rpi_pico_pio.c187 .piodev = DEVICE_DT_GET(DT_INST_PARENT(idx)), \

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