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Searched refs:DT_DEP_ORD (Results 1 – 16 of 16) sorted by relevance

/Zephyr-Core-3.4.0/drivers/clock_control/
Dclock_control_smartbond.c26 case DT_DEP_ORD(DT_NODELABEL(rc32k)): in smartbond_clock_control_on()
29 case DT_DEP_ORD(DT_NODELABEL(rcx)): in smartbond_clock_control_on()
32 case DT_DEP_ORD(DT_NODELABEL(xtal32k)): in smartbond_clock_control_on()
35 case DT_DEP_ORD(DT_NODELABEL(rc32m)): in smartbond_clock_control_on()
38 case DT_DEP_ORD(DT_NODELABEL(xtal32m)): in smartbond_clock_control_on()
42 case DT_DEP_ORD(DT_NODELABEL(pll)): in smartbond_clock_control_on()
68 case DT_DEP_ORD(DT_NODELABEL(rc32k)): in smartbond_clock_control_off()
74 case DT_DEP_ORD(DT_NODELABEL(rcx)): in smartbond_clock_control_off()
80 case DT_DEP_ORD(DT_NODELABEL(xtal32k)): in smartbond_clock_control_off()
86 case DT_DEP_ORD(DT_NODELABEL(rc32m)): in smartbond_clock_control_off()
[all …]
Dclock_control_ifx_cat1.c17 #define GET_CLK_SOURCE_ORD(N) DT_DEP_ORD(DT_CLOCKS_CTLR_BY_IDX(DT_NODELABEL(N), 0))
103 [INFINEON_CAT1_CLOCK_IMO] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_imo)) },
106 [INFINEON_CAT1_CLOCK_PATHMUX0] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(path_mux0)) },
110 [INFINEON_CAT1_CLOCK_PATHMUX1] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(path_mux1)) },
114 [INFINEON_CAT1_CLOCK_PATHMUX2] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(path_mux2)) },
118 [INFINEON_CAT1_CLOCK_PATHMUX3] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(path_mux3)) },
122 [INFINEON_CAT1_CLOCK_PATHMUX4] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(path_mux4)) },
126 [INFINEON_CAT1_CLOCK_HF0] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf0)) },
130 [INFINEON_CAT1_CLOCK_HF1] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf1)) },
134 [INFINEON_CAT1_CLOCK_HF2] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf2)) },
[all …]
/Zephyr-Core-3.4.0/include/zephyr/devicetree/
Dordinals.h25 #define DT_DEP_ORD(node_id) DT_CAT(node_id, _ORD) macro
71 #define DT_INST_DEP_ORD(inst) DT_DEP_ORD(DT_DRV_INST(inst))
/Zephyr-Core-3.4.0/soc/arm/nxp_imx/rt/
Dsoc.h29 #if (DT_DEP_ORD(DT_NODELABEL(ocram)) != DT_DEP_ORD(DT_CHOSEN(zephyr_sram))) && \
Dmpu_regions.c9 #define IS_CHOSEN_SRAM(x) (DT_DEP_ORD(DT_NODELABEL(x)) == DT_DEP_ORD(DT_CHOSEN(zephyr_sram)))
Dlinker.ld9 #define IS_CHOSEN_SRAM(x) (DT_DEP_ORD(DT_NODELABEL(x)) == DT_DEP_ORD(DT_CHOSEN(zephyr_sram)))
Dsections.ld9 #define IS_CHOSEN_SRAM(x) (DT_DEP_ORD(DT_NODELABEL(x)) == DT_DEP_ORD(DT_CHOSEN(zephyr_sram)))
Dsoc_rt10xx.c338 #if (DT_DEP_ORD(DT_NODELABEL(ocram)) != DT_DEP_ORD(DT_CHOSEN(zephyr_sram))) && \ in z_arm_platform_init()
Dsoc_rt11xx.c701 #if (DT_DEP_ORD(DT_NODELABEL(ocram)) != DT_DEP_ORD(DT_CHOSEN(zephyr_sram))) && \ in z_arm_platform_init()
/Zephyr-Core-3.4.0/drivers/regulator/
Dregulator_fake.c75 #define FAKE_DATA_NAME(node_id) _CONCAT(data_, DT_DEP_ORD(node_id))
76 #define FAKE_CONF_NAME(node_id) _CONCAT(config_, DT_DEP_ORD(node_id))
/Zephyr-Core-3.4.0/tests/lib/devicetree/api/src/
Dmain.c1726 zassert_equal(DT_DEP_ORD(DT_SPI_DEV_CS_GPIOS_CTLR(TEST_SPI_DEV_0)), in ZTEST()
1727 DT_DEP_ORD(DT_NODELABEL(test_gpio_1)), in ZTEST()
2254 #define DEP_ORD_AND_COMMA(node_id) DT_DEP_ORD(node_id),
2259 DT_DEP_ORD(node_id), \
2260 DT_DEP_ORD(DT_PARENT(node_id)), \
2275 unsigned int root_ord = DT_DEP_ORD(DT_ROOT), in ZTEST()
2276 test_ord = DT_DEP_ORD(DT_PATH(test)), in ZTEST()
2291 zassert_true(DT_DEP_ORD(DT_NODELABEL(test_child_a)) > in ZTEST()
2292 DT_DEP_ORD(DT_NODELABEL(test_children)), ""); in ZTEST()
2293 zassert_true(DT_DEP_ORD(DT_NODELABEL(test_irq)) > in ZTEST()
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/Zephyr-Core-3.4.0/include/zephyr/
Ddevice.h95 #define Z_DEVICE_DT_DEV_ID(node_id) _CONCAT(dts_ord_, DT_DEP_ORD(node_id))
832 (DT_DEP_ORD(node_id), DT_REQUIRES_DEP_ORDS(node_id)), \
Ddevicetree.h568 (DT_DEP_ORD(node_id1) == (DT_DEP_ORD(node_id2)))
/Zephyr-Core-3.4.0/include/zephyr/drivers/pcie/
Dpcie.h59 #define Z_DEVICE_PCIE_NAME(node_id) _CONCAT(pcie_dev_, DT_DEP_ORD(node_id))
/Zephyr-Core-3.4.0/tests/lib/devicetree/devices/src/
Dmain.c54 NULL, NULL, POST_KERNEL, 70, NULL, DT_DEP_ORD(TEST_DEVB), 999);
/Zephyr-Core-3.4.0/doc/releases/
Drelease-notes-2.5.rst802 - :c:macro:`DT_DEP_ORD`, :c:macro:`DT_INST_DEP_ORD`