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Searched refs:DT_CHOSEN (Results 1 – 25 of 156) sorted by relevance

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/Zephyr-Core-3.4.0/soc/arc/snps_qemu/
Dlinker.ld12 #if DT_NODE_HAS_PROP(DT_CHOSEN(zephyr_sram), reg) && \
13 (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) > 0)
14 #define SRAM_START DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
15 #define SRAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
21 #if DT_NODE_HAS_PROP(DT_CHOSEN(zephyr_flash), reg) && \
22 (DT_REG_SIZE(DT_CHOSEN(zephyr_flash)) > 0)
23 #define FLASH_START DT_REG_ADDR(DT_CHOSEN(zephyr_flash))
24 #define FLASH_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))
/Zephyr-Core-3.4.0/boards/arc/qemu_arc/
Darc_mpu_regions.c26 #if DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) > 0
31 DT_REG_ADDR(DT_CHOSEN(zephyr_sram)),
32 DT_REG_SIZE(DT_CHOSEN(zephyr_sram)),
53 #if DT_REG_SIZE(DT_CHOSEN(zephyr_flash)) > 0
56 DT_REG_ADDR(DT_CHOSEN(zephyr_flash)),
57 DT_REG_SIZE(DT_CHOSEN(zephyr_flash)),
/Zephyr-Core-3.4.0/soc/arc/snps_arc_iot/
Dlinker.ld17 #if DT_NODE_HAS_PROP(DT_CHOSEN(zephyr_sram), reg) && \
18 (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) > 0)
19 #define SRAM_START DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
20 #define SRAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
23 #if DT_NODE_HAS_PROP(DT_CHOSEN(zephyr_flash), reg) && \
24 (DT_REG_SIZE(DT_CHOSEN(zephyr_flash)) > 0)
25 #define FLASH_START DT_REG_ADDR(DT_CHOSEN(zephyr_flash))
26 #define FLASH_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))
/Zephyr-Core-3.4.0/soc/arc/snps_nsim/
Dlinker.ld31 #if DT_NODE_HAS_PROP(DT_CHOSEN(zephyr_sram), reg) && (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) > 0)
32 #define SRAM_START DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
33 #define SRAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
37 #if DT_NODE_HAS_PROP(DT_CHOSEN(zephyr_flash), reg) && \
38 (DT_REG_SIZE(DT_CHOSEN(zephyr_flash)) > 0)
39 #define FLASH_START DT_REG_ADDR(DT_CHOSEN(zephyr_flash))
40 #define FLASH_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))
/Zephyr-Core-3.4.0/boards/arc/nsim/
Darc_mpu_regions.c58 #if DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) > 0
62 DT_REG_ADDR(DT_CHOSEN(zephyr_sram)),
63 DT_REG_SIZE(DT_CHOSEN(zephyr_sram)),
78 #if DT_REG_SIZE(DT_CHOSEN(zephyr_flash)) > 0
81 DT_REG_ADDR(DT_CHOSEN(zephyr_flash)),
82 DT_REG_SIZE(DT_CHOSEN(zephyr_flash)),
Dhaps_arcv3_init.c42 z_arc_v2_aux_reg_write(AUX_CLN_DATA, (DT_REG_ADDR(DT_CHOSEN(zephyr_sram)) / (1024 * 1024))); in haps_arcv3_init()
44 z_arc_v2_aux_reg_write(AUX_CLN_DATA, (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) / (1024 * 1024))); in haps_arcv3_init()
/Zephyr-Core-3.4.0/soc/x86/raptor_lake/
Dsoc.h28 #if DT_ON_BUS(DT_CHOSEN(zephyr_console), pcie)
30 #define X86_SOC_EARLY_SERIAL_PCIDEV DT_REG_ADDR(DT_CHOSEN(zephyr_console))
32 #define X86_SOC_EARLY_SERIAL_MMIO8_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_console))
/Zephyr-Core-3.4.0/soc/nios2/nios2f-zephyr/
Dlinker.ld14 #define _RAM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
15 #define _RAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
17 #define _ROM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_flash))
18 #define _ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))
/Zephyr-Core-3.4.0/soc/arc/snps_arc_hsdk/
Dlinker.ld16 #if DT_NODE_HAS_PROP(DT_CHOSEN(zephyr_sram), reg) && \
17 (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) > 0)
18 #define SRAM_START DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
19 #define SRAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
/Zephyr-Core-3.4.0/soc/arc/snps_arc_hsdk4xd/
Dlinker.ld16 #if DT_NODE_HAS_PROP(DT_CHOSEN(zephyr_sram), reg) && (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) > 0)
17 #define SRAM_START DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
18 #define SRAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
/Zephyr-Core-3.4.0/soc/nios2/nios2-qemu/
Dlinker.ld14 #define _RAM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
15 #define _RAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
17 #define _ROM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_flash))
18 #define _ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))
/Zephyr-Core-3.4.0/soc/arm/gigadevice/gd32a50x/
Dsoc.c13 register unsigned r0 __asm("r0") = DT_REG_ADDR(DT_CHOSEN(zephyr_sram)); in z_arm_platform_init()
15 DT_REG_ADDR(DT_CHOSEN(zephyr_sram)) + DT_REG_SIZE(DT_CHOSEN(zephyr_sram)); in z_arm_platform_init()
/Zephyr-Core-3.4.0/soc/arm/st_stm32/common/
Dccm.ld12 } GROUP_LINK_IN(LINKER_DT_NODE_REGION_NAME(DT_CHOSEN(zephyr_ccm)))
20 } GROUP_LINK_IN(LINKER_DT_NODE_REGION_NAME(DT_CHOSEN(zephyr_ccm)))
28 } GROUP_LINK_IN(LINKER_DT_NODE_REGION_NAME(DT_CHOSEN(zephyr_ccm)) AT> ROMABLE_REGION)
/Zephyr-Core-3.4.0/soc/x86/elkhart_lake/
Dsoc.h30 #if DT_ON_BUS(DT_CHOSEN(zephyr_console), pcie)
34 #define X86_SOC_EARLY_SERIAL_MMIO8_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_console))
/Zephyr-Core-3.4.0/kernel/
Dxip.c30 #if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_ccm), okay) in z_data_copy()
34 #if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay) in z_data_copy()
38 #if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay) in z_data_copy()
/Zephyr-Core-3.4.0/soc/arc/snps_emsdp/
Dlinker.ld17 #if DT_NODE_HAS_PROP(DT_CHOSEN(zephyr_sram), reg) && \
18 (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) > 0)
19 #define SRAM_START DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
20 #define SRAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
/Zephyr-Core-3.4.0/subsys/ipc/rpmsg_service/
Drpmsg_backend.h16 #define VDEV_START_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_ipc_shm))
17 #define VDEV_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_ipc_shm))
/Zephyr-Core-3.4.0/samples/subsys/ipc/openamp/
Dcommon.h11 #define VDEV_START_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_ipc_shm))
12 #define VDEV_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_ipc_shm))
/Zephyr-Core-3.4.0/arch/x86/core/
Dmemmap.c40 DT_REG_ADDR(DT_CHOSEN(zephyr_sram)),
41 DT_REG_SIZE(DT_CHOSEN(zephyr_sram)),
/Zephyr-Core-3.4.0/tests/drivers/can/timing/src/
Dmain.c219 const struct device *const dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_canbus)); in ZTEST_USER()
232 const struct device *const dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_canbus)); in ZTEST_USER()
254 const struct device *const dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_canbus)); in ZTEST_USER()
266 const struct device *const dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_canbus)); in ZTEST_USER()
286 const struct device *const dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_canbus)); in ZTEST_USER()
298 const struct device *const dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_canbus)); in ZTEST_USER()
315 const struct device *const dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_canbus)); in can_timing_setup()
/Zephyr-Core-3.4.0/tests/drivers/uart/uart_basic_api/src/
Dtest_uart_poll.c14 const struct device *const uart_dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_console)); in test_poll_in()
43 const struct device *const uart_dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_console)); in test_poll_out()
Dtest_uart_config.c39 const struct device *const uart_dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_console)); in test_configure()
61 const struct device *const uart_dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_console)); in test_config_get()
Dmain.c50 #if DT_NODE_HAS_COMPAT(DT_CHOSEN(zephyr_console), zephyr_cdc_acm_uart) in uart_basic_setup()
54 dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_console)); in uart_basic_setup()
/Zephyr-Core-3.4.0/include/zephyr/linker/
Dlinker-defs.h161 #if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_ccm), okay)
173 #if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)
180 #if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)
192 #if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_ocm), okay)
/Zephyr-Core-3.4.0/samples/subsys/usb/console/src/
Dmain.c13 BUILD_ASSERT(DT_NODE_HAS_COMPAT(DT_CHOSEN(zephyr_console), zephyr_cdc_acm_uart),
80 const struct device *const dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_console)); in main()

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