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Searched refs:APBSRC_CLK (Results 1 – 2 of 2) sorted by relevance

/Zephyr-Core-3.4.0/drivers/clock_control/
Dclock_control_npcx.c157 BUILD_ASSERT(APBSRC_CLK / (APB1DIV_VAL + 1) <= MHZ(50) &&
158 APBSRC_CLK / (APB1DIV_VAL + 1) >= MHZ(4) &&
161 BUILD_ASSERT(APBSRC_CLK / (APB2DIV_VAL + 1) <= MHZ(50) &&
162 APBSRC_CLK / (APB2DIV_VAL + 1) >= MHZ(8) &&
165 BUILD_ASSERT(APBSRC_CLK / (APB3DIV_VAL + 1) <= MHZ(50) &&
166 APBSRC_CLK / (APB3DIV_VAL + 1) >= KHZ(12500) &&
170 BUILD_ASSERT(APBSRC_CLK / (APB4DIV_VAL + 1) <= MHZ(100) &&
171 APBSRC_CLK / (APB4DIV_VAL + 1) >= MHZ(8) &&
/Zephyr-Core-3.4.0/soc/arm/nuvoton_npcx/common/
Dsoc_clock.h77 #define APBSRC_CLK OFMCLK macro
93 #define NPCX_APB_CLOCK(no) (APBSRC_CLK / (APB##no##DIV_VAL + 1))