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Searched refs:timing (Results 1 – 25 of 78) sorted by relevance

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/Zephyr-Core-2.7.6/tests/drivers/can/timing/src/
Dmain.c56 static void verify_bitrate(struct can_timing *timing, uint32_t bitrate) in verify_bitrate() argument
58 const uint32_t ts = 1 + timing->prop_seg + timing->phase_seg1 + in verify_bitrate()
59 timing->phase_seg2; in verify_bitrate()
64 zassert_not_equal(timing->prescaler, 0, "Prescaler is zero"); in verify_bitrate()
69 bitrate_calc = core_clock / timing->prescaler / ts; in verify_bitrate()
76 static void verify_sp(struct can_timing *timing, uint16_t sp, in verify_sp() argument
83 uint32_t ts = 1 + timing->prop_seg + timing->phase_seg1 + in verify_sp()
84 timing->phase_seg2; in verify_sp()
86 ((1 + timing->prop_seg + timing->phase_seg1) * 1000) / ts; in verify_sp()
88 zassert_true(timing->prop_seg <= max->prop_seg, "prop_seg exceeds max"); in verify_sp()
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/Zephyr-Core-2.7.6/doc/reference/timing_functions/
Dindex.rst6 The timing functions can be used to obtain execution time of
9 Please note that the timing functions may use a different timer
16 To allow using the timing functions, :kconfig:`CONFIG_TIMING_FUNCTIONS`
22 To gather timing information:
27 timing information. This usually starts the timer.
41 7. Repeat from step 3 to gather timing information for other
45 timing information. This usually stops the timer.
50 This shows an example on how to use the timing functions:
54 #include <timing/timing.h>
/Zephyr-Core-2.7.6/subsys/timing/
DKconfig8 When enabled, timing related functions are compiled. This is
9 useful for gathering timing on code execution.
15 Hidden option to indicate that timing functions need to be
19 to use timing functions.
DCMakeLists.txt6 zephyr_library_sources(timing.c)
/Zephyr-Core-2.7.6/drivers/can/
Dcan_mcp2515.c319 const struct can_timing *timing, in mcp2515_set_timing() argument
326 if (!timing) { in mcp2515_set_timing()
335 __ASSERT(timing->prescaler > 0, "Prescaler should be bigger than zero"); in mcp2515_set_timing()
336 uint8_t brp = timing->prescaler - 1; in mcp2515_set_timing()
337 if (timing->sjw != CAN_SJW_NO_CHANGE) { in mcp2515_set_timing()
338 dev_data->sjw = (timing->sjw - 1) << 6; in mcp2515_set_timing()
346 const uint8_t phseg1 = (timing->phase_seg1 - 1) << 3; in mcp2515_set_timing()
347 const uint8_t prseg = (timing->prop_seg - 1); in mcp2515_set_timing()
355 const uint8_t phseg2 = (timing->phase_seg2 - 1); in mcp2515_set_timing()
368 __ASSERT(timing->sjw <= 4, "1 <= SJW <= 4"); in mcp2515_set_timing()
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Dcan_mcan.c106 const struct can_timing *timing, in can_mcan_configure_timing() argument
109 if (timing) { in can_mcan_configure_timing()
112 __ASSERT_NO_MSG(timing->prop_seg == 0); in can_mcan_configure_timing()
113 __ASSERT_NO_MSG(timing->phase_seg1 <= 0x100 && in can_mcan_configure_timing()
114 timing->phase_seg1 > 0); in can_mcan_configure_timing()
115 __ASSERT_NO_MSG(timing->phase_seg2 <= 0x80 && in can_mcan_configure_timing()
116 timing->phase_seg2 > 0); in can_mcan_configure_timing()
117 __ASSERT_NO_MSG(timing->prescaler <= 0x200 && in can_mcan_configure_timing()
118 timing->prescaler > 0); in can_mcan_configure_timing()
119 __ASSERT_NO_MSG(timing->sjw <= 0x80 && timing->sjw > 0); in can_mcan_configure_timing()
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Dcan_mcux_flexcan.c120 struct can_timing timing; member
131 const struct can_timing *timing, in mcux_flexcan_set_timing() argument
137 uint8_t sjw_backup = data->timing.sjw; in mcux_flexcan_set_timing()
140 if (!timing) { in mcux_flexcan_set_timing()
144 data->timing = *timing; in mcux_flexcan_set_timing()
145 if (timing->sjw == CAN_SJW_NO_CHANGE) { in mcux_flexcan_set_timing()
146 data->timing.sjw = sjw_backup; in mcux_flexcan_set_timing()
149 timing_tmp.preDivider = data->timing.prescaler - 1U; in mcux_flexcan_set_timing()
150 timing_tmp.rJumpwidth = data->timing.sjw - 1U; in mcux_flexcan_set_timing()
151 timing_tmp.phaseSeg1 = data->timing.phase_seg1 - 1U; in mcux_flexcan_set_timing()
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Dcan_rcar.c613 const struct can_timing *timing) in can_rcar_set_bittiming() argument
617 bcr = RCAR_CAN_BCR_TSEG1(timing->phase_seg1 + timing->prop_seg - 1) | in can_rcar_set_bittiming()
618 RCAR_CAN_BCR_BPR(timing->prescaler - 1) | in can_rcar_set_bittiming()
619 RCAR_CAN_BCR_SJW(timing->sjw - 1) | in can_rcar_set_bittiming()
620 RCAR_CAN_BCR_TSEG2(timing->phase_seg2 - 1); in can_rcar_set_bittiming()
631 const struct can_timing *timing, in can_rcar_set_timing() argument
648 can_rcar_set_bittiming(config, timing); in can_rcar_set_timing()
847 struct can_timing timing; in can_rcar_init() local
898 timing.sjw = config->sjw; in can_rcar_init()
900 ret = can_calc_timing(dev, &timing, config->bus_speed, in can_rcar_init()
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Dcan_common.c271 int can_calc_prescaler(const struct device *dev, struct can_timing *timing, in can_calc_prescaler() argument
274 uint32_t ts = timing->prop_seg + timing->phase_seg1 + timing->phase_seg2 + in can_calc_prescaler()
284 timing->prescaler = core_clock / (bitrate * ts); in can_calc_prescaler()
286 return core_clock % (ts * timing->prescaler); in can_calc_prescaler()
Dcan_stm32.c357 const struct can_timing *timing, in can_stm32_set_timing() argument
375 (((timing->phase_seg1 - 1) << CAN_BTR_TS1_Pos) & CAN_BTR_TS1_Msk) | in can_stm32_set_timing()
376 (((timing->phase_seg2 - 1) << CAN_BTR_TS2_Pos) & CAN_BTR_TS2_Msk) | in can_stm32_set_timing()
377 (((timing->prescaler - 1) << CAN_BTR_BRP_Pos) & CAN_BTR_BRP_Msk); in can_stm32_set_timing()
379 if (timing->sjw != CAN_SJW_NO_CHANGE) { in can_stm32_set_timing()
381 (((timing->sjw - 1) << CAN_BTR_SJW_Pos) & CAN_BTR_SJW_Msk); in can_stm32_set_timing()
420 struct can_timing timing; in can_stm32_init() local
484 timing.sjw = cfg->sjw; in can_stm32_init()
486 ret = can_calc_timing(dev, &timing, cfg->bus_speed, in can_stm32_init()
493 timing.prescaler, timing.phase_seg1, timing.phase_seg2); in can_stm32_init()
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Dcan_handlers.c11 const struct can_timing *timing, in z_vrfy_can_set_timing() argument
17 (const struct can_timing *)timing, in z_vrfy_can_set_timing()
/Zephyr-Core-2.7.6/soc/arm/nordic_nrf/
DCMakeLists.txt13 # Use nRF-specific timing calculations only if DWT is not present
15 zephyr_library_sources(timing.c)
/Zephyr-Core-2.7.6/soc/arm/microchip_mec/mec172x/
DCMakeLists.txt14 # Use MEC172x timing calculations only if DWT is not present
16 zephyr_library_sources(timing.c)
/Zephyr-Core-2.7.6/soc/arm/microchip_mec/mec1501/
DCMakeLists.txt18 # Use MEC15xx timing calculations only if DWT is not present
20 zephyr_library_sources(timing.c)
/Zephyr-Core-2.7.6/include/drivers/
Dcan.h331 const struct can_timing *timing,
706 int can_calc_prescaler(const struct device *dev, struct can_timing *timing,
746 const struct can_timing *timing,
750 const struct can_timing *timing, in z_impl_can_set_timing() argument
756 return api->set_timing(dev, timing, timing_data); in z_impl_can_set_timing()
779 struct can_timing timing; in can_set_bitrate() local
785 ret = can_calc_timing(dev, &timing, bitrate, 875); in can_set_bitrate()
790 timing.sjw = CAN_SJW_NO_CHANGE; in can_set_bitrate()
800 return can_set_timing(dev, &timing, &timing_data); in can_set_bitrate()
802 return can_set_timing(dev, &timing, NULL); in can_set_bitrate()
/Zephyr-Core-2.7.6/drivers/memc/
Dmemc_stm32_sdram.c21 FMC_SDRAM_TimingTypeDef timing; member
50 (FMC_SDRAM_TimingTypeDef *)&config->banks[i].timing); in memc_stm32_sdram_init()
103 .timing = { \
/Zephyr-Core-2.7.6/subsys/lorawan/
DKconfig24 System Max Rx timing error value in ms to be used by LoRaWAN stack
25 for calculating the RX1/RX2 window timing.
/Zephyr-Core-2.7.6/arch/nios2/core/
DCMakeLists.txt19 zephyr_library_sources_ifdef(CONFIG_TIMING_FUNCTIONS timing.c)
/Zephyr-Core-2.7.6/doc/reference/networking/
Dcan_api.rst48 The bit-timing as defined in ISO 11898-1:2003 looks as following:
78 The timing parameters (SJW, bitrate and sampling point, or bitrate, Prop_Seg,
80 changed at run-time from the timing-API.
326 arguments. The first timing parameter sets the timing for classic CAN and
327 arbitration phase for CAN-FD. The second parameter sets the timing of the data
329 NULL to the second one. The `can_calc_timing` function can calculate timing from
335 struct can_timing timing;
341 ret = can_calc_timing(can_dev, &timing, 250000, 875);
347 LOG_ERR("Failed to calc a valid timing");
351 ret = can_set_timing(can_dev, &timing, NULL);
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/Zephyr-Core-2.7.6/drivers/eeprom/
DKconfig69 bool "Enable hardware timing simulation"
72 Enable Simulated hardware timing.
/Zephyr-Core-2.7.6/boards/shields/wnc_m14a2a/
DKconfig.defconfig20 # extend retry timing to 20 seconds for LTE/LTE-M
/Zephyr-Core-2.7.6/boards/shields/sparkfun_sara_r4/
DKconfig.defconfig27 # extend retry timing to 20 seconds for LTE/LTE-M
/Zephyr-Core-2.7.6/doc/reference/kernel/
Dindex.rst105 These pages cover timing related services.
110 timing/clocks.rst
111 timing/timers.rst
/Zephyr-Core-2.7.6/subsys/
DCMakeLists.txt30 add_subdirectory_ifdef(CONFIG_TIMING_FUNCTIONS timing)
/Zephyr-Core-2.7.6/arch/arm/core/aarch32/cortex_m/
DCMakeLists.txt27 zephyr_library_sources(timing.c)

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