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Searched refs:reg_val (Results 1 – 25 of 39) sorted by relevance

12

/Zephyr-Core-2.7.6/drivers/serial/
Duart_rcar.c132 uint8_t reg_val; in uart_rcar_set_baudrate() local
134 reg_val = ((data->clk_rate + 16 * baud_rate) / (32 * baud_rate) - 1); in uart_rcar_set_baudrate()
135 uart_rcar_write_8(config, SCBRR, reg_val); in uart_rcar_set_baudrate()
142 uint16_t reg_val; in uart_rcar_poll_in() local
155 reg_val = uart_rcar_read_16(config, SCFSR); in uart_rcar_poll_in()
156 reg_val &= ~SCFSR_RDF; in uart_rcar_poll_in()
157 uart_rcar_write_16(config, SCFSR, reg_val); in uart_rcar_poll_in()
169 uint16_t reg_val; in uart_rcar_poll_out() local
178 reg_val = uart_rcar_read_16(config, SCFSR); in uart_rcar_poll_out()
179 reg_val &= ~(SCFSR_TDFE | SCFSR_TEND); in uart_rcar_poll_out()
[all …]
Duart_xlnx_ps.c287 uint32_t reg_val; in uart_xlnx_ps_init() local
296 reg_val = sys_read32(reg_base + XUARTPS_MR_OFFSET); in uart_xlnx_ps_init()
297 reg_val &= (~(XUARTPS_MR_CHARLEN_MASK | XUARTPS_MR_STOPMODE_MASK | in uart_xlnx_ps_init()
299 reg_val |= XUARTPS_MR_CHARLEN_8_BIT | XUARTPS_MR_STOPMODE_1_BIT | in uart_xlnx_ps_init()
301 sys_write32(reg_val, reg_base + XUARTPS_MR_OFFSET); in uart_xlnx_ps_init()
341 uint32_t reg_val; in uart_xlnx_ps_poll_in() local
345 reg_val = sys_read32(reg_base + XUARTPS_SR_OFFSET); in uart_xlnx_ps_poll_in()
346 if ((reg_val & XUARTPS_SR_RXEMPTY) == 0) { in uart_xlnx_ps_poll_in()
372 uint32_t reg_val; in uart_xlnx_ps_poll_out() local
378 reg_val = sys_read32(reg_base + XUARTPS_SR_OFFSET); in uart_xlnx_ps_poll_out()
[all …]
/Zephyr-Core-2.7.6/drivers/ethernet/
Deth_xlnx_gem.c94 uint32_t reg_val; in DT_INST_FOREACH_STATUS_OKAY() local
190 reg_val = sys_read32(dev_conf->base_addr + in DT_INST_FOREACH_STATUS_OKAY()
192 reg_val |= ETH_XLNX_GEM_NWCTRL_MDEN_BIT; in DT_INST_FOREACH_STATUS_OKAY()
193 sys_write32(reg_val, dev_conf->base_addr + in DT_INST_FOREACH_STATUS_OKAY()
262 uint32_t reg_val; in eth_xlnx_gem_isr() local
265 reg_val = sys_read32(dev_conf->base_addr + ETH_XLNX_GEM_ISR_OFFSET); in eth_xlnx_gem_isr()
271 if (reg_val & ETH_XLNX_GEM_IXR_ERRORS_MASK) { in eth_xlnx_gem_isr()
273 dev->name, reg_val); in eth_xlnx_gem_isr()
285 if ((reg_val & ETH_XLNX_GEM_IXR_TX_COMPLETE_BIT) != 0) { in eth_xlnx_gem_isr()
296 if ((reg_val & ETH_XLNX_GEM_IXR_FRAME_RX_BIT) != 0) { in eth_xlnx_gem_isr()
[all …]
Dphy_xlnx_gem.c40 uint32_t reg_val; in phy_xlnx_gem_mdio_read() local
55 reg_val = sys_read32(base_addr + ETH_XLNX_GEM_NWSR_OFFSET); in phy_xlnx_gem_mdio_read()
56 } while ((reg_val & ETH_XLNX_GEM_MDIO_IDLE_BIT) == 0 && poll_cnt < 10); in phy_xlnx_gem_mdio_read()
67 reg_val = ETH_XLNX_GEM_PHY_MAINT_CONST_BITS; in phy_xlnx_gem_mdio_read()
69 reg_val |= ETH_XLNX_GEM_PHY_MAINT_READ_OP_BIT; in phy_xlnx_gem_mdio_read()
71 reg_val |= (((uint32_t)phy_addr & ETH_XLNX_GEM_PHY_MAINT_PHY_ADDRESS_MASK) << in phy_xlnx_gem_mdio_read()
74 reg_val |= (((uint32_t)reg_addr & ETH_XLNX_GEM_PHY_MAINT_REGISTER_ID_MASK) << in phy_xlnx_gem_mdio_read()
77 sys_write32(reg_val, base_addr + ETH_XLNX_GEM_PHY_MAINTENANCE_OFFSET); in phy_xlnx_gem_mdio_read()
87 reg_val = sys_read32(base_addr + ETH_XLNX_GEM_NWSR_OFFSET); in phy_xlnx_gem_mdio_read()
88 } while ((reg_val & ETH_XLNX_GEM_MDIO_IDLE_BIT) == 0 && poll_cnt < 10); in phy_xlnx_gem_mdio_read()
[all …]
Deth_stellaris.c126 uint32_t reg_val; in eth_stellaris_rx_pkt() local
144 reg_val = sys_read32(REG_MACDATA); in eth_stellaris_rx_pkt()
145 frame_len = reg_val & 0x0000ffff; in eth_stellaris_rx_pkt()
158 data = (uint8_t *)&reg_val + 2; in eth_stellaris_rx_pkt()
168 reg_val = sys_read32(REG_MACDATA); in eth_stellaris_rx_pkt()
170 data = (uint8_t *)&reg_val; in eth_stellaris_rx_pkt()
179 reg_val = sys_read32(REG_MACDATA); in eth_stellaris_rx_pkt()
188 data = (uint8_t *)&reg_val; in eth_stellaris_rx_pkt()
/Zephyr-Core-2.7.6/drivers/timer/
Dxlnx_psttc_timer.c101 uint32_t reg_val; in sys_clock_driver_init() local
125 reg_val = sys_read32(TIMER_BASE_ADDR + XTTCPS_CNT_CNTRL_OFFSET); in sys_clock_driver_init()
126 reg_val |= XTTCPS_CNT_CNTRL_RST_MASK; in sys_clock_driver_init()
127 sys_write32(reg_val, TIMER_BASE_ADDR + XTTCPS_CNT_CNTRL_OFFSET); in sys_clock_driver_init()
130 reg_val = sys_read32(TIMER_BASE_ADDR + XTTCPS_CNT_CNTRL_OFFSET); in sys_clock_driver_init()
131 reg_val |= XTTCPS_CNT_CNTRL_MATCH_MASK; in sys_clock_driver_init()
132 sys_write32(reg_val, TIMER_BASE_ADDR + XTTCPS_CNT_CNTRL_OFFSET); in sys_clock_driver_init()
135 reg_val = IS_ENABLED(CONFIG_TICKLESS_KERNEL) ? in sys_clock_driver_init()
137 sys_write32(reg_val, TIMER_BASE_ADDR + XTTCPS_MATCH_0_OFFSET); in sys_clock_driver_init()
144 reg_val = sys_read32(TIMER_BASE_ADDR + XTTCPS_IER_OFFSET); in sys_clock_driver_init()
[all …]
Drcar_cmt_timer.c58 uint32_t reg_val; in cmt_isr() local
61 reg_val = sys_read32(TIMER_BASE_ADDR + CMCSR0_OFFSET); in cmt_isr()
62 reg_val &= ~CSR_MATCH_FLAG; in cmt_isr()
63 sys_write32(reg_val, TIMER_BASE_ADDR + CMCSR0_OFFSET); in cmt_isr()
78 uint32_t reg_val; in sys_clock_driver_init() local
96 reg_val = sys_read32(TIMER_BASE_ADDR + CMSTR0_OFFSET); in sys_clock_driver_init()
97 reg_val &= ~START_BIT; in sys_clock_driver_init()
98 sys_write32(reg_val, TIMER_BASE_ADDR + CMSTR0_OFFSET); in sys_clock_driver_init()
100 reg_val = sys_read32(TIMER_BASE_ADDR + CMSTR1_OFFSET); in sys_clock_driver_init()
101 reg_val &= ~START_BIT; in sys_clock_driver_init()
[all …]
/Zephyr-Core-2.7.6/soc/arm/atmel_sam/same70/
Dsoc.c60 uint32_t reg_val; in clock_init() local
155 reg_val = PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk; in clock_init()
156 PMC->PMC_MCKR = reg_val | PMC_MCKR_CSS_MAIN_CLK; in clock_init()
191 reg_val = PMC->PMC_MCKR & ~PMC_MCKR_PRES_Msk; in clock_init()
192 PMC->PMC_MCKR = reg_val | PMC_MCKR_PRES_CLK_1; in clock_init()
200 reg_val = PMC->PMC_MCKR & ~PMC_MCKR_MDIV_Msk; in clock_init()
201 PMC->PMC_MCKR = reg_val | SOC_ATMEL_SAME70_MDIV; in clock_init()
209 reg_val = PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk; in clock_init()
210 PMC->PMC_MCKR = reg_val | PMC_MCKR_CSS_PLLA_CLK; in clock_init()
/Zephyr-Core-2.7.6/soc/arm/atmel_sam/samv71/
Dsoc.c61 uint32_t reg_val; in clock_init() local
156 reg_val = PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk; in clock_init()
157 PMC->PMC_MCKR = reg_val | PMC_MCKR_CSS_MAIN_CLK; in clock_init()
192 reg_val = PMC->PMC_MCKR & ~PMC_MCKR_PRES_Msk; in clock_init()
193 PMC->PMC_MCKR = reg_val | PMC_MCKR_PRES_CLK_1; in clock_init()
201 reg_val = PMC->PMC_MCKR & ~PMC_MCKR_MDIV_Msk; in clock_init()
202 PMC->PMC_MCKR = reg_val | SOC_ATMEL_SAMV71_MDIV; in clock_init()
210 reg_val = PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk; in clock_init()
211 PMC->PMC_MCKR = reg_val | PMC_MCKR_CSS_PLLA_CLK; in clock_init()
/Zephyr-Core-2.7.6/soc/arm/atmel_sam/sam4s/
Dsoc.c33 uint32_t reg_val; in clock_init() local
129 reg_val = PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk; in clock_init()
130 PMC->PMC_MCKR = reg_val | PMC_MCKR_CSS_MAIN_CLK; in clock_init()
165 reg_val = PMC->PMC_MCKR & ~PMC_MCKR_PRES_Msk; in clock_init()
166 PMC->PMC_MCKR = reg_val | PMC_MCKR_PRES_CLK_1; in clock_init()
174 reg_val = PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk; in clock_init()
175 PMC->PMC_MCKR = reg_val | PMC_MCKR_CSS_PLLA_CLK; in clock_init()
/Zephyr-Core-2.7.6/soc/arm/atmel_sam/sam4e/
Dsoc.c34 uint32_t reg_val; in clock_init() local
130 reg_val = PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk; in clock_init()
131 PMC->PMC_MCKR = reg_val | PMC_MCKR_CSS_MAIN_CLK; in clock_init()
166 reg_val = PMC->PMC_MCKR & ~PMC_MCKR_PRES_Msk; in clock_init()
167 PMC->PMC_MCKR = reg_val | PMC_MCKR_PRES_CLK_1; in clock_init()
175 reg_val = PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk; in clock_init()
176 PMC->PMC_MCKR = reg_val | PMC_MCKR_CSS_PLLA_CLK; in clock_init()
/Zephyr-Core-2.7.6/soc/arm/atmel_sam/sam3x/
Dsoc.c46 uint32_t reg_val; in clock_init() local
142 reg_val = PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk; in clock_init()
143 PMC->PMC_MCKR = reg_val | PMC_MCKR_CSS_MAIN_CLK; in clock_init()
178 reg_val = PMC->PMC_MCKR & ~PMC_MCKR_PRES_Msk; in clock_init()
179 PMC->PMC_MCKR = reg_val | PMC_MCKR_PRES_CLK_1; in clock_init()
187 reg_val = PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk; in clock_init()
188 PMC->PMC_MCKR = reg_val | PMC_MCKR_CSS_PLLA_CLK; in clock_init()
/Zephyr-Core-2.7.6/drivers/sensor/hp206c/
Dhp206c.c51 uint8_t *reg_val) in hp206c_read_reg() argument
55 return hp206c_read(dev, cmd, reg_val, 1); in hp206c_read_reg()
74 uint8_t reg_val) in hp206c_write_reg() argument
78 return hp206c_write(dev, cmd, &reg_val, 1); in hp206c_write_reg()
127 uint8_t reg_val; in hp206c_altitude_offs_set() local
129 reg_val = offs & 0xff; in hp206c_altitude_offs_set()
131 if (hp206c_write_reg(dev, HP206C_REG_ALT_OFF_LSB, reg_val) < 0) { in hp206c_altitude_offs_set()
135 reg_val = (offs & 0xff00) >> 8; in hp206c_altitude_offs_set()
137 if (hp206c_write_reg(dev, HP206C_REG_ALT_OFF_MSB, reg_val) < 0) { in hp206c_altitude_offs_set()
/Zephyr-Core-2.7.6/drivers/sensor/bmi160/
Dbmi160.c328 return range_map[i].reg_val; in bmi160_range_to_reg_val()
336 static int32_t bmi160_reg_val_to_range(uint8_t reg_val, in bmi160_reg_val_to_range() argument
343 if (reg_val == range_map[i].reg_val) { in bmi160_reg_val_to_range()
351 int32_t bmi160_acc_reg_val_to_range(uint8_t reg_val) in bmi160_acc_reg_val_to_range() argument
353 return bmi160_reg_val_to_range(reg_val, bmi160_acc_range_map, in bmi160_acc_reg_val_to_range()
357 int32_t bmi160_gyr_reg_val_to_range(uint8_t reg_val) in bmi160_gyr_reg_val_to_range() argument
359 return bmi160_reg_val_to_range(reg_val, bmi160_gyr_range_map, in bmi160_gyr_reg_val_to_range()
382 int32_t reg_val = bmi160_range_to_reg_val(range, in bmi160_acc_range_set() local
386 if (reg_val < 0) { in bmi160_acc_range_set()
387 return reg_val; in bmi160_acc_range_set()
[all …]
Dbmi160_trigger.c195 uint8_t acc_range_g, reg_val; in bmi160_acc_slope_config() local
199 if (bmi160_byte_read(dev, BMI160_REG_ACC_RANGE, &reg_val) < 0) { in bmi160_acc_slope_config()
203 acc_range_g = bmi160_acc_reg_val_to_range(reg_val); in bmi160_acc_slope_config()
212 reg_val = (slope_th_ums2 - 1) * 512U / (acc_range_g * SENSOR_G); in bmi160_acc_slope_config()
215 reg_val) < 0) { in bmi160_acc_slope_config()
/Zephyr-Core-2.7.6/drivers/sensor/lis2dh/
Dlis2dh_trigger.c134 uint8_t reg_val; in lis2dh_trigger_anym_set() local
150 status = lis2dh->hw_tf->read_reg(dev, LIS2DH_REG_INT2_SRC, &reg_val); in lis2dh_trigger_anym_set()
201 uint8_t range_g, reg_val; in lis2dh_acc_slope_config() local
205 &reg_val); in lis2dh_acc_slope_config()
211 range_g = 2 * (1 << ((LIS2DH_FS_MASK & reg_val) in lis2dh_acc_slope_config()
222 reg_val = 128 / range_g * (slope_th_ums2 - 1) / SENSOR_G; in lis2dh_acc_slope_config()
224 LOG_INF("int2_ths=0x%x range_g=%d ums2=%u", reg_val, in lis2dh_acc_slope_config()
228 reg_val); in lis2dh_acc_slope_config()
331 uint8_t reg_val; in lis2dh_thread_cb() local
335 &reg_val); in lis2dh_thread_cb()
[all …]
/Zephyr-Core-2.7.6/drivers/clock_control/
Dclock_control_rcar_cpg_mssr.c114 uint32_t reg_val; in cpg_rmstp_clock_endisable() local
121 reg_val = sys_read32(config->base_address + RMSTPSR(reg)); in cpg_rmstp_clock_endisable()
123 reg_val &= ~bitmask; in cpg_rmstp_clock_endisable()
125 reg_val |= bitmask; in cpg_rmstp_clock_endisable()
128 sys_write32(reg_val, config->base_address + RMSTPSR(reg)); in cpg_rmstp_clock_endisable()
/Zephyr-Core-2.7.6/drivers/sensor/bmc150_magn/
Dbmc150_magn.c30 uint8_t reg_val; member
104 reg_val << in bmc150_magn_set_odr()
117 uint8_t reg_val; in bmc150_magn_read_rep_xy() local
120 BMC150_MAGN_REG_REP_XY, &reg_val) < 0) { in bmc150_magn_read_rep_xy()
124 data->rep_xy = BMC150_MAGN_REGVAL_TO_REPXY((int)(reg_val)); in bmc150_magn_read_rep_xy()
133 uint8_t reg_val; in bmc150_magn_read_rep_z() local
136 BMC150_MAGN_REG_REP_Z, &reg_val) < 0) { in bmc150_magn_read_rep_z()
140 data->rep_z = BMC150_MAGN_REGVAL_TO_REPZ((int)(reg_val)); in bmc150_magn_read_rep_z()
179 uint8_t i, odr_val, reg_val; in bmc150_magn_read_odr() local
182 BMC150_MAGN_REG_OPMODE_ODR, &reg_val) < 0) { in bmc150_magn_read_odr()
[all …]
/Zephyr-Core-2.7.6/drivers/sensor/bmm150/
Dbmm150.c18 uint8_t reg_val; member
93 reg_val << in bmm150_set_odr()
105 uint8_t reg_val; in bmm150_read_rep_xy() local
108 BMM150_REG_REP_XY, &reg_val) < 0) { in bmm150_read_rep_xy()
112 data->rep_xy = BMM150_REGVAL_TO_REPXY((uint8_t)(reg_val)); in bmm150_read_rep_xy()
121 uint8_t reg_val; in bmm150_read_rep_z() local
124 BMM150_REG_REP_Z, &reg_val) < 0) { in bmm150_read_rep_z()
128 data->rep_z = BMM150_REGVAL_TO_REPZ((int)(reg_val)); in bmm150_read_rep_z()
168 uint8_t i, odr_val, reg_val; in bmm150_read_odr() local
171 BMM150_REG_OPMODE_ODR, &reg_val) < 0) { in bmm150_read_odr()
[all …]
/Zephyr-Core-2.7.6/drivers/sensor/sx9500/
Dsx9500_trigger.c68 uint8_t reg_val; in sx9500_gpio_thread_cb() local
71 SX9500_REG_IRQ_SRC, &reg_val) < 0) { in sx9500_gpio_thread_cb()
76 if ((reg_val & SX9500_CONV_DONE_IRQ) && data->handler_drdy) { in sx9500_gpio_thread_cb()
80 if ((reg_val & SX9500_NEAR_FAR_IRQ) && data->handler_near_far) { in sx9500_gpio_thread_cb()
/Zephyr-Core-2.7.6/drivers/gpio/
Dgpio_intel.c397 uint32_t pin, raw_pin, reg_addr, reg_val, cmp; in port_get_raw() local
422 reg_val = sys_read32(reg_addr); in port_get_raw()
424 if ((reg_val & cmp) != 0U) { in port_get_raw()
437 uint32_t pin, raw_pin, reg_addr, reg_val; in port_set_raw() local
455 reg_val = sys_read32(reg_addr); in port_set_raw()
458 reg_val |= PAD_CFG0_TXSTATE; in port_set_raw()
460 reg_val &= ~PAD_CFG0_TXSTATE; in port_set_raw()
463 sys_write32(reg_val, reg_addr); in port_set_raw()
/Zephyr-Core-2.7.6/drivers/sensor/sht3xd/
Dsht3xd_trigger.c41 uint16_t set_cmd, clear_cmd, reg_val, temp, rh; in sht3xd_attr_set() local
73 reg_val = (rh & 0xFE00) | ((temp & 0xFF80) >> 7); in sht3xd_attr_set()
75 if (sht3xd_write_reg(dev, set_cmd, reg_val) < 0 || in sht3xd_attr_set()
76 sht3xd_write_reg(dev, clear_cmd, reg_val) < 0) { in sht3xd_attr_set()
/Zephyr-Core-2.7.6/drivers/interrupt_controller/
Dintc_gic.c125 uint32_t reg_val; in gic_dist_init() local
146 reg_val = cpu_mask | (cpu_mask << 8) | (cpu_mask << 16) in gic_dist_init()
149 sys_write32(reg_val, GICD_ITARGETSRn + i); in gic_dist_init()
/Zephyr-Core-2.7.6/drivers/ieee802154/
Dieee802154_kw41z.c527 for (uint16_t reg_val = 0, i = 0; i < pkt_len; i++) { in kw41z_rx() local
529 reg_val = ZLL->PKT_BUFFER_RX[i/2U]; in kw41z_rx()
530 buf->data[i] = reg_val & 0xFF; in kw41z_rx()
532 buf->data[i] = reg_val >> 8; in kw41z_rx()
537 for (uint32_t reg_val = 0, i = 0; i < pkt_len; i++) { in kw41z_rx() local
540 reg_val = ZLL->PKT_BUFFER[i/4U]; in kw41z_rx()
541 buf->data[i] = reg_val & 0xFF; in kw41z_rx()
544 buf->data[i] = (reg_val >> 8) & 0xFF; in kw41z_rx()
547 buf->data[i] = (reg_val >> 16) & 0xFF; in kw41z_rx()
550 buf->data[i] = reg_val >> 24; in kw41z_rx()
/Zephyr-Core-2.7.6/drivers/sensor/bmp388/
Dbmp388.c259 uint8_t reg_val = 0; in bmp388_attr_set_oversampling() local
284 ++reg_val; in bmp388_attr_set_oversampling()
290 reg_val << pos); in bmp388_attr_set_oversampling()
297 data->osr_pressure = reg_val; in bmp388_attr_set_oversampling()
299 data->osr_temp = reg_val; in bmp388_attr_set_oversampling()
555 uint8_t reg_val; in bmp388_device_ctrl() local
559 reg_val = BMP388_PWR_CTRL_MODE_NORMAL; in bmp388_device_ctrl()
562 reg_val = BMP388_PWR_CTRL_MODE_SLEEP; in bmp388_device_ctrl()
571 reg_val) < 0) { in bmp388_device_ctrl()

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