pll_div (reference) in projects: Zephyr-Core-2.7.6

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/Zephyr-Core-2.7.6/drivers/clock_control/
D	clock_stm32l0_l1.c	`26 #define pll_div(v) z_pll_div(v) macro 34 pllinit->PLLDiv = pll_div(STM32_PLL_DIVISOR); in config_pll_init()`
D	clock_stm32g0.c	`24 #define pll_div(v) z_pll_div(v) macro 35 pllinit->PLLM = pll_div(STM32_PLL_M_DIVISOR); in config_pll_init()`

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
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Zephyr-Core-3.5.0
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