| /Zephyr-Core-2.7.6/soc/arm/atmel_sam/common/ |
| D | soc_sam4l_gpio.c | 15 uint32_t mask, uint32_t flags) in configure_common_attr() argument
20 gpio->IERC = mask; in configure_common_attr()
24 gpio->PUERS = mask; in configure_common_attr()
26 gpio->PUERC = mask; in configure_common_attr()
31 gpio->PDERS = mask; in configure_common_attr()
33 gpio->PDERC = mask; in configure_common_attr()
38 gpio->ODMERS = mask; in configure_common_attr()
40 gpio->ODMERC = mask; in configure_common_attr()
45 uint32_t mask, uint32_t flags) in configure_input_attr() argument
52 gpio->GFERC = mask; in configure_input_attr()
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| D | soc_gpio.c | 24 static void configure_common_attr(Pio *pio, uint32_t mask, uint32_t flags) in configure_common_attr() argument
27 pio->PIO_IDR = mask; in configure_common_attr()
31 pio->PIO_PUER = mask; in configure_common_attr()
33 pio->PIO_PUDR = mask; in configure_common_attr()
40 pio->PIO_PPDER = mask; in configure_common_attr()
42 pio->PIO_PPDDR = mask; in configure_common_attr()
48 pio->PIO_MDER = mask; in configure_common_attr()
50 pio->PIO_MDDR = mask; in configure_common_attr()
54 static void configure_input_attr(Pio *pio, uint32_t mask, uint32_t flags) in configure_input_attr() argument
61 pio->PIO_IFSCER = mask; in configure_input_attr()
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| D | soc_sam4l_pm.c | 42 uint32_t mask; in soc_pmc_peripheral_enable() local
54 mask = *(&PM->CPUMASK + bus_id); in soc_pmc_peripheral_enable()
55 mask |= (1U << per_idx); in soc_pmc_peripheral_enable()
60 *(&PM->CPUMASK + bus_id) = mask; in soc_pmc_peripheral_enable()
68 uint32_t mask; in soc_pmc_peripheral_disable() local
80 mask = *(&PM->CPUMASK + bus_id); in soc_pmc_peripheral_disable()
81 mask &= ~(1U << per_idx); in soc_pmc_peripheral_disable()
86 *(&PM->CPUMASK + bus_id) = mask; in soc_pmc_peripheral_disable()
94 uint32_t mask; in soc_pmc_peripheral_is_enabled() local
106 mask = *(&PM->CPUMASK + bus_id); in soc_pmc_peripheral_is_enabled()
[all …]
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| D | soc_gpio.h | 86 uint32_t mask; /** pin(s) bit mask */ member
143 pin->regs->OVRS = pin->mask; in soc_gpio_set()
145 pin->regs->PIO_SODR = pin->mask; in soc_gpio_set()
161 pin->regs->OVRC = pin->mask; in soc_gpio_clear()
163 pin->regs->PIO_CODR = pin->mask; in soc_gpio_clear()
179 return pin->regs->PVR & pin->mask; in soc_gpio_get()
181 return pin->regs->PIO_PDSR & pin->mask; in soc_gpio_get()
209 pin->regs->STERS = pin->mask; in soc_gpio_debounce_length_set()
211 pin->regs->STERC = pin->mask; in soc_gpio_debounce_length_set()
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| /Zephyr-Core-2.7.6/soc/xtensa/esp32s2/include/ |
| D | _soc_inthandlers.h | 120 static inline int _xtensa_handle_one_int1(unsigned int mask) in _xtensa_handle_one_int1() argument
124 if (mask & 0x7f) { in _xtensa_handle_one_int1()
125 if (mask & 0x7) { in _xtensa_handle_one_int1()
126 if (mask & BIT(0)) { in _xtensa_handle_one_int1()
127 mask = BIT(0); in _xtensa_handle_one_int1()
131 if (mask & BIT(1)) { in _xtensa_handle_one_int1()
132 mask = BIT(1); in _xtensa_handle_one_int1()
136 if (mask & BIT(2)) { in _xtensa_handle_one_int1()
137 mask = BIT(2); in _xtensa_handle_one_int1()
142 if (mask & 0x18) { in _xtensa_handle_one_int1()
[all …]
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| /Zephyr-Core-2.7.6/soc/xtensa/esp32/include/ |
| D | _soc_inthandlers.h | 114 static inline int _xtensa_handle_one_int1(unsigned int mask) in _xtensa_handle_one_int1() argument
118 if (mask & 0x7f) { in _xtensa_handle_one_int1()
119 if (mask & 0x7) { in _xtensa_handle_one_int1()
120 if (mask & BIT(0)) { in _xtensa_handle_one_int1()
121 mask = BIT(0); in _xtensa_handle_one_int1()
125 if (mask & BIT(1)) { in _xtensa_handle_one_int1()
126 mask = BIT(1); in _xtensa_handle_one_int1()
130 if (mask & BIT(2)) { in _xtensa_handle_one_int1()
131 mask = BIT(2); in _xtensa_handle_one_int1()
136 if (mask & 0x18) { in _xtensa_handle_one_int1()
[all …]
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| /Zephyr-Core-2.7.6/soc/xtensa/intel_adsp/cavs_v15/include/ |
| D | _soc_inthandlers.h | 81 static inline int _xtensa_handle_one_int1(unsigned int mask) in _xtensa_handle_one_int1() argument
85 if (mask & 0x3) { in _xtensa_handle_one_int1()
86 if (mask & BIT(0)) { in _xtensa_handle_one_int1()
87 mask = BIT(0); in _xtensa_handle_one_int1()
91 if (mask & BIT(1)) { in _xtensa_handle_one_int1()
92 mask = BIT(1); in _xtensa_handle_one_int1()
97 if (mask & BIT(2)) { in _xtensa_handle_one_int1()
98 mask = BIT(2); in _xtensa_handle_one_int1()
102 if (mask & BIT(3)) { in _xtensa_handle_one_int1()
103 mask = BIT(3); in _xtensa_handle_one_int1()
[all …]
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| /Zephyr-Core-2.7.6/soc/xtensa/intel_adsp/cavs_v20/include/ |
| D | _soc_inthandlers.h | 85 static inline int _xtensa_handle_one_int1(unsigned int mask) in _xtensa_handle_one_int1() argument
89 if (mask & 0x3) { in _xtensa_handle_one_int1()
90 if (mask & BIT(0)) { in _xtensa_handle_one_int1()
91 mask = BIT(0); in _xtensa_handle_one_int1()
95 if (mask & BIT(1)) { in _xtensa_handle_one_int1()
96 mask = BIT(1); in _xtensa_handle_one_int1()
101 if (mask & BIT(2)) { in _xtensa_handle_one_int1()
102 mask = BIT(2); in _xtensa_handle_one_int1()
106 if (mask & BIT(3)) { in _xtensa_handle_one_int1()
107 mask = BIT(3); in _xtensa_handle_one_int1()
[all …]
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| /Zephyr-Core-2.7.6/soc/xtensa/intel_adsp/cavs_v18/include/ |
| D | _soc_inthandlers.h | 85 static inline int _xtensa_handle_one_int1(unsigned int mask) in _xtensa_handle_one_int1() argument
89 if (mask & 0x3) { in _xtensa_handle_one_int1()
90 if (mask & BIT(0)) { in _xtensa_handle_one_int1()
91 mask = BIT(0); in _xtensa_handle_one_int1()
95 if (mask & BIT(1)) { in _xtensa_handle_one_int1()
96 mask = BIT(1); in _xtensa_handle_one_int1()
101 if (mask & BIT(2)) { in _xtensa_handle_one_int1()
102 mask = BIT(2); in _xtensa_handle_one_int1()
106 if (mask & BIT(3)) { in _xtensa_handle_one_int1()
107 mask = BIT(3); in _xtensa_handle_one_int1()
[all …]
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| /Zephyr-Core-2.7.6/soc/xtensa/intel_adsp/cavs_v25/include/ |
| D | _soc_inthandlers.h | 85 static inline int _xtensa_handle_one_int1(unsigned int mask) in _xtensa_handle_one_int1() argument
89 if (mask & 0x3) { in _xtensa_handle_one_int1()
90 if (mask & BIT(0)) { in _xtensa_handle_one_int1()
91 mask = BIT(0); in _xtensa_handle_one_int1()
95 if (mask & BIT(1)) { in _xtensa_handle_one_int1()
96 mask = BIT(1); in _xtensa_handle_one_int1()
101 if (mask & BIT(2)) { in _xtensa_handle_one_int1()
102 mask = BIT(2); in _xtensa_handle_one_int1()
106 if (mask & BIT(3)) { in _xtensa_handle_one_int1()
107 mask = BIT(3); in _xtensa_handle_one_int1()
[all …]
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| /Zephyr-Core-2.7.6/drivers/gpio/ |
| D | gpio_sam.c | 41 static int gpio_sam_port_configure(const struct device *dev, uint32_t mask, in gpio_sam_port_configure() argument
56 pio->PIO_IDR = mask; in gpio_sam_port_configure()
58 pio->PIO_PUDR = mask; in gpio_sam_port_configure()
64 pio->PIO_PPDDR = mask; in gpio_sam_port_configure()
67 pio->PIO_PER = mask; in gpio_sam_port_configure()
69 pio->PIO_ODR = mask; in gpio_sam_port_configure()
78 pio->PIO_SODR = mask; in gpio_sam_port_configure()
82 pio->PIO_CODR = mask; in gpio_sam_port_configure()
85 pio->PIO_OER = mask; in gpio_sam_port_configure()
87 pio->PIO_OWER = mask; in gpio_sam_port_configure()
[all …]
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| D | gpio_sam4l.c | 43 uint32_t mask, in gpio_sam_port_configure() argument
55 gpio->IERC = mask; in gpio_sam_port_configure()
56 gpio->PUERC = mask; in gpio_sam_port_configure()
57 gpio->PDERC = mask; in gpio_sam_port_configure()
58 gpio->GPERS = mask; in gpio_sam_port_configure()
59 gpio->ODERC = mask; in gpio_sam_port_configure()
60 gpio->STERC = mask; in gpio_sam_port_configure()
69 gpio->STERS = mask; in gpio_sam_port_configure()
73 gpio->OVRS = mask; in gpio_sam_port_configure()
76 gpio->OVRC = mask; in gpio_sam_port_configure()
[all …]
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| D | gpio_mmio32.c | 38 if ((config->mask & (1 << pin)) == 0) { in gpio_mmio32_config()
57 *reg = (*reg & (config->mask & ~(1 << pin))); in gpio_mmio32_config()
70 *value = *config->reg & config->mask; in gpio_mmio32_port_get_raw()
76 uint32_t mask, in gpio_mmio32_port_set_masked_raw() argument
84 mask &= config->mask; in gpio_mmio32_port_set_masked_raw()
85 value &= mask; in gpio_mmio32_port_set_masked_raw()
89 *reg = (*reg & ~mask) | value; in gpio_mmio32_port_set_masked_raw()
96 uint32_t mask) in gpio_mmio32_port_set_bits_raw() argument
103 mask &= config->mask; in gpio_mmio32_port_set_bits_raw()
107 *reg = (*reg | mask); in gpio_mmio32_port_set_bits_raw()
[all …]
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| D | gpio_npcx.c | 95 uint32_t mask = BIT(pin); in gpio_npcx_config() local
114 inst->PDIR &= ~mask; in gpio_npcx_config()
127 inst->PTYPE |= mask; in gpio_npcx_config()
129 inst->PTYPE &= ~mask; in gpio_npcx_config()
133 inst->PPUD &= ~mask; in gpio_npcx_config()
134 inst->PPULL |= mask; in gpio_npcx_config()
136 inst->PPUD |= mask; in gpio_npcx_config()
137 inst->PPULL |= mask; in gpio_npcx_config()
140 inst->PPULL &= ~mask; in gpio_npcx_config()
145 inst->PDOUT |= mask; in gpio_npcx_config()
[all …]
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| D | gpio_mchp_xec_v2.c | 74 static inline void xec_mask_write32(uintptr_t addr, uint32_t mask, uint32_t val) in xec_mask_write32() argument
76 uint32_t r = (sys_read32(addr) & ~mask) | (val & mask); in xec_mask_write32()
99 uint32_t mask = 0U; in gpio_xec_configure() local
118 mask |= MCHP_GPIO_CTRL_DIR_MASK; in gpio_xec_configure()
119 mask |= MCHP_GPIO_CTRL_INPAD_DIS_MASK; in gpio_xec_configure()
120 mask |= MCHP_GPIO_CTRL_PWRG_MASK; in gpio_xec_configure()
126 mask |= MCHP_GPIO_CTRL_PUD_MASK; in gpio_xec_configure()
137 mask |= MCHP_GPIO_CTRL_BUFT_MASK; in gpio_xec_configure()
150 mask |= MCHP_GPIO_CTRL_AOD_MASK; in gpio_xec_configure()
164 xec_mask_write32(pcr1_addr, mask, pcr1); in gpio_xec_configure()
[all …]
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| D | gpio_cmsdk_ahb.c | 58 uint32_t mask, in gpio_cmsdk_ahb_port_set_masked_raw() argument
63 cfg->port->dataout = (cfg->port->dataout & ~mask) | (mask & value); in gpio_cmsdk_ahb_port_set_masked_raw()
69 uint32_t mask) in gpio_cmsdk_ahb_port_set_bits_raw() argument
73 cfg->port->dataout |= mask; in gpio_cmsdk_ahb_port_set_bits_raw()
79 uint32_t mask) in gpio_cmsdk_ahb_port_clear_bits_raw() argument
83 cfg->port->dataout &= ~mask; in gpio_cmsdk_ahb_port_clear_bits_raw()
89 uint32_t mask) in gpio_cmsdk_ahb_port_toggle_bits() argument
93 cfg->port->dataout ^= mask; in gpio_cmsdk_ahb_port_toggle_bits()
98 static int cmsdk_ahb_gpio_config(const struct device *dev, uint32_t mask, in cmsdk_ahb_gpio_config() argument
123 gpio_cmsdk_ahb_port_set_bits_raw(dev, mask); in cmsdk_ahb_gpio_config()
[all …]
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| /Zephyr-Core-2.7.6/soc/xtensa/sample_controller/include/ |
| D | _soc_inthandlers.h | 83 static inline int _xtensa_handle_one_int0(unsigned int mask) in _xtensa_handle_one_int0() argument
88 static inline int _xtensa_handle_one_int1(unsigned int mask) in _xtensa_handle_one_int1() argument
90 if (mask & 0x7f) { in _xtensa_handle_one_int1()
91 if (mask & 0x7) { in _xtensa_handle_one_int1()
92 if (mask & (1 << 0)) { in _xtensa_handle_one_int1()
98 if (mask & (1 << 1)) { in _xtensa_handle_one_int1()
104 if (mask & (1 << 2)) { in _xtensa_handle_one_int1()
111 if (mask & 0x18) { in _xtensa_handle_one_int1()
112 if (mask & (1 << 3)) { in _xtensa_handle_one_int1()
118 if (mask & (1 << 4)) { in _xtensa_handle_one_int1()
[all …]
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| /Zephyr-Core-2.7.6/drivers/hwinfo/ |
| D | hwinfo_mcux_rcm.c | 24 uint32_t mask = 0; in hwinfo_mcux_rcm_xlate_reset_sources() local
28 mask |= RESET_LOW_POWER_WAKE; in hwinfo_mcux_rcm_xlate_reset_sources()
33 mask |= RESET_BROWNOUT; in hwinfo_mcux_rcm_xlate_reset_sources()
38 mask |= RESET_CLOCK; in hwinfo_mcux_rcm_xlate_reset_sources()
44 mask |= RESET_PLL; in hwinfo_mcux_rcm_xlate_reset_sources()
49 mask |= RESET_WATCHDOG; in hwinfo_mcux_rcm_xlate_reset_sources()
53 mask |= RESET_PIN; in hwinfo_mcux_rcm_xlate_reset_sources()
57 mask |= RESET_POR; in hwinfo_mcux_rcm_xlate_reset_sources()
62 mask |= RESET_DEBUG; in hwinfo_mcux_rcm_xlate_reset_sources()
67 mask |= RESET_CPU_LOCKUP; in hwinfo_mcux_rcm_xlate_reset_sources()
[all …]
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| /Zephyr-Core-2.7.6/soc/xtensa/intel_s1000/include/ |
| D | _soc_inthandlers.h | 80 static inline int _xtensa_handle_one_int1(unsigned int mask) in _xtensa_handle_one_int1() argument
82 if (mask & 0x3) { in _xtensa_handle_one_int1()
83 if (mask & (1 << 0)) { in _xtensa_handle_one_int1()
89 if (mask & (1 << 1)) { in _xtensa_handle_one_int1()
96 if (mask & (1 << 2)) { in _xtensa_handle_one_int1()
102 if (mask & (1 << 3)) { in _xtensa_handle_one_int1()
112 static inline int _xtensa_handle_one_int2(unsigned int mask) in _xtensa_handle_one_int2() argument
114 if (mask & 0x30) { in _xtensa_handle_one_int2()
115 if (mask & (1 << 4)) { in _xtensa_handle_one_int2()
121 if (mask & (1 << 5)) { in _xtensa_handle_one_int2()
[all …]
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| /Zephyr-Core-2.7.6/soc/xtensa/nxp_adsp/imx8/include/ |
| D | _soc_inthandlers.h | 86 static inline int _xtensa_handle_one_int1(unsigned int mask) in _xtensa_handle_one_int1() argument
90 if (mask & BIT(8)) { in _xtensa_handle_one_int1()
91 mask = BIT(8); in _xtensa_handle_one_int1()
98 return mask; in _xtensa_handle_one_int1()
101 static inline int _xtensa_handle_one_int2(unsigned int mask) in _xtensa_handle_one_int2() argument
106 mask &= XCHAL_INTLEVEL2_MASK; in _xtensa_handle_one_int2()
108 if (mask & BIT(i)) { in _xtensa_handle_one_int2()
109 mask = BIT(i); in _xtensa_handle_one_int2()
116 return mask; in _xtensa_handle_one_int2()
119 static inline int _xtensa_handle_one_int3(unsigned int mask) in _xtensa_handle_one_int3() argument
[all …]
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| /Zephyr-Core-2.7.6/include/sys/ |
| D | atomic.h | 147 atomic_val_t mask = ATOMIC_MASK(bit); in atomic_test_and_clear_bit() local
150 old = atomic_and(ATOMIC_ELEM(target, bit), ~mask); in atomic_test_and_clear_bit()
152 return (old & mask) != 0; in atomic_test_and_clear_bit()
168 atomic_val_t mask = ATOMIC_MASK(bit); in atomic_test_and_set_bit() local
171 old = atomic_or(ATOMIC_ELEM(target, bit), mask); in atomic_test_and_set_bit()
173 return (old & mask) != 0; in atomic_test_and_set_bit()
189 atomic_val_t mask = ATOMIC_MASK(bit); in atomic_clear_bit() local
191 (void)atomic_and(ATOMIC_ELEM(target, bit), ~mask); in atomic_clear_bit()
207 atomic_val_t mask = ATOMIC_MASK(bit); in atomic_set_bit() local
209 (void)atomic_or(ATOMIC_ELEM(target, bit), mask); in atomic_set_bit()
[all …]
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| /Zephyr-Core-2.7.6/dts/arm/nuvoton/npcx/ |
| D | npcx-miwus-int-map.dtsi | 17 group-mask = <0x02>;
22 group-mask = <0x04>;
33 group-mask = <0x01>;
38 group-mask = <0x02>;
43 group-mask = <0x04>;
48 group-mask = <0x08>;
53 group-mask = <0x10>;
58 group-mask = <0x20>;
63 group-mask = <0x40>;
68 group-mask = <0x80>;
[all …]
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| /Zephyr-Core-2.7.6/drivers/pinmux/ |
| D | pinmux_b91.c | 117 uint8_t mask = 0; in pinmux_b91_set_pull_up() local
122 mask = 0xfc; in pinmux_b91_set_pull_up()
125 mask = 0xf3; in pinmux_b91_set_pull_up()
128 mask = 0xcf; in pinmux_b91_set_pull_up()
131 mask = 0x3f; in pinmux_b91_set_pull_up()
136 analog_write_reg8(analog_reg, (analog_read_reg8(analog_reg) & mask) | val); in pinmux_b91_set_pull_up()
154 uint8_t mask = 0; in pinmux_b91_set() local
163 mask = (uint8_t)~(BIT(offset) | BIT(offset + 1)); in pinmux_b91_set()
169 reg_pin_mux(pin) = (reg_pin_mux(pin) & mask) | (func << offset); in pinmux_b91_set()
179 uint8_t mask = 0u; in pinmux_b91_get() local
[all …]
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| /Zephyr-Core-2.7.6/dts/arm/nuvoton/npcx/npcx9/ |
| D | npcx9-miwus-int-map.dtsi | 21 group-mask = <0x01>;
26 group-mask = <0x08>;
31 group-mask = <0x10>;
36 group-mask = <0x20>;
41 group-mask = <0x40>;
46 group-mask = <0x80>;
57 group-mask = <0x20>;
62 group-mask = <0x40>;
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| /Zephyr-Core-2.7.6/drivers/interrupt_controller/ |
| D | intc_sam0_eic.c | 105 uint32_t mask; in sam0_eic_acquire() local
117 mask = BIT(line_index); in sam0_eic_acquire()
178 EIC->INTFLAG.reg = mask; in sam0_eic_acquire()
212 uint32_t mask; in sam0_eic_release() local
223 mask = BIT(line_index); in sam0_eic_release()
247 EIC->INTENCLR.reg = mask; in sam0_eic_release()
248 EIC->INTFLAG.reg = mask; in sam0_eic_release()
259 uint32_t mask; in sam0_eic_enable_interrupt() local
271 mask = BIT(line_index); in sam0_eic_enable_interrupt()
272 EIC->INTFLAG.reg = mask; in sam0_eic_enable_interrupt()
[all …]
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