1 /* 2 * Copyright (c) 2019, MADMACHINE LIMITED 3 * 4 * refer to hal_nxp board file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 */ 8 9 #ifndef __FLEXSPI_NOR_CONFIG__ 10 #define __FLEXSPI_NOR_CONFIG__ 11 12 #include <zephyr/types.h> 13 #include "fsl_common.h" 14 15 #define FLEXSPI_CFG_BLK_TAG (0x42464346UL) 16 #define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) 17 #define FLEXSPI_CFG_BLK_SIZE (512) 18 19 #define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 20 21 #define CMD_INDEX_READ 0 22 #define CMD_INDEX_READSTATUS 1 23 #define CMD_INDEX_WRITEENABLE 2 24 #define CMD_INDEX_WRITE 4 25 26 #define CMD_LUT_SEQ_IDX_READ 0 27 #define CMD_LUT_SEQ_IDX_READSTATUS 1 28 #define CMD_LUT_SEQ_IDX_WRITEENABLE 3 29 #define CMD_LUT_SEQ_IDX_WRITE 9 30 31 #define CMD_SDR 0x01 32 #define CMD_DDR 0x21 33 #define RADDR_SDR 0x02 34 #define RADDR_DDR 0x22 35 #define CADDR_SDR 0x03 36 #define CADDR_DDR 0x23 37 #define MODE1_SDR 0x04 38 #define MODE1_DDR 0x24 39 #define MODE2_SDR 0x05 40 #define MODE2_DDR 0x25 41 #define MODE4_SDR 0x06 42 #define MODE4_DDR 0x26 43 #define MODE8_SDR 0x07 44 #define MODE8_DDR 0x27 45 #define WRITE_SDR 0x08 46 #define WRITE_DDR 0x28 47 #define READ_SDR 0x09 48 #define READ_DDR 0x29 49 #define LEARN_SDR 0x0A 50 #define LEARN_DDR 0x2A 51 #define DATSZ_SDR 0x0B 52 #define DATSZ_DDR 0x2B 53 #define DUMMY_SDR 0x0C 54 #define DUMMY_DDR 0x2C 55 #define DUMMY_RWDS_SDR 0x0D 56 #define DUMMY_RWDS_DDR 0x2D 57 #define JMP_ON_CS 0x1F 58 #define STOP 0 59 60 #define FLEXSPI_1PAD 0 61 #define FLEXSPI_2PAD 1 62 #define FLEXSPI_4PAD 2 63 #define FLEXSPI_8PAD 3 64 65 #define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ 66 (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | \ 67 FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ 68 FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) 69 70 /* For flexspi_mem_config.serialClkFreq */ 71 #if defined(CONFIG_SOC_MIMXRT1011) 72 enum { 73 kFlexSpiSerialClk_30MHz = 1, 74 kFlexSpiSerialClk_50MHz = 2, 75 kFlexSpiSerialClk_60MHz = 3, 76 kFlexSpiSerialClk_75MHz = 4, 77 kFlexSpiSerialClk_80MHz = 5, 78 kFlexSpiSerialClk_100MHz = 6, 79 kFlexSpiSerialClk_120MHz = 7, 80 kFlexSpiSerialClk_133MHz = 8, 81 }; 82 #elif defined(CONFIG_SOC_MIMXRT1015) || defined(CONFIG_SOC_MIMXRT1021) || \ 83 defined(CONFIG_SOC_MIMXRT1024) 84 enum { 85 kFlexSpiSerialClk_30MHz = 1, 86 kFlexSpiSerialClk_50MHz = 2, 87 kFlexSpiSerialClk_60MHz = 3, 88 kFlexSpiSerialClk_75MHz = 4, 89 kFlexSpiSerialClk_80MHz = 5, 90 kFlexSpiSerialClk_100MHz = 6, 91 kFlexSpiSerialClk_133MHz = 7, 92 }; 93 #elif defined(CONFIG_SOC_MIMXRT1051) || defined(CONFIG_SOC_MIMXRT1052) 94 enum { 95 kFlexSpiSerialClk_30MHz = 1, 96 kFlexSpiSerialClk_50MHz = 2, 97 kFlexSpiSerialClk_60MHz = 3, 98 kFlexSpiSerialClk_75MHz = 4, 99 kFlexSpiSerialClk_80MHz = 5, 100 kFlexSpiSerialClk_100MHz = 6, 101 kFlexSpiSerialClk_133MHz = 7, 102 kFlexSpiSerialClk_166MHz = 8, 103 kFlexSpiSerialClk_200MHz = 9, 104 }; 105 #elif defined(CONFIG_SOC_MIMXRT1061) || defined(CONFIG_SOC_MIMXRT1062) || \ 106 defined(CONFIG_SOC_MIMXRT1062) || defined(CONFIG_SOC_MIMXRT1064) 107 enum { 108 kFlexSpiSerialClk_30MHz = 1, 109 kFlexSpiSerialClk_50MHz = 2, 110 kFlexSpiSerialClk_60MHz = 3, 111 kFlexSpiSerialClk_75MHz = 4, 112 kFlexSpiSerialClk_80MHz = 5, 113 kFlexSpiSerialClk_100MHz = 6, 114 kFlexSpiSerialClk_120MHz = 7, 115 kFlexSpiSerialClk_133MHz = 8, 116 kFlexSpiSerialClk_166MHz = 9, 117 }; 118 #else 119 #error "kFlexSpiSerialClk is not defined for this SoC" 120 #endif 121 122 /* For flexspi_mem_config.controllerMiscOption */ 123 enum { 124 kFlexSpiClk_SDR, 125 kFlexSpiClk_DDR, 126 }; 127 128 /* For flexspi_mem_config.readSampleClkSrc */ 129 enum { 130 kFlexSPIReadSampleClk_LoopbackInternally = 0, 131 kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, 132 kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, 133 kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, 134 }; 135 136 /* For flexspi_mem_config.controllerMiscOption */ 137 enum { 138 kFlexSpiMiscOffset_DiffClkEnable = 0, 139 kFlexSpiMiscOffset_Ck2Enable = 1, 140 kFlexSpiMiscOffset_ParallelEnable = 2, 141 kFlexSpiMiscOffset_WordAddressableEnable = 3, 142 kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, 143 kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, 144 kFlexSpiMiscOffset_DdrModeEnable = 6, 145 }; 146 147 /* For flexspi_mem_config.deviceType */ 148 enum { 149 kFlexSpiDeviceType_SerialNOR = 1, 150 kFlexSpiDeviceType_SerialNAND = 2, 151 kFlexSpiDeviceType_SerialRAM = 3, 152 kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, 153 kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, 154 }; 155 156 /* For flexspi_mem_config.sflashPadType */ 157 enum { 158 kSerialFlash_1Pad = 1, 159 kSerialFlash_2Pads = 2, 160 kSerialFlash_4Pads = 4, 161 kSerialFlash_8Pads = 8, 162 }; 163 164 enum { 165 kDeviceConfigCmdType_Generic, 166 kDeviceConfigCmdType_QuadEnable, 167 kDeviceConfigCmdType_Spi2Xpi, 168 kDeviceConfigCmdType_Xpi2Spi, 169 kDeviceConfigCmdType_Spi2NoCmd, 170 kDeviceConfigCmdType_Reset, 171 }; 172 173 struct flexspi_lut_seq_t { 174 uint8_t seqNum; 175 uint8_t seqId; 176 uint16_t reserved; 177 }; 178 179 struct flexspi_mem_config_t { 180 uint32_t tag; 181 uint32_t version; 182 uint32_t reserved0; 183 uint8_t readSampleClkSrc; 184 uint8_t csHoldTime; 185 uint8_t csSetupTime; 186 uint8_t columnAddressWidth; 187 188 uint8_t deviceModeCfgEnable; 189 uint8_t deviceModeType; 190 191 uint16_t waitTimeCfgCommands; 192 193 struct flexspi_lut_seq_t deviceModeSeq; 194 195 uint32_t deviceModeArg; 196 uint8_t configCmdEnable; 197 uint8_t configModeType[3]; 198 struct flexspi_lut_seq_t configCmdSeqs[3]; 199 uint32_t reserved1; 200 uint32_t configCmdArgs[3]; 201 uint32_t reserved2; 202 uint32_t controllerMiscOption; 203 204 uint8_t deviceType; 205 uint8_t sflashPadType; 206 uint8_t serialClkFreq; 207 208 uint8_t lutCustomSeqEnable; 209 210 uint32_t reserved3[2]; 211 uint32_t sflashA1Size; 212 uint32_t sflashA2Size; 213 uint32_t sflashB1Size; 214 uint32_t sflashB2Size; 215 uint32_t csPadSettingOverride; 216 uint32_t sclkPadSettingOverride; 217 uint32_t dataPadSettingOverride; 218 uint32_t dqsPadSettingOverride; 219 uint32_t timeoutInMs; 220 uint32_t commandInterval; 221 uint16_t dataValidTime[2]; 222 uint16_t busyOffset; 223 uint16_t busyBitPolarity; 224 225 uint32_t lookupTable[64]; 226 struct flexspi_lut_seq_t lutCustomSeq[12]; 227 uint32_t reserved4[4]; 228 }; 229 230 #define NOR_CMD_INDEX_READ CMD_INDEX_READ 231 #define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS 232 #define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE 233 #define NOR_CMD_INDEX_ERASESECTOR 3 234 #define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE 235 #define NOR_CMD_INDEX_CHIPERASE 5 236 #define NOR_CMD_INDEX_DUMMY 6 237 #define NOR_CMD_INDEX_ERASEBLOCK 7 238 239 #define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ 240 #define NOR_CMD_LUT_SEQ_IDX_READSTATUS CMD_LUT_SEQ_IDX_READSTATUS 241 #define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI 2 242 #define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE CMD_LUT_SEQ_IDX_WRITEENABLE 243 #define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI 4 244 #define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 245 #define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 246 #define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM CMD_LUT_SEQ_IDX_WRITE 247 #define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 248 #define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 249 #define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD 14 250 #define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD 15 251 252 struct flexspi_nor_config_t { 253 struct flexspi_mem_config_t memConfig; 254 uint32_t pageSize; 255 uint32_t sectorSize; 256 uint8_t ipcmdSerialClkFreq; 257 uint8_t isUniformBlockSize; 258 uint8_t reserved0[2]; 259 uint8_t serialNorType; 260 uint8_t needExitNoCmdMode; 261 uint8_t halfClkForNonReadCmd; 262 uint8_t needRestoreNoCmdMode; 263 uint32_t blockSize; 264 uint32_t reserve2[11]; 265 }; 266 267 #ifdef __cplusplus 268 extern "C" { 269 #endif 270 271 #ifdef __cplusplus 272 } 273 #endif 274 #endif 275
