| /Zephyr-Core-2.7.6/samples/subsys/ipc/rpmsg_multi_instance/ |
| D | README.rst | 38 Master [no 1] core received a message: 1
39 Master [no 2] core received a message: 1
40 Master [no 1] core received a message: 3
41 Master [no 2] core received a message: 3
42 Master [no 1] core received a message: 5
43 Master [no 2] core received a message: 5
45 Master [no 1] core received a message: 99
47 Master [no 2] core received a message: 99
59 Remote [no 1] core received a message: 0
60 Remote [no 2] core received a message: 0
[all …]
|
| /Zephyr-Core-2.7.6/soc/xtensa/nxp_adsp/imx8/include/ |
| D | _soc_inthandlers.h | 23 #error core-isa.h interrupt level does not match dispatcher!
26 #error core-isa.h interrupt level does not match dispatcher!
29 #error core-isa.h interrupt level does not match dispatcher!
32 #error core-isa.h interrupt level does not match dispatcher!
35 #error core-isa.h interrupt level does not match dispatcher!
38 #error core-isa.h interrupt level does not match dispatcher!
41 #error core-isa.h interrupt level does not match dispatcher!
44 #error core-isa.h interrupt level does not match dispatcher!
47 #error core-isa.h interrupt level does not match dispatcher!
50 #error core-isa.h interrupt level does not match dispatcher!
[all …]
|
| /Zephyr-Core-2.7.6/soc/xtensa/esp32s2/include/ |
| D | _soc_inthandlers.h | 24 #error core-isa.h interrupt level does not match dispatcher!
27 #error core-isa.h interrupt level does not match dispatcher!
30 #error core-isa.h interrupt level does not match dispatcher!
33 #error core-isa.h interrupt level does not match dispatcher!
36 #error core-isa.h interrupt level does not match dispatcher!
39 #error core-isa.h interrupt level does not match dispatcher!
42 #error core-isa.h interrupt level does not match dispatcher!
45 #error core-isa.h interrupt level does not match dispatcher!
48 #error core-isa.h interrupt level does not match dispatcher!
51 #error core-isa.h interrupt level does not match dispatcher!
[all …]
|
| /Zephyr-Core-2.7.6/soc/xtensa/esp32/include/ |
| D | _soc_inthandlers.h | 18 #error core-isa.h interrupt level does not match dispatcher!
21 #error core-isa.h interrupt level does not match dispatcher!
24 #error core-isa.h interrupt level does not match dispatcher!
27 #error core-isa.h interrupt level does not match dispatcher!
30 #error core-isa.h interrupt level does not match dispatcher!
33 #error core-isa.h interrupt level does not match dispatcher!
36 #error core-isa.h interrupt level does not match dispatcher!
39 #error core-isa.h interrupt level does not match dispatcher!
42 #error core-isa.h interrupt level does not match dispatcher!
45 #error core-isa.h interrupt level does not match dispatcher!
[all …]
|
| /Zephyr-Core-2.7.6/soc/xtensa/sample_controller/include/ |
| D | _soc_inthandlers.h | 17 #error core-isa.h interrupt level does not match dispatcher!
20 #error core-isa.h interrupt level does not match dispatcher!
23 #error core-isa.h interrupt level does not match dispatcher!
26 #error core-isa.h interrupt level does not match dispatcher!
29 #error core-isa.h interrupt level does not match dispatcher!
32 #error core-isa.h interrupt level does not match dispatcher!
35 #error core-isa.h interrupt level does not match dispatcher!
38 #error core-isa.h interrupt level does not match dispatcher!
41 #error core-isa.h interrupt level does not match dispatcher!
44 #error core-isa.h interrupt level does not match dispatcher!
[all …]
|
| /Zephyr-Core-2.7.6/soc/xtensa/intel_s1000/include/ |
| D | _soc_inthandlers.h | 17 #error core-isa.h interrupt level does not match dispatcher!
20 #error core-isa.h interrupt level does not match dispatcher!
23 #error core-isa.h interrupt level does not match dispatcher!
26 #error core-isa.h interrupt level does not match dispatcher!
29 #error core-isa.h interrupt level does not match dispatcher!
32 #error core-isa.h interrupt level does not match dispatcher!
35 #error core-isa.h interrupt level does not match dispatcher!
38 #error core-isa.h interrupt level does not match dispatcher!
41 #error core-isa.h interrupt level does not match dispatcher!
44 #error core-isa.h interrupt level does not match dispatcher!
[all …]
|
| /Zephyr-Core-2.7.6/soc/xtensa/intel_adsp/cavs_v15/include/ |
| D | _soc_inthandlers.h | 18 #error core-isa.h interrupt level does not match dispatcher!
21 #error core-isa.h interrupt level does not match dispatcher!
24 #error core-isa.h interrupt level does not match dispatcher!
27 #error core-isa.h interrupt level does not match dispatcher!
30 #error core-isa.h interrupt level does not match dispatcher!
33 #error core-isa.h interrupt level does not match dispatcher!
36 #error core-isa.h interrupt level does not match dispatcher!
39 #error core-isa.h interrupt level does not match dispatcher!
42 #error core-isa.h interrupt level does not match dispatcher!
45 #error core-isa.h interrupt level does not match dispatcher!
[all …]
|
| /Zephyr-Core-2.7.6/soc/xtensa/intel_adsp/cavs_v20/include/ |
| D | _soc_inthandlers.h | 22 #error core-isa.h interrupt level does not match dispatcher!
25 #error core-isa.h interrupt level does not match dispatcher!
28 #error core-isa.h interrupt level does not match dispatcher!
31 #error core-isa.h interrupt level does not match dispatcher!
34 #error core-isa.h interrupt level does not match dispatcher!
37 #error core-isa.h interrupt level does not match dispatcher!
40 #error core-isa.h interrupt level does not match dispatcher!
43 #error core-isa.h interrupt level does not match dispatcher!
46 #error core-isa.h interrupt level does not match dispatcher!
49 #error core-isa.h interrupt level does not match dispatcher!
[all …]
|
| /Zephyr-Core-2.7.6/soc/xtensa/intel_adsp/cavs_v18/include/ |
| D | _soc_inthandlers.h | 22 #error core-isa.h interrupt level does not match dispatcher!
25 #error core-isa.h interrupt level does not match dispatcher!
28 #error core-isa.h interrupt level does not match dispatcher!
31 #error core-isa.h interrupt level does not match dispatcher!
34 #error core-isa.h interrupt level does not match dispatcher!
37 #error core-isa.h interrupt level does not match dispatcher!
40 #error core-isa.h interrupt level does not match dispatcher!
43 #error core-isa.h interrupt level does not match dispatcher!
46 #error core-isa.h interrupt level does not match dispatcher!
49 #error core-isa.h interrupt level does not match dispatcher!
[all …]
|
| /Zephyr-Core-2.7.6/soc/xtensa/intel_adsp/cavs_v25/include/ |
| D | _soc_inthandlers.h | 22 #error core-isa.h interrupt level does not match dispatcher!
25 #error core-isa.h interrupt level does not match dispatcher!
28 #error core-isa.h interrupt level does not match dispatcher!
31 #error core-isa.h interrupt level does not match dispatcher!
34 #error core-isa.h interrupt level does not match dispatcher!
37 #error core-isa.h interrupt level does not match dispatcher!
40 #error core-isa.h interrupt level does not match dispatcher!
43 #error core-isa.h interrupt level does not match dispatcher!
46 #error core-isa.h interrupt level does not match dispatcher!
49 #error core-isa.h interrupt level does not match dispatcher!
[all …]
|
| /Zephyr-Core-2.7.6/samples/subsys/ipc/rpmsg_service/ |
| D | README.rst | 56 Master core received a message: 1
57 Master core received a message: 3
58 Master core received a message: 5
60 Master core received a message: 99
70 Remote core received a message: 0
71 Remote core received a message: 2
72 Remote core received a message: 4
74 Remote core received a message: 98
99 and network core images, the following messages (one for master and one for
108 Master core received a message: 1
[all …]
|
| /Zephyr-Core-2.7.6/samples/subsys/ipc/openamp/ |
| D | README.rst | 62 Master core received a message: 1
63 Master core received a message: 3
64 Master core received a message: 5
66 Master core received a message: 99
76 Remote core received a message: 0
77 Remote core received a message: 2
78 Remote core received a message: 4
80 Remote core received a message: 98
|
| /Zephyr-Core-2.7.6/include/arch/arc/ |
| D | arch_inlines.h | 20 uint32_t core; in arch_curr_cpu() local
22 core = z_arc_v2_core_id(); in arch_curr_cpu()
24 return &_kernel.cpus[core]; in arch_curr_cpu()
|
| /Zephyr-Core-2.7.6/soc/xtensa/intel_adsp/common/ |
| D | soc_mp.c | 248 IDC[start_rec.cpu].core[i].tfc = BIT(31); in z_mp_entry()
356 IDC[curr_cpu].core[cpu_num].ietc = ietc; in arch_start_cpu()
357 IDC[curr_cpu].core[cpu_num].itc = IDC_MSG_POWER_UP | IPC_IDCITC_BUSY; in arch_start_cpu()
391 IDC[curr].core[c].itc = BIT(31); in arch_sched_ipi()
422 IDC[prid()].core[i].tfc = BIT(31); in idc_isr()
445 for (int core = 0; core < CONFIG_MP_NUM_CPUS; core++) { in soc_idc_init() local
448 IDC[core].busy_int |= coremask; in soc_idc_init()
449 IDC[core].done_int &= ~coremask; in soc_idc_init()
454 CAVS_INTCTRL[core].l2.clear = CAVS_L2_IDC; in soc_idc_init()
461 IDC[i].core[j].tfc = BIT(31); in soc_idc_init()
|
| /Zephyr-Core-2.7.6/boards/arm/thingy53_nrf5340/doc/ |
| D | index.rst | 13 The nRF5340 is a dual-core SoC based on the Arm® Cortex®-M33 architecture, with:
15 * a full-featured Arm Cortex-M33F core with DSP instructions, FPU, and
17 the **application core**
18 * a secondary Arm Cortex-M33 core, with a reduced feature set, running at
19 a fixed 64 MHz, referred to as the **network core**.
22 core on the nRF5340 SoC. The nrf5340dk_nrf5340_cpunet build target provides
23 support for the network core on the nRF5340 SoC.
|
| /Zephyr-Core-2.7.6/soc/arc/snps_arc_hsdk/ |
| D | soc.c | 19 uint32_t core; in arc_hsdk_init() local
23 core = z_arc_v2_core_id(); in arc_hsdk_init()
30 z_arc_connect_idu_set_dest(i, 1 << core); in arc_hsdk_init()
|
| /Zephyr-Core-2.7.6/soc/arc/snps_nsim/ |
| D | soc.c | 24 uint32_t core; in arc_nsim_init() local
28 core = z_arc_v2_core_id(); in arc_nsim_init()
35 z_arc_connect_idu_set_dest(i, 1 << core); in arc_nsim_init()
|
| /Zephyr-Core-2.7.6/boards/arc/hsdk/support/ |
| D | openocd.cfg | 30 # Contains quad-core ARC HS38.
38 # CHIPNAME will be used to choose core family (600, 700 or EM). As far as
54 # ARC HS38 core 2
65 # Enable L2 cache support for core 2.
69 # ARC HS38 core 3
80 # Enable L2 cache support for core 3.
84 # ARC HS38 core 4
96 # Enable L2 cache support for core 4.
100 # ARC HS38 core 1
111 # Enable L2 cache support for core 1.
|
| D | openocd-2-cores.cfg | 30 # Contains quad-core ARC HS38.
38 # CHIPNAME will be used to choose core family (600, 700 or EM). As far as
54 # ARC HS38 core 2
65 # Enable L2 cache support for core 2.
69 # ARC HS38 core 1
80 # Enable L2 cache support for core 1.
|
| /Zephyr-Core-2.7.6/soc/arm/nxp_lpc/lpc54xxx/ |
| D | Kconfig.soc | 42 bool "Enable LPC54114 Cortex-M0 second core"
45 Driver for second core startup
49 string "Binary image of second core's code"
52 used by the second core.
56 hex "Address the second core will boot at"
59 This is the address the second core will boot from. Additionally this
|
| /Zephyr-Core-2.7.6/drivers/sensor/ams_iAQcore/ |
| D | Kconfig | 1 # iAQ-core Digital VOC sensor configuration options
7 bool "iAQ-core Digital VOC sensor"
10 Enable driver for iAQ-core Digital VOC sensor.
|
| /Zephyr-Core-2.7.6/boards/arm/udoo_neo_full_m4/doc/ |
| D | index.rst | 11 composed of one ARM |reg| Cortex-A9 core running up to 1 GHz and one Cortex-M4
12 core running up to 227 MHz for high CPU performance and real-time response.
13 Zephyr was ported to run on the Cortex-M4 core only. In a future release, it
14 will also communicate with the Cortex-A9 core (running Linux) via OpenAMP.
26 - MCIMX6X MCU with a single Cortex-A9 (1 GHz) core and single Cortex-M4 (227 MHz) core
161 on the board with the on-chip PLL to generate core clock.
162 PLL settings for M4 core are set via code running on the A9 core.
167 The MCIMX6X SoC has six UARTs. UART5 is configured for the M4 core and the
168 remaining are used by the A9 core or not used.
173 The M4 core does not have a flash memory and is not provided a clock
[all …]
|
| /Zephyr-Core-2.7.6/boards/arm/nrf5340dk_nrf5340/doc/ |
| D | index.rst | 12 The nRF5340 is a dual-core SoC based on the Arm® Cortex®-M33 architecture, with:
14 * a full-featured Arm Cortex-M33F core with DSP instructions, FPU, and
16 the **application core**
17 * a secondary Arm Cortex-M33 core, with a reduced feature set, running at
18 a fixed 64 MHz, referred to as the **network core**.
21 core on the nRF5340 SoC. The nrf5340dk_nrf5340_cpunet build target provides
22 support for the network core on the nRF5340 SoC.
162 - Implementation Defined Attribution Unit (`IDAU`_) on the application core.
172 nRF5340 application core supports the Armv8-M Security Extension.
176 nRF5340 network core does not support the Armv8-M Security Extension.
[all …]
|
| /Zephyr-Core-2.7.6/soc/arm/nxp_lpc/lpc55xxx/ |
| D | Kconfig.soc | 84 bool "Enable LPC55xxx's second core"
87 Driver for second core startup
91 string "Binary image of second core's code"
94 used by the second core.
104 hex "Address the second core will boot at"
107 This is the address the second core will boot from.
|
| /Zephyr-Core-2.7.6/samples/subsys/ipc/ipm_mcux/ |
| D | README.rst | 9 Some NXP microcontrollers from LPC family are dual-core, this
11 processor core to the other.
14 - :ref:`lpcxpresso54114`, two core processors (Cortex-M4F and Cortex-M0+)
15 - :ref:`lpcxpresso55s69`, two core processors (dual Cortex-M33)
|
