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/Zephyr-Core-2.7.6/dts/riscv/starfive/
Dstarfive_jh7100_clk.dtsi9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <125000000>;
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
17 clock-frequency = <125000000>;
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
23 clock-frequency = <100000000>;
27 #clock-cells = <0>;
[all …]
/Zephyr-Core-2.7.6/dts/arm/nxp/
Dnxp_ke1xf.dtsi8 #include <dt-bindings/clock/kinetis_pcc.h>
9 #include <dt-bindings/clock/kinetis_scg.h>
127 #clock-cells = <1>;
130 compatible = "fixed-clock";
132 #clock-cells = <0>;
136 compatible = "fixed-clock";
137 clock-frequency = <8000000>;
138 #clock-cells = <0>;
142 compatible = "fixed-clock";
143 clock-frequency = <48000000>;
[all …]
Dnxp_kv5x.dtsi8 #include <dt-bindings/clock/kinetis_sim.h>
9 #include <dt-bindings/clock/kinetis_mcg.h>
40 #clock-cells = <3>;
43 compatible = "fixed-factor-clock";
45 clock-div = <1>;
46 #clock-cells = <0>;
50 compatible = "fixed-factor-clock";
52 clock-div = <2>;
53 #clock-cells = <0>;
57 compatible = "fixed-factor-clock";
[all …]
Dnxp_kw40z.dtsi5 #include <dt-bindings/clock/kinetis_sim.h>
6 #include <dt-bindings/clock/kinetis_mcg.h>
32 mcg: clock-controller@40064000 {
36 #clock-cells = <1>;
39 osc: clock-controller@40065000 {
48 clock-frequency = <32768>;
55 #clock-cells = <3>;
58 compatible = "fixed-factor-clock";
60 clock-div = <1>;
61 #clock-cells = <0>;
[all …]
Dnxp_k8x.dtsi8 #include <dt-bindings/clock/kinetis_mcg.h>
9 #include <dt-bindings/clock/kinetis_sim.h>
45 #clock-cells = <3>;
48 compatible = "fixed-factor-clock";
50 clock-div = <1>;
51 #clock-cells = <0>;
55 compatible = "fixed-factor-clock";
57 clock-div = <2>;
58 #clock-cells = <0>;
62 compatible = "fixed-factor-clock";
[all …]
Dnxp_kw41z.dtsi9 #include <dt-bindings/clock/kinetis_sim.h>
10 #include <dt-bindings/clock/kinetis_mcg.h>
37 mcg: clock-controller@40064000 {
41 #clock-cells = <1>;
44 osc: clock-controller@40065000 {
54 clock-frequency = <32768>;
63 #clock-cells = <3>;
66 compatible = "fixed-factor-clock";
68 clock-div = <1>;
69 #clock-cells = <0>;
[all …]
/Zephyr-Core-2.7.6/dts/arm/atmel/
Dsamd20.dtsi23 clock-names = "GCLK", "PM";
32 clock-names = "GCLK", "PM";
41 clock-names = "GCLK", "PM";
49 clock-names = "GCLK", "PM";
55 clock-names = "GCLK", "PM";
61 clock-names = "GCLK", "PM";
67 clock-names = "GCLK", "PM";
73 clock-names = "GCLK", "PM";
79 clock-names = "GCLK", "PM";
85 clock-names = "GCLK", "PM";
[all …]
Dsamd21.dtsi38 clock-names = "GCLK", "PM";
47 clock-names = "GCLK", "PM";
59 clock-names = "GCLK", "PM";
71 clock-names = "GCLK", "PM";
82 clock-names = "GCLK", "PM";
88 clock-names = "GCLK", "PM";
94 clock-names = "GCLK", "PM";
100 clock-names = "GCLK", "PM";
106 clock-names = "GCLK", "PM";
112 clock-names = "GCLK", "PM";
[all …]
Dsamr21.dtsi58 clock-names = "GCLK", "PM";
70 clock-names = "GCLK", "PM";
82 clock-names = "GCLK", "PM";
93 clock-names = "GCLK", "PM";
99 clock-names = "GCLK", "PM";
105 clock-names = "GCLK", "PM";
111 clock-names = "GCLK", "PM";
117 clock-names = "GCLK", "PM";
123 clock-names = "GCLK", "PM";
129 clock-names = "GCLK", "PM";
[all …]
Dsamd5x.dtsi95 #clock-cells = <2>;
101 #clock-cells = <1>;
173 clock-names = "GCLK", "MCLK";
183 clock-names = "GCLK", "MCLK";
193 clock-names = "GCLK", "MCLK";
203 clock-names = "GCLK", "MCLK";
213 clock-names = "GCLK", "MCLK";
223 clock-names = "GCLK", "MCLK";
233 clock-names = "GCLK", "MCLK";
243 clock-names = "GCLK", "MCLK";
[all …]
/Zephyr-Core-2.7.6/soc/nios2/nios2f-zephyr/cpu/
Dghrd_timing.sdc7 # JTAG Signal Constraints constrain the TCK port, assuming a 10MHz JTAG clock and 3ns delays
9 set_input_delay -clock altera_reserved_tck -clock_fall -max 5 [get_ports altera_reserved_tdi]
10 set_input_delay -clock altera_reserved_tck -clock_fall -max 5 [get_ports altera_reserved_tms]
11 set_output_delay -clock altera_reserved_tck 5 [get_ports altera_reserved_tdo]
22 set_output_delay -clock {clk_50 } -rise -min 11 [get_ports {qspi_io[*]}]
23 set_output_delay -clock {clk_50 } -rise -min 11 [get_ports {qspi_clk}]
24 set_output_delay -clock {clk_50 } -rise -min 11 [get_ports {qspi_csn}]
25 set_input_delay -clock {clk_50 } -rise -min 10 [get_ports {qspi_io[*]}]
/Zephyr-Core-2.7.6/dts/riscv/
Driscv32-litex-vexriscv.dtsi22 clock-frequency = <100000000>;
174 clock-outputs {
177 clk0: clock-controller@0 {
178 #clock-cells = <1>;
181 clock-output-names = "CLK_0";
182 litex,clock-frequency = <100000000>;
183 litex,clock-phase = <0>;
184 litex,clock-duty-num = <1>;
185 litex,clock-duty-den = <2>;
186 litex,clock-margin = <1>;
[all …]
/Zephyr-Core-2.7.6/soc/arm/nxp_kinetis/k8x/
DKconfig.soc45 int "Freescale K8x core clock divider"
48 This option specifies the divide value for the K8x processor core clock
49 from the system clock.
52 int "Freescale K8x bus clock divider"
55 This option specifies the divide value for the K8x bus clock from the
56 system clock.
59 int "Freescale K8x FlexBus clock divider"
62 This option specifies the divide value for the K8x FlexBus clock from the
63 system clock.
66 int "Freescale K8x flash clock divider"
[all …]
/Zephyr-Core-2.7.6/boards/riscv/hifive1/
Dhifive1.dts48 clock-frequency = <16000000>;
52 clock-frequency = <16000000>;
57 clock-frequency = <16000000>;
72 clock-frequency = <16000000>;
77 clock-frequency = <16000000>;
82 clock-frequency = <16000000>;
87 clock-frequency = <16000000>;
92 clock-frequency = <16000000>;
/Zephyr-Core-2.7.6/drivers/clock_control/
DKconfig.litex1 # LiteX SoC Builder clock control driver
7 bool "LiteX MMCM clock control"
10 This option enables LiteX clock control driver.
11 It gives ability to change clock parameters
13 clock outputs
/Zephyr-Core-2.7.6/soc/arm/atmel_sam/sam3x/
DKconfig.soc27 bool "Atmel SAM3 to use external crystal oscillator for slow clock"
30 oscillator to drive the slow clock. Note that this
35 The slow clock will be driven by the internal fast
39 bool "Atmel SAM3 to use external crystal oscillator for main clock"
41 The main clock is being used to drive the PLL, and
42 thus driving the processor clock.
45 to drive the main clock. Note that this adds about
59 The processor clock is (MAINCK * (MULA + 1) / DIVA).
65 PLL is running at 7 times of main clock.
72 The processor clock is (MAINCK * (MULA + 1) / DIVA).
[all …]
/Zephyr-Core-2.7.6/soc/arm/atmel_sam/sam4e/
DKconfig.soc29 bool "Atmel SAM4E to use external crystal oscillator for slow clock"
32 oscillator to drive the slow clock. Note that this
37 The slow clock will be driven by the internal fast
41 bool "Atmel SAM4E to use external crystal oscillator for main clock"
43 The main clock is being used to drive the PLL, and
44 thus driving the processor clock.
47 to drive the main clock. Note that this adds about
61 The processor clock is (MAINCK * (MULA + 1) / DIVA).
67 PLL is running at 10 times of main clock.
74 The processor clock is (MAINCK * (MULA + 1) / DIVA).
[all …]
/Zephyr-Core-2.7.6/dts/arm/st/u5/
Dstm32u5.dtsi9 #include <dt-bindings/clock/stm32_clock.h>
39 #clock-cells = <0>;
40 compatible = "st,stm32-hse-clock";
45 #clock-cells = <0>;
46 compatible = "fixed-clock";
47 clock-frequency = <DT_FREQ_M(16)>;
52 #clock-cells = <0>;
53 compatible = "st,stm32u5-msi-clock";
59 #clock-cells = <0>;
60 compatible = "fixed-clock";
[all …]
/Zephyr-Core-2.7.6/drivers/i2s/
DKconfig.stm3227 Enable it if I2S clock should be provided by the PLLI2S.
28 If not enabled the clock will be provided by HSI/HSE.
31 int "Division factor for PLLI2S VCO input clock"
36 Division factor for the audio PLL (PLLI2S) VCO input clock.
43 int "Multiplier factor for PLLI2S VCO output clock"
48 Multiply factor for the audio PLL (PLLI2S) VCO output clock.
54 int "Division factor for I2S clock"
59 Division factor for the I2S clock.
60 PLLR factor should be selected to ensure that the I2S clock
/Zephyr-Core-2.7.6/soc/arm/atmel_sam/sam4s/
DKconfig.soc49 bool "Atmel SAM4S to use external crystal oscillator for slow clock"
52 oscillator to drive the slow clock. Note that this
57 The slow clock will be driven by the internal fast
61 bool "Atmel SAM4S to use external crystal oscillator for main clock"
63 The main clock is being used to drive the PLL, and
64 thus driving the processor clock.
67 to drive the main clock. Note that this adds about
81 The processor clock is (MAINCK * (MULA + 1) / DIVA).
87 PLL is running at 10 times of main clock.
94 The processor clock is (MAINCK * (MULA + 1) / DIVA).
[all …]
/Zephyr-Core-2.7.6/boards/riscv/hifive1_revb/
Dhifive1_revb.dts80 clock-frequency = <16000000>;
86 clock-frequency = <16000000>;
91 clock-frequency = <16000000>;
106 clock-frequency = <16000000>;
111 clock-frequency = <16000000>;
116 clock-frequency = <16000000>;
121 clock-frequency = <16000000>;
126 clock-frequency = <16000000>;
133 clock-frequency = <100000>;
/Zephyr-Core-2.7.6/dts/arm/st/l0/
Dstm32l0.dtsi9 #include <dt-bindings/clock/stm32_clock.h>
37 #clock-cells = <0>;
38 compatible = "st,stm32-hse-clock";
43 #clock-cells = <0>;
44 compatible = "fixed-clock";
45 clock-frequency = <DT_FREQ_M(16)>;
50 #clock-cells = <0>;
51 compatible = "st,stm32l0-msi-clock";
57 #clock-cells = <0>;
58 compatible = "fixed-clock";
[all …]
/Zephyr-Core-2.7.6/soc/arm/atmel_sam0/common/
DKconfig.samd5x10 startup. This can then be selected as the main clock source
14 prompt "Main clock source"
16 Selects the clock that the main clocks, such as the CPU
17 clock and AHB clock, will be derived from.
/Zephyr-Core-2.7.6/soc/x86/apollo_lake/doc/
Dsupported_features.txt19 configuration. The UARTs are fed a master clock which is fed into a PLL which
20 in turn outputs the baud master clock. The PLL is controlled by a per-UART
30 The resulting baud master clock frequency is ``(n/m)`` * master.
32 Typically, the master clock is 100MHz, and the firmware by default sets
34 results in the de-facto standard 1.8432MHz master clock and a max baud rate
36 Zephyr what the resulting master clock is.
49 clock-frequency = <7372800>;
56 and ``clock-frequency`` (the resulting baud master clock). The meaning of
/Zephyr-Core-2.7.6/samples/drivers/clock_control_litex/
DREADME.rst9 This sample is providing an overview of LiteX clock control driver capabilities.
16 * Optional: clock output signals redirected to output pins for testing
20 …guration of the driver, including default settings for clock outputs, is held in Device Tree clock…
23 :start-at: clk0: clock-controller@0 {
27 :start-at: clk1: clock-controller@1 {
31 :start-at: clock0: clock@82005000 {
34 This configuration defines 2 clock outputs: ``clk0`` and ``clk1`` with default frequency set to 100…
36 **Important note:** ``reg`` properties in ``clk0`` and ``clk1`` nodes reference the clock output n…
46 | To change clock parameter it is needed to cast a pointer to structure ``litex_clk_setup`` onto ``…
66 … offset) can be acquired with function ``clock_control_get_status()`` and clock output frequency o…
[all …]

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