| /Zephyr-Core-2.7.6/tests/net/ptp/clock/src/ |
| D | main.c | 307 const struct device *clk; in iface_cb() local
314 clk = net_eth_get_ptp_clock(iface); in iface_cb()
315 if (!clk) { in iface_cb()
414 const struct device *clk; in test_ptp_clock_interfaces() local
418 clk = net_eth_get_ptp_clock(eth_interfaces[idx]); in test_ptp_clock_interfaces()
419 zassert_not_null(clk, "Clock not found for interface %p\n", in test_ptp_clock_interfaces()
423 clk = net_eth_get_ptp_clock(eth_interfaces[idx]); in test_ptp_clock_interfaces()
424 zassert_not_null(clk, "Clock not found for interface %p\n", in test_ptp_clock_interfaces()
427 clk = net_eth_get_ptp_clock(eth_interfaces[non_ptp_interface]); in test_ptp_clock_interfaces()
428 zassert_is_null(clk, "Clock found for interface %p\n", in test_ptp_clock_interfaces()
[all …]
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| /Zephyr-Core-2.7.6/drivers/clock_control/ |
| D | clock_control_rcar_cpg_mssr.c | 141 struct rcar_cpg_clk *clk = (struct rcar_cpg_clk *)sys; in cpg_mssr_blocking_start() local
144 if (clk->domain == CPG_MOD) { in cpg_mssr_blocking_start()
145 ret = cpg_rmstp_clock_endisable(dev, clk->module, true); in cpg_mssr_blocking_start()
146 } else if (clk->domain == CPG_CORE) { in cpg_mssr_blocking_start()
147 ret = cpg_core_clock_endisable(dev, clk->module, clk->rate, in cpg_mssr_blocking_start()
157 struct rcar_cpg_clk *clk = (struct rcar_cpg_clk *)sys; in cpg_mssr_stop() local
160 if (clk->domain == CPG_MOD) { in cpg_mssr_stop()
161 ret = cpg_rmstp_clock_endisable(dev, clk->module, false); in cpg_mssr_stop()
162 } else if (clk->domain == CPG_CORE) { in cpg_mssr_stop()
163 ret = cpg_core_clock_endisable(dev, clk->module, 0, false); in cpg_mssr_stop()
[all …]
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| D | clock_control_litex.h | 86 #define CLKOUT_EXIST(N) DT_NODE_HAS_STATUS(DT_NODELABEL(clk##N), okay)
87 #define CLKOUT_ID(N) DT_REG_ADDR(DT_NODELABEL(clk##N))
88 #define CLKOUT_FREQ(N) DT_PROP(DT_NODELABEL(clk##N), \
90 #define CLKOUT_PHASE(N) DT_PROP(DT_NODELABEL(clk##N), \
92 #define CLKOUT_DUTY_NUM(N) DT_PROP(DT_NODELABEL(clk##N), \
94 #define CLKOUT_DUTY_DEN(N) DT_PROP(DT_NODELABEL(clk##N), \
96 #define CLKOUT_MARGIN(N) DT_PROP(DT_NODELABEL(clk##N), \
98 #define CLKOUT_MARGIN_EXP(N) DT_PROP(DT_NODELABEL(clk##N), \
|
| D | clock_control_esp32.c | 35 uint32_t clk; member
73 [0] = { .clk = DPORT_PERIP_CLK_EN_REG, .rst = DPORT_PERIP_RST_EN_REG },
74 [1] = { .clk = DPORT_PERI_CLK_EN_REG, .rst = DPORT_PERI_RST_EN_REG },
75 [2] = { .clk = DPORT_WIFI_CLK_EN_REG, .rst = DPORT_CORE_RST_EN_REG }
264 esp32_set_mask32(BIT(offset), clock_control_regs[bank].clk); in clock_control_esp32_on()
278 esp32_clear_mask32(BIT(offset), clock_control_regs[bank].clk); in clock_control_esp32_off()
290 if (DPORT_GET_PERI_REG_MASK(clock_control_regs[bank].clk, BIT(offset))) { in clock_control_esp32_get_status()
|
| /Zephyr-Core-2.7.6/boards/arm/sam4l_ek/ |
| D | sam4l_ek.dts | 66 clk = <4>;
73 std-clk-slew-lim = <0>;
74 std-clk-strength-low = "0.5";
78 hs-clk-slew-lim = <0>;
79 hs-clk-strength-high = "0.5";
80 hs-clk-strength-low = "0.5";
|
| /Zephyr-Core-2.7.6/soc/arm/nxp_kinetis/kwx/ |
| D | soc_kw4xz.c | 19 #define CLOCK_NODEID(clk) \ argument
20 DT_CHILD(DT_INST(0, nxp_kinetis_sim), clk)
22 #define CLOCK_DIVIDER(clk) \ argument
23 DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1
|
| D | soc_kw2xd.c | 29 #define CLOCK_NODEID(clk) \ argument
30 DT_CHILD(DT_INST(0, nxp_kinetis_sim), clk)
32 #define CLOCK_DIVIDER(clk) \ argument
33 DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1
|
| /Zephyr-Core-2.7.6/soc/arm/nxp_kinetis/k2x/ |
| D | soc.c | 30 #define CLOCK_NODEID(clk) \ argument
31 DT_CHILD(DT_INST(0, nxp_kinetis_sim), clk)
33 #define CLOCK_DIVIDER(clk) \ argument
34 DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1
|
| /Zephyr-Core-2.7.6/dts/arm/st/f2/ |
| D | stm32f207.dtsi | 16 clock-names = "stmmaceth", "mac-clk-tx",
17 "mac-clk-rx", "mac-clk-ptp";
|
| /Zephyr-Core-2.7.6/soc/arm/nxp_kinetis/kl2x/ |
| D | soc.c | 17 #define CLOCK_NODEID(clk) \ argument
18 DT_CHILD(DT_INST(0, nxp_kinetis_sim), clk)
20 #define CLOCK_DIVIDER(clk) \ argument
21 DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1
|
| /Zephyr-Core-2.7.6/soc/arm/nxp_kinetis/kv5x/ |
| D | soc.c | 21 #define CLOCK_NODEID(clk) \ argument
22 DT_CHILD(DT_INST(0, nxp_kinetis_sim), clk)
24 #define CLOCK_DIVIDER(clk) \ argument
25 DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1
|
| /Zephyr-Core-2.7.6/dts/arm/st/f4/ |
| D | stm32f407.dtsi | 16 clock-names = "stmmaceth", "mac-clk-tx",
17 "mac-clk-rx", "mac-clk-ptp";
|
| /Zephyr-Core-2.7.6/subsys/net/l2/ethernet/gptp/ |
| D | gptp_user_api.c | 57 const struct device *clk; in gptp_event_capture() local
66 clk = net_eth_get_ptp_clock(GPTP_PORT_IFACE(port)); in gptp_event_capture()
67 if (clk) { in gptp_event_capture()
68 ptp_clock_get(clk, slave_time); in gptp_event_capture()
|
| /Zephyr-Core-2.7.6/soc/arm/nxp_kinetis/k8x/ |
| D | soc.c | 25 #define CLOCK_NODEID(clk) \ argument
26 DT_CHILD(DT_INST(0, nxp_kinetis_sim), clk)
28 #define CLOCK_DIVIDER(clk) \ argument
29 DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1
|
| /Zephyr-Core-2.7.6/drivers/memc/ |
| D | memc_stm32.c | 29 const struct device *clk; in memc_stm32_init() local
40 clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE); in memc_stm32_init()
42 r = clock_control_on(clk, (clock_control_subsys_t *)&config->pclken); in memc_stm32_init()
|
| /Zephyr-Core-2.7.6/soc/arm/nxp_kinetis/k6x/ |
| D | soc.c | 30 #define CLOCK_NODEID(clk) \ argument
31 DT_CHILD(DT_INST(0, nxp_kinetis_sim), clk)
33 #define CLOCK_DIVIDER(clk) \ argument
34 DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1
|
| /Zephyr-Core-2.7.6/drivers/timer/ |
| D | rcar_cmt_timer.c | 77 const struct device *clk; in sys_clock_driver_init() local
82 clk = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)); in sys_clock_driver_init()
83 if (clk == NULL) { in sys_clock_driver_init()
87 ret = clock_control_on(clk, (clock_control_subsys_t *)&mod_clk); in sys_clock_driver_init()
|
| /Zephyr-Core-2.7.6/dts/arm/cypress/ |
| D | psoc6-pinctrl.dtsi | 15 DT_CYPRESS_HSIOM(spi0, clk, 0, 4, act_8, drive-push-pull);
21 DT_CYPRESS_HSIOM(spi1, clk, 10, 2, act_8, drive-push-pull);
28 DT_CYPRESS_HSIOM(spi2, clk, 9, 2, act_8, drive-push-pull);
35 DT_CYPRESS_HSIOM(spi3, clk, 6, 2, act_8, drive-push-pull);
42 DT_CYPRESS_HSIOM(spi4, clk, 7, 2, act_8, drive-push-pull);
49 DT_CYPRESS_HSIOM(spi4, clk, 8, 2, act_8, drive-push-pull);
56 DT_CYPRESS_HSIOM(spi5, clk, 5, 2, act_8, drive-push-pull);
63 DT_CYPRESS_HSIOM(spi5, clk, 11, 2, act_8, drive-push-pull);
70 DT_CYPRESS_HSIOM(spi6, clk, 6, 6, act_8, drive-push-pull);
74 DT_CYPRESS_HSIOM(spi6, clk, 12, 2, act_8, drive-push-pull);
[all …]
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| /Zephyr-Core-2.7.6/soc/arm/st_stm32/common/ |
| D | stm32_backup_sram.c | 28 const struct device *clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE); in stm32_backup_sram_init() local
30 ret = clock_control_on(clk, (clock_control_subsys_t *)&config->pclken); in stm32_backup_sram_init()
|
| /Zephyr-Core-2.7.6/drivers/pwm/ |
| D | pwm_stm32.c | 120 const struct device *clk; in get_tim_clk() local
123 clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE); in get_tim_clk()
125 r = clock_control_get_rate(clk, (clock_control_subsys_t *)pclken, in get_tim_clk()
285 const struct device *clk; in pwm_stm32_init() local
289 clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE); in pwm_stm32_init()
291 r = clock_control_on(clk, (clock_control_subsys_t *)&cfg->pclken); in pwm_stm32_init()
|
| /Zephyr-Core-2.7.6/dts/arm/nxp/ |
| D | nxp_rt6xx_common.dtsi | 283 clk-divider = <1>;
292 clk-divider = <1>;
319 clk-divider = <1>;
320 clk-source = <0>;
335 clk-source = <1>;
348 clk-source = <1>;
361 clk-source = <1>;
374 clk-source = <1>;
387 clk-source = <1>;
|
| D | nxp_lpc55S6x_common.dtsi | 285 clk-divider = <1>;
294 clk-divider = <8>;
295 clk-source = <0>;
319 clk-source = <3>;
332 clk-source = <3>;
345 clk-source = <3>;
358 clk-source = <3>;
371 clk-source = <3>;
|
| /Zephyr-Core-2.7.6/drivers/counter/ |
| D | timer_dtmr_cmsdk_apb.c | 147 const struct device *clk = in dtmr_cmsdk_apb_init() local
151 clock_control_on(clk, (clock_control_subsys_t *) &cfg->dtimer_cc_as); in dtmr_cmsdk_apb_init()
152 clock_control_on(clk, (clock_control_subsys_t *) &cfg->dtimer_cc_ss); in dtmr_cmsdk_apb_init()
153 clock_control_on(clk, (clock_control_subsys_t *) &cfg->dtimer_cc_dss); in dtmr_cmsdk_apb_init()
|
| D | timer_tmr_cmsdk_apb.c | 150 const struct device *clk = in tmr_cmsdk_apb_init() local
154 clock_control_on(clk, (clock_control_subsys_t *) &cfg->timer_cc_as); in tmr_cmsdk_apb_init()
155 clock_control_on(clk, (clock_control_subsys_t *) &cfg->timer_cc_ss); in tmr_cmsdk_apb_init()
156 clock_control_on(clk, (clock_control_subsys_t *) &cfg->timer_cc_dss); in tmr_cmsdk_apb_init()
|
| /Zephyr-Core-2.7.6/dts/arm/st/f7/ |
| D | stm32f767.dtsi | 76 clock-names = "stmmaceth", "mac-clk-tx",
77 "mac-clk-rx", "mac-clk-ptp";
|
