1 /*
2  * Copyright (c) 2018 Foundries.io Ltd
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #ifndef SOC_RISCV32_OPENISA_RV32M1_SOC_ZERO_RISCY_H_
8 #define SOC_RISCV32_OPENISA_RV32M1_SOC_ZERO_RISCY_H_
9 
10 /* Control and Status Registers (CSRs) available for ZERO_RISCY. */
11 #define ZERO_RISCY_MSTATUS 0x300U
12 #define ZERO_RISCY_MTVEC   0x305U
13 #define ZERO_RISCY_MEPC    0x341U
14 #define ZERO_RISCY_MCAUSE  0x342U
15 #define ZERO_RISCY_PCCR0   0x780U
16 #define ZERO_RISCY_PCCR1   0x781U
17 #define ZERO_RISCY_PCCR2   0x782U
18 #define ZERO_RISCY_PCCR3   0x783U
19 #define ZERO_RISCY_PCCR4   0x784U
20 #define ZERO_RISCY_PCCR5   0x785U
21 #define ZERO_RISCY_PCCR6   0x786U
22 #define ZERO_RISCY_PCCR7   0x787U
23 #define ZERO_RISCY_PCCR8   0x788U
24 #define ZERO_RISCY_PCCR9   0x789U
25 #define ZERO_RISCY_PCCR10  0x78AU
26 #define ZERO_RISCY_PCCR    0x78BU
27 #define ZERO_RISCY_PCER    0x7A0U
28 #define ZERO_RISCY_PCMR    0x7A1U
29 #define ZERO_RISCY_MHARTID 0xF14U
30 
31 /*
32  * Map from SoC-specific configuration to generic Zephyr macros.
33  *
34  * These are expected by the code in arch/, and must be provided for
35  * the kernel to work (or even build at all).
36  *
37  * Some of these may also apply to ZERO-RISCY; needs investigation.
38  */
39 
40 /*
41  * Exception code mask. Use of the bottom five bits is a subset of
42  * what the standard allocates (which is XLEN-1 bits).
43  */
44 #define SOC_MCAUSE_EXP_MASK 0x1F
45 /*
46  * Assembler instruction to exit from interrupt in machine mode.
47  * The name "ERET" is a leftover from pre-v1.10 privileged ISA specs.
48  * The "mret" mnemonic works properly with the Pulpino toolchain;
49  * YMMV if using a generic toolchain.
50  */
51 #define SOC_ERET mret
52 /* The ecall exception number. This is a standard value. */
53 #define SOC_MCAUSE_ECALL_EXP 11
54 
55 #endif /* SOC_RISCV32_OPENISA_RV32M1_SOC_ZERO_RISCY_H_ */
56