Searched refs:XUARTPS_SR_OFFSET (Results 1 – 1 of 1) sorted by relevance
57 #define XUARTPS_SR_OFFSET 0x002CU /**< Channel Status [14:0] */ macro371 uint32_t reg_val = sys_read32(reg_base + XUARTPS_SR_OFFSET); in uart_xlnx_ps_poll_in()400 while ((sys_read32(reg_base + XUARTPS_SR_OFFSET) & XUARTPS_SR_TXFULL) != 0) { in uart_xlnx_ps_poll_out()895 (sys_read32(reg_base + XUARTPS_SR_OFFSET) & XUARTPS_SR_TXFULL) == 0) { in uart_xlnx_ps_fifo_fill()917 (sys_read32(reg_base + XUARTPS_SR_OFFSET) & XUARTPS_SR_RXEMPTY) == 0) { in uart_xlnx_ps_fifo_read()935 if ((sys_read32(reg_base + XUARTPS_SR_OFFSET) & (XUARTPS_SR_TTRIG | XUARTPS_SR_TXEMPTY)) != in uart_xlnx_ps_irq_tx_enable()969 uint32_t reg_val = sys_read32(reg_base + XUARTPS_SR_OFFSET); in uart_xlnx_ps_irq_tx_ready()988 uint32_t reg_val = sys_read32(reg_base + XUARTPS_SR_OFFSET); in uart_xlnx_ps_irq_tx_complete()1004 if ((sys_read32(reg_base + XUARTPS_SR_OFFSET) & XUARTPS_SR_RXEMPTY) == 0) { in uart_xlnx_ps_irq_rx_enable()1037 uint32_t reg_val = sys_read32(reg_base + XUARTPS_SR_OFFSET); in uart_xlnx_ps_irq_rx_ready()
