1 /*
2 * Copyright (c) 2017 Intel Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 /*
8 * This driver is written based on the Altera's
9 * Nios-II QSPI Controller HAL driver.
10 */
11
12 #include <kernel.h>
13 #include <device.h>
14 #include <string.h>
15 #include <drivers/flash.h>
16 #include <errno.h>
17 #include <init.h>
18 #include <soc.h>
19 #include <sys/util.h>
20 #include "flash_priv.h"
21 #include "altera_generic_quad_spi_controller2_regs.h"
22 #include "altera_generic_quad_spi_controller2.h"
23
24 #define LOG_LEVEL CONFIG_FLASH_LOG_LEVEL
25 #include <logging/log.h>
26 LOG_MODULE_REGISTER(flash_nios2_qspi);
27
28 /*
29 * Remove the following macros once the Altera HAL
30 * supports the QSPI Controller v2 IP.
31 */
32 #define ALTERA_QSPI_CONTROLLER2_FLAG_STATUS_REG 0x0000001C
33 #define FLAG_STATUS_PROTECTION_ERROR (1 << 1)
34 #define FLAG_STATUS_PROGRAM_SUSPENDED (1 << 2)
35 #define FLAG_STATUS_PROGRAM_ERROR (1 << 4)
36 #define FLAG_STATUS_ERASE_ERROR (1 << 5)
37 #define FLAG_STATUS_ERASE_SUSPENDED (1 << 6)
38 #define FLAG_STATUS_CONTROLLER_READY (1 << 7)
39
40 /* ALTERA_QSPI_CONTROLLER2_STATUS_REG bits */
41 #define STATUS_PROTECTION_POS 2
42 #define STATUS_PROTECTION_MASK 0x1F
43 #define STATUS_PROTECTION_EN_VAL 0x17
44 #define STATUS_PROTECTION_DIS_VAL 0x0
45
46 /* ALTERA_QSPI_CONTROLLER2_MEM_OP_REG bits */
47 #define MEM_OP_ERASE_CMD 0x00000002
48 #define MEM_OP_WRITE_EN_CMD 0x00000004
49 #define MEM_OP_SECTOR_OFFSET_BIT_POS 8
50 #define MEM_OP_UNLOCK_ALL_SECTORS 0x00000003
51 #define MEM_OP_LOCK_ALL_SECTORS 0x00000F03
52
53 #define NIOS2_QSPI_BLANK_WORD 0xFFFFFFFF
54
55 #define NIOS2_WRITE_BLOCK_SIZE 4
56
57 #define USEC_TO_MSEC(x) (x / 1000)
58
59 struct flash_nios2_qspi_config {
60 alt_qspi_controller2_dev qspi_dev;
61 struct k_sem sem_lock;
62 };
63
64 static const struct flash_parameters flash_nios2_qspi_parameters = {
65 .write_block_size = NIOS2_WRITE_BLOCK_SIZE,
66 .erase_value = 0xff,
67 };
68
69 static int flash_nios2_qspi_write_protection(const struct device *dev,
70 bool enable);
71
flash_nios2_qspi_erase(const struct device * dev,off_t offset,size_t len)72 static int flash_nios2_qspi_erase(const struct device *dev, off_t offset,
73 size_t len)
74 {
75 struct flash_nios2_qspi_config *flash_cfg = dev->data;
76 alt_qspi_controller2_dev *qspi_dev = &flash_cfg->qspi_dev;
77 uint32_t block_offset, offset_in_block, length_to_erase;
78 uint32_t erase_offset = offset; /* address of next byte to erase */
79 uint32_t remaining_length = len; /* length of data left to be erased */
80 uint32_t flag_status;
81 int32_t rc = 0, i, timeout, rc2;
82
83 k_sem_take(&flash_cfg->sem_lock, K_FOREVER);
84
85 rc = flash_nios2_qspi_write_protection(dev, false);
86 if (rc) {
87 goto qspi_erase_err;
88 }
89 /*
90 * check if offset is word aligned and
91 * length is with in the range
92 */
93 if (((offset + len) > qspi_dev->data_end) ||
94 (0 != (erase_offset &
95 (NIOS2_WRITE_BLOCK_SIZE - 1)))) {
96 LOG_ERR("erase failed at offset 0x%lx", (long)offset);
97 rc = -EINVAL;
98 goto qspi_erase_err;
99 }
100
101 for (i = offset/qspi_dev->sector_size;
102 i < qspi_dev->number_of_sectors; i++) {
103
104 if ((remaining_length <= 0U) ||
105 erase_offset >= (offset + len)) {
106 break;
107 }
108
109 block_offset = 0U; /* block offset in byte addressing */
110 offset_in_block = 0U; /* offset into current sector to erase */
111 length_to_erase = 0U; /* length to erase in current sector */
112
113 /* calculate current sector/block offset in byte addressing */
114 block_offset = erase_offset & ~(qspi_dev->sector_size - 1);
115
116 /* calculate offset into sector/block if there is one */
117 if (block_offset != erase_offset) {
118 offset_in_block = erase_offset - block_offset;
119 }
120
121 /* calculate the byte size of data to be written in a sector */
122 length_to_erase = MIN(qspi_dev->sector_size - offset_in_block,
123 remaining_length);
124
125 /* Erase sector */
126 IOWR_32DIRECT(qspi_dev->csr_base,
127 ALTERA_QSPI_CONTROLLER2_MEM_OP_REG,
128 MEM_OP_WRITE_EN_CMD);
129 IOWR_32DIRECT(qspi_dev->csr_base,
130 ALTERA_QSPI_CONTROLLER2_MEM_OP_REG,
131 (i << MEM_OP_SECTOR_OFFSET_BIT_POS)
132 | MEM_OP_ERASE_CMD);
133
134 /*
135 * poll the status register to know the
136 * completion of the erase operation.
137 */
138 timeout = ALTERA_QSPI_CONTROLLER2_1US_TIMEOUT_VALUE;
139 while (timeout > 0) {
140 /* wait for 1 usec */
141 k_busy_wait(1);
142
143 flag_status = IORD_32DIRECT(qspi_dev->csr_base,
144 ALTERA_QSPI_CONTROLLER2_FLAG_STATUS_REG);
145
146 if (flag_status & FLAG_STATUS_CONTROLLER_READY) {
147 break;
148 }
149
150 timeout--;
151 }
152
153 if ((flag_status & FLAG_STATUS_ERASE_ERROR) ||
154 (flag_status & FLAG_STATUS_PROTECTION_ERROR)) {
155 LOG_ERR("erase failed, Flag Status Reg:0x%x",
156 flag_status);
157 rc = -EIO;
158 goto qspi_erase_err;
159 }
160
161 /* update remaining length and erase_offset */
162 remaining_length -= length_to_erase;
163 erase_offset += length_to_erase;
164 }
165
166 qspi_erase_err:
167 rc2 = flash_nios2_qspi_write_protection(dev, true);
168
169 if (!rc) {
170 rc = rc2;
171 }
172
173 k_sem_give(&flash_cfg->sem_lock);
174 return rc;
175
176 }
177
flash_nios2_qspi_write_block(const struct device * dev,int block_offset,int mem_offset,const void * data,size_t len)178 static int flash_nios2_qspi_write_block(const struct device *dev,
179 int block_offset,
180 int mem_offset, const void *data,
181 size_t len)
182 {
183 struct flash_nios2_qspi_config *flash_cfg = dev->data;
184 alt_qspi_controller2_dev *qspi_dev = &flash_cfg->qspi_dev;
185 uint32_t buffer_offset = 0U; /* offset into data buffer to get write data */
186 int32_t remaining_length = len; /* length left to write */
187 uint32_t write_offset = mem_offset; /* offset into flash to write too */
188 uint32_t word_to_write, padding, bytes_to_copy;
189 uint32_t flag_status;
190 int32_t rc = 0;
191
192 while (remaining_length > 0) {
193 /* initialize word to write to blank word */
194 word_to_write = NIOS2_QSPI_BLANK_WORD;
195
196 /* bytes to pad the next word that is written */
197 padding = 0U;
198
199 /* number of bytes from source to copy */
200 bytes_to_copy = NIOS2_WRITE_BLOCK_SIZE;
201
202 /*
203 * we need to make sure the write is word aligned
204 * this should only be true at most 1 time
205 */
206 if (0 != (write_offset & (NIOS2_WRITE_BLOCK_SIZE - 1))) {
207 /*
208 * data is not word aligned calculate padding bytes
209 * need to add before start of a data offset
210 */
211 padding = write_offset & (NIOS2_WRITE_BLOCK_SIZE - 1);
212
213 /*
214 * update variables to account
215 * for padding being added
216 */
217 bytes_to_copy -= padding;
218
219 if (bytes_to_copy > remaining_length) {
220 bytes_to_copy = remaining_length;
221 }
222
223 write_offset = write_offset - padding;
224
225 if (0 != (write_offset &
226 (NIOS2_WRITE_BLOCK_SIZE - 1))) {
227 rc = -EINVAL;
228 goto qspi_write_block_err;
229 }
230 } else {
231 if (bytes_to_copy > remaining_length) {
232 bytes_to_copy = remaining_length;
233 }
234 }
235
236 /* Check memcpy lentgh is with in NIOS2_WRITE_BLOCK_SIZE */
237 if (padding + bytes_to_copy > NIOS2_WRITE_BLOCK_SIZE) {
238 rc = -EINVAL;
239 goto qspi_write_block_err;
240 }
241
242 /* prepare the word to be written */
243 memcpy((uint8_t *)&word_to_write + padding,
244 (const uint8_t *)data + buffer_offset,
245 bytes_to_copy);
246
247 /* enable write */
248 IOWR_32DIRECT(qspi_dev->csr_base,
249 ALTERA_QSPI_CONTROLLER2_MEM_OP_REG,
250 MEM_OP_WRITE_EN_CMD);
251
252 /* write to flash 32 bits at a time */
253 IOWR_32DIRECT(qspi_dev->data_base, write_offset, word_to_write);
254
255 /* check whether write operation is successful */
256 flag_status = IORD_32DIRECT(qspi_dev->csr_base,
257 ALTERA_QSPI_CONTROLLER2_FLAG_STATUS_REG);
258
259 if ((flag_status & FLAG_STATUS_PROGRAM_ERROR) ||
260 (flag_status & FLAG_STATUS_PROTECTION_ERROR)) {
261 LOG_ERR("write failed, Flag Status Reg:0x%x",
262 flag_status);
263 rc = -EIO; /* sector might be protected */
264 goto qspi_write_block_err;
265 }
266
267 /* update offset and length variables */
268 buffer_offset += bytes_to_copy;
269 remaining_length -= bytes_to_copy;
270 write_offset = write_offset + NIOS2_WRITE_BLOCK_SIZE;
271 }
272
273 qspi_write_block_err:
274 return rc;
275 }
276
flash_nios2_qspi_write(const struct device * dev,off_t offset,const void * data,size_t len)277 static int flash_nios2_qspi_write(const struct device *dev, off_t offset,
278 const void *data, size_t len)
279 {
280 struct flash_nios2_qspi_config *flash_cfg = dev->data;
281 alt_qspi_controller2_dev *qspi_dev = &flash_cfg->qspi_dev;
282 uint32_t block_offset, offset_in_block, length_to_write;
283 uint32_t write_offset = offset; /* address of next byte to write */
284 uint32_t buffer_offset = 0U; /* offset into source buffer */
285 uint32_t remaining_length = len; /* length of data left to be written */
286 int32_t rc = 0, i, rc2;
287
288 k_sem_take(&flash_cfg->sem_lock, K_FOREVER);
289
290 rc = flash_nios2_qspi_write_protection(dev, false);
291 if (rc) {
292 goto qspi_write_err;
293 }
294 /*
295 * check if offset is word aligned and
296 * length is with in the range
297 */
298 if ((data == NULL) || ((offset + len) > qspi_dev->data_end) ||
299 (0 != (write_offset &
300 (NIOS2_WRITE_BLOCK_SIZE - 1)))) {
301 LOG_ERR("write failed at offset 0x%lx", (long)offset);
302 rc = -EINVAL;
303 goto qspi_write_err;
304 }
305
306 for (i = offset/qspi_dev->sector_size;
307 i < qspi_dev->number_of_sectors; i++) {
308
309 if (remaining_length <= 0U) {
310 break;
311 }
312
313 block_offset = 0U; /* block offset in byte addressing */
314 offset_in_block = 0U; /* offset into current sector to write */
315 length_to_write = 0U; /* length to write to current sector */
316
317 /* calculate current sector/block offset in byte addressing */
318 block_offset = write_offset & ~(qspi_dev->sector_size - 1);
319
320 /* calculate offset into sector/block if there is one */
321 if (block_offset != write_offset) {
322 offset_in_block = write_offset - block_offset;
323 }
324
325 /* calculate the byte size of data to be written in a sector */
326 length_to_write = MIN(qspi_dev->sector_size - offset_in_block,
327 remaining_length);
328
329 rc = flash_nios2_qspi_write_block(dev,
330 block_offset, write_offset,
331 (const uint8_t *)data + buffer_offset,
332 length_to_write);
333 if (rc < 0) {
334 goto qspi_write_err;
335 }
336
337 /* update remaining length and buffer_offset */
338 remaining_length -= length_to_write;
339 buffer_offset += length_to_write;
340 write_offset += length_to_write;
341 }
342
343 qspi_write_err:
344 rc2 = flash_nios2_qspi_write_protection(dev, true);
345
346 if (!rc) {
347 rc = rc2;
348 }
349
350 k_sem_give(&flash_cfg->sem_lock);
351 return rc;
352 }
353
flash_nios2_qspi_read(const struct device * dev,off_t offset,void * data,size_t len)354 static int flash_nios2_qspi_read(const struct device *dev, off_t offset,
355 void *data, size_t len)
356 {
357 struct flash_nios2_qspi_config *flash_cfg = dev->data;
358 alt_qspi_controller2_dev *qspi_dev = &flash_cfg->qspi_dev;
359 uint32_t buffer_offset = 0U; /* offset into data buffer to get read data */
360 uint32_t remaining_length = len; /* length left to read */
361 uint32_t read_offset = offset; /* offset into flash to read from */
362 uint32_t word_to_read, bytes_to_copy;
363 int32_t rc = 0;
364
365 /*
366 * check if offset and length are within the range
367 */
368 if ((data == NULL) || (offset < qspi_dev->data_base) ||
369 ((offset + len) > qspi_dev->data_end)) {
370 LOG_ERR("read failed at offset 0x%lx", (long)offset);
371 return -EINVAL;
372 }
373
374 if (!len) {
375 return 0;
376 }
377
378 k_sem_take(&flash_cfg->sem_lock, K_FOREVER);
379
380 /* first unaligned start */
381 read_offset &= ~(NIOS2_WRITE_BLOCK_SIZE - 1U);
382 if (offset > read_offset) {
383 /* number of bytes from source to copy */
384 bytes_to_copy = NIOS2_WRITE_BLOCK_SIZE - (offset - read_offset);
385 if (bytes_to_copy > remaining_length) {
386 bytes_to_copy = remaining_length;
387 }
388 /* read from flash 32 bits at a time */
389 word_to_read = IORD_32DIRECT(qspi_dev->data_base, read_offset);
390 memcpy((uint8_t *)data, (uint8_t *)&word_to_read + offset -
391 read_offset, bytes_to_copy);
392 /* update offset and length variables */
393 read_offset += NIOS2_WRITE_BLOCK_SIZE;
394 buffer_offset += bytes_to_copy;
395 remaining_length -= bytes_to_copy;
396 }
397
398 /* aligned part, including unaligned end */
399 while (remaining_length > 0) {
400 /* number of bytes from source to copy */
401 bytes_to_copy = NIOS2_WRITE_BLOCK_SIZE;
402
403 if (bytes_to_copy > remaining_length) {
404 bytes_to_copy = remaining_length;
405 }
406
407 /* read from flash 32 bits at a time */
408 word_to_read = IORD_32DIRECT(qspi_dev->data_base, read_offset);
409 memcpy((uint8_t *)data + buffer_offset, &word_to_read,
410 bytes_to_copy);
411 /* update offset and length variables */
412 read_offset += bytes_to_copy;
413 buffer_offset += bytes_to_copy;
414 remaining_length -= bytes_to_copy;
415 }
416
417 k_sem_give(&flash_cfg->sem_lock);
418 return rc;
419 }
420
flash_nios2_qspi_write_protection(const struct device * dev,bool enable)421 static int flash_nios2_qspi_write_protection(const struct device *dev,
422 bool enable)
423 {
424 struct flash_nios2_qspi_config *flash_cfg = dev->data;
425 alt_qspi_controller2_dev *qspi_dev = &flash_cfg->qspi_dev;
426 uint32_t status, lock_val;
427 int32_t rc = 0, timeout;
428
429 /* set write enable */
430 IOWR_32DIRECT(qspi_dev->csr_base,
431 ALTERA_QSPI_CONTROLLER2_MEM_OP_REG,
432 MEM_OP_WRITE_EN_CMD);
433 if (enable) {
434 IOWR_32DIRECT(qspi_dev->csr_base,
435 ALTERA_QSPI_CONTROLLER2_MEM_OP_REG,
436 MEM_OP_LOCK_ALL_SECTORS);
437 lock_val = STATUS_PROTECTION_EN_VAL;
438 } else {
439 IOWR_32DIRECT(qspi_dev->csr_base,
440 ALTERA_QSPI_CONTROLLER2_MEM_OP_REG,
441 MEM_OP_UNLOCK_ALL_SECTORS);
442 lock_val = STATUS_PROTECTION_DIS_VAL;
443 }
444
445 /*
446 * poll the status register to know the
447 * completion of the erase operation.
448 */
449 timeout = ALTERA_QSPI_CONTROLLER2_1US_TIMEOUT_VALUE;
450 while (timeout > 0) {
451 /* wait for 1 usec */
452 k_busy_wait(1);
453
454 /*
455 * read flash flag status register before
456 * checking the QSPI status
457 */
458 IORD_32DIRECT(qspi_dev->csr_base,
459 ALTERA_QSPI_CONTROLLER2_FLAG_STATUS_REG);
460
461 /* read QPSI status register */
462 status = IORD_32DIRECT(qspi_dev->csr_base,
463 ALTERA_QSPI_CONTROLLER2_STATUS_REG);
464 if (((status >> STATUS_PROTECTION_POS) &
465 STATUS_PROTECTION_MASK) == lock_val) {
466 break;
467 }
468
469 timeout--;
470 }
471
472 if (timeout <= 0) {
473 LOG_ERR("locking failed, status-reg 0x%x", status);
474 rc = -EIO;
475 }
476
477 /* clear flag status register */
478 IOWR_32DIRECT(qspi_dev->csr_base,
479 ALTERA_QSPI_CONTROLLER2_FLAG_STATUS_REG, 0x0);
480 return rc;
481 }
482
483 static const struct flash_parameters *
flash_nios2_qspi_get_parameters(const struct device * dev)484 flash_nios2_qspi_get_parameters(const struct device *dev)
485 {
486 ARG_UNUSED(dev);
487
488 return &flash_nios2_qspi_parameters;
489 }
490
491 static const struct flash_driver_api flash_nios2_qspi_api = {
492 .erase = flash_nios2_qspi_erase,
493 .write = flash_nios2_qspi_write,
494 .read = flash_nios2_qspi_read,
495 .get_parameters = flash_nios2_qspi_get_parameters,
496 #if defined(CONFIG_FLASH_PAGE_LAYOUT)
497 .page_layout = (flash_api_pages_layout)
498 flash_page_layout_not_implemented,
499 #endif
500 };
501
flash_nios2_qspi_init(const struct device * dev)502 static int flash_nios2_qspi_init(const struct device *dev)
503 {
504 struct flash_nios2_qspi_config *flash_cfg = dev->data;
505
506 k_sem_init(&flash_cfg->sem_lock, 1, 1);
507 return 0;
508 }
509
510 struct flash_nios2_qspi_config flash_cfg = {
511 .qspi_dev = {
512 .data_base = EXT_FLASH_AVL_MEM_BASE,
513 .data_end = EXT_FLASH_AVL_MEM_BASE + EXT_FLASH_AVL_MEM_SPAN,
514 .csr_base = EXT_FLASH_AVL_CSR_BASE,
515 .size_in_bytes = EXT_FLASH_AVL_MEM_SPAN,
516 .is_epcs = EXT_FLASH_AVL_MEM_IS_EPCS,
517 .number_of_sectors = EXT_FLASH_AVL_MEM_NUMBER_OF_SECTORS,
518 .sector_size = EXT_FLASH_AVL_MEM_SECTOR_SIZE,
519 .page_size = EXT_FLASH_AVL_MEM_PAGE_SIZE,
520 }
521 };
522
523 DEVICE_DEFINE(flash_nios2_qspi,
524 CONFIG_SOC_FLASH_NIOS2_QSPI_DEV_NAME,
525 flash_nios2_qspi_init, NULL, &flash_cfg, NULL,
526 POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
527 &flash_nios2_qspi_api);
528
